Firestorm: LD2R (post-index, 4H) measurements

Code:

  ld2r { v0.4h, v1.4h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.006

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
63005	29289	226	2	1	5	0	3	1	0	0	5	0	4708	28614	0	1	17183	4006	1000	2008	1000	1000	2000	1000	5000	5001	23908	12	22741	29190	29330	3	10	4000	1000	2000	2000	2000	29138	29290	1	1	61001	1000	1000	1002	3	3	1002	0	1	1	1000	3	1	2	1	1	12931	9286	6917	3108	1	37	20551	3148	3808	9	40	34	28402	1000	16069	13403	14426	1000	2000	1000	29249	29272	29422	29251	29168
63004	29209	227	0	1	1	0	0	1	1	0	4	0	4562	28786	0	0	17120	4008	1000	2008	1000	1000	2000	1000	5000	5000	23916	5	22784	29041	29249	3	10	4000	1000	2000	2000	2000	29188	29206	1	1	61001	1000	1000	1002	3	2	1002	0	1	1	1000	3	1	3	1	1	13454	9245	6904	3113	1	40	20584	3223	3811	6	43	37	28523	1000	16276	13084	14637	1000	2000	1000	29377	29249	29246	29267	29199
63004	29305	226	0	1	1	0	1	1	0	0	4	0	4619	28723	0	0	17100	4008	1000	2008	1000	1000	2000	1000	5000	5000	23908	6	22758	29069	29294	3	10	4000	1000	2000	2000	2000	29166	29247	1	1	61001	1000	1000	1002	2	3	1002	0	1	1	1000	3	1	3	1	0	12996	9241	6992	3205	0	42	20596	3278	3811	13	45	41	28463	1000	16030	13198	14348	1000	2000	1000	29196	29384	29169	29230	29342
63004	29332	228	0	1	0	1	1	0	0	0	5	0	4653	28920	0	0	17200	4006	1000	2006	1000	1000	2000	1000	5000	5000	23911	4	22761	29126	29276	3	10	4000	1000	2000	2000	2000	29424	29742	1	1	61001	1000	1000	1002	1	3	1003	0	1	1	1000	2	1	2	1	1	13073	9233	6944	3130	0	36	20715	3429	3808	8	43	35	28693	1000	16389	13152	14550	1000	2000	1000	29602	29587	29250	29229	29415
63004	29443	227	0	1	0	1	0	1	0	0	3	0	4606	28720	0	0	17153	4008	1000	2008	1000	1000	2000	1000	5000	5000	23880	4	22730	29003	29161	3	10	4000	1000	2000	2000	2000	29103	29058	1	1	61001	1000	1000	1002	2	3	1003	0	0	2	1000	2	2	3	1	1	12943	9241	6907	3110	0	39	20437	3153	3813	7	38	42	28385	1000	16095	13419	14384	1000	2000	1000	29142	29302	29277	29150	29299
63004	29690	228	0	1	1	1	0	1	0	0	2	0	4629	28767	1	0	17072	4006	1000	2008	1000	1000	2000	1000	5000	5000	23900	7	22682	29114	29232	3	10	4000	1000	2000	2000	2000	29162	29093	1	1	61001	1000	1000	1001	2	3	1002	0	0	2	1001	2	1	3	1	1	12833	9154	6880	3090	1	38	20548	3035	3817	10	40	35	28351	1000	16506	13312	14521	1000	2000	1000	29130	29163	29274	29188	29272
63004	29294	218	0	1	0	1	1	0	1	1	4	0	4559	28753	0	1	17401	4008	1000	2008	1000	1000	2000	1000	5000	5000	23872	5	22744	29268	29333	3	10	4000	1000	2000	2000	2000	29238	29559	1	1	61001	1000	1000	1003	2	2	1002	0	1	1	1001	2	2	2	1	2	12924	9154	6839	3065	0	37	20665	3074	3816	10	37	34	28358	1000	16433	13437	14427	1000	2000	1000	29232	29225	29247	29182	29133
63004	29230	219	0	1	1	1	0	1	1	1	4	0	4573	28766	0	0	17134	4006	1000	2006	1000	1000	2000	1000	5000	5000	23896	8	22764	29084	29205	3	10	4000	1000	2000	2000	2000	29096	29086	1	1	61001	1000	1000	1002	1	2	1003	0	0	2	1000	2	2	3	1	1	12873	9050	6899	3119	0	35	20553	3039	3816	10	39	38	28398	1000	16301	13299	14534	1000	2000	1000	29304	29273	29302	29283	29255
63004	29199	220	0	1	1	1	1	1	1	0	4	0	4534	28722	1	0	17198	4008	1000	2006	1000	1000	2000	1000	5000	5000	23898	5	22768	29011	29253	3	10	4000	1000	2000	2000	2000	29122	29194	1	1	61001	1000	1000	1002	1	3	1003	0	1	2	1001	2	2	2	1	0	12870	9144	6924	3121	1	41	20665	3071	3811	7	40	39	28352	1000	16419	13235	14530	1000	2000	1000	29244	29218	29225	29293	29204
63004	29166	218	0	1	0	1	0	0	1	1	3	0	4518	28748	0	0	17125	4008	1000	2006	1000	1000	2000	1000	5000	5000	23899	2	22726	29054	29251	3	10	4000	1000	2000	2000	2000	29146	29067	1	1	61001	1000	1000	1001	2	2	1003	0	1	1	1001	2	1	3	1	1	13013	9431	6857	3102	0	35	20605	3053	3814	7	46	41	28378	1000	16480	13310	14447	1000	2000	1000	29280	29245	29210	29182	29264

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.4h, v1.4h }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	24	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140057	1086	0	0	0	0	0	0	1	0	0	16	0	0	0	0	140039	139577	25	90103	50100	30003	10000	40100	30000	10000	1236903	5331357	16114560	0	0	140030	140054	140035	130731	3	131154	80100	30200	10000	30000	60200	20000	30000	140054	140054	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	9	4	3	10000	0	0	1	0	0	0	0	0	3210	0	0	1	121	1	1	139724	50000	13	10	14	10000	20000	50100	140052	140052	140055	140052	140053
70204	140051	1085	0	0	0	0	0	0	1	0	0	13	0	0	0	0	140039	139593	25	90100	50100	30000	10000	40100	30000	10000	1236990	5331357	16114560	1	5	140029	140054	140051	130727	3	131157	80100	30200	10000	30000	60200	20000	30000	140054	140051	2	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	7	0	0	10000	1	0	1	0	0	0	0	0	3210	0	0	1	121	1	1	139724	50000	13	10	13	10000	20000	50100	140036	140055	140055	140036	140066
70204	140035	1085	0	0	0	0	0	0	0	0	0	1	0	0	0	0	140039	139593	25	90103	50100	30003	10000	40100	30139	11221	1299318	5331357	16114560	0	0	140030	140035	140055	130730	3	131157	80100	30200	10000	30000	60200	20000	30000	140035	140051	2	1	50201	100	99	100	40100	10000	10000	0	100	10001	0	1	10000	58	0	0	10001	1	0	1	0	0	0	0	0	3210	0	0	1	121	1	1	139721	50011	13	10	10	10000	20000	50100	140036	140036	140142	140036	140073
70204	140054	1085	0	0	0	0	0	0	0	0	0	0	0	0	0	0	140040	139596	25	90103	50100	30003	10000	40100	30000	10000	1236963	5331474	16114560	0	0	140030	140054	140054	130730	3	131157	80100	30200	10000	30000	60200	20000	30000	140054	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10001	64	0	0	10000	1	0	1	0	2	0	0	0	3210	0	0	1	121	1	1	139811	50000	0	10	10	10000	20000	50100	140053	140038	140055	140055	140049
70204	140054	1085	0	0	0	0	1	0	0	0	1	1	0	0	0	0	140039	139596	25	90103	50110	30003	10000	40100	30000	10000	1236999	5331357	16114560	0	0	140030	140054	140054	130730	3	131157	80100	30200	10000	30123	60200	20000	30000	140058	140035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	8	2	3	10000	1	0	1	0	0	0	0	0	3210	5	4	1	121	1	1	139724	50000	13	13	13	10000	20000	50100	140055	140052	140055	140055	140084
70204	140054	1086	0	0	0	0	0	0	0	0	0	1	0	0	0	0	140039	139596	25	90103	50100	30007	10000	40100	30000	10000	1236963	5331471	16114560	1	5	140027	140054	140051	130730	3	131157	80100	30200	10000	30000	60200	23150	35565	142445	140054	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	0	3210	0	0	1	121	1	1	139724	50000	13	10	13	10000	20000	50100	140052	140112	140056	140057	140040
70204	140051	1086	0	0	0	0	0	0	0	0	0	13	0	0	0	0	140136	139610	25	90103	50100	30003	10000	40100	30000	10000	1236903	5331510	16111598	0	0	140107	140035	140054	130729	3	131164	80100	30200	10000	30000	60200	20000	30000	140035	140035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	46	0	0	10000	1	0	1	0	0	0	0	0	3210	0	0	1	121	1	1	139725	50000	0	13	13	10000	20000	50100	140055	140055	140055	140144	140080
70204	140054	1085	0	0	0	0	0	0	0	0	0	1	0	0	0	0	140132	139596	25	90103	50100	30000	10000	40100	30000	10000	1236990	5331471	16119080	0	0	140098	140035	140055	130735	3	131157	80425	30200	10000	30000	60200	20000	30000	140054	140054	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	85	0	3	10000	1	0	1	0	0	0	0	0	3210	5	4	1	121	1	1	139724	50000	13	10	10	10000	20000	50100	140055	140054	140036	140148	140085
70204	140051	1085	0	0	0	0	0	0	0	0	0	13	0	0	0	0	140036	139593	25	90103	50100	30003	10000	40100	30000	10000	1236990	5331471	16114560	0	0	140030	140054	140035	130731	3	131157	80100	30200	10000	30000	60200	20000	30000	140051	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	84	0	0	10000	1	0	1	0	0	0	0	0	3210	5	4	1	121	1	1	139801	50010	0	10	13	10000	20000	50100	140055	140036	140153	140055	142717
70204	140322	1088	0	0	1	0	0	0	0	2	4	3697	2640	0	0	0	140405	139667	83	90180	50124	30019	10004	40399	30236	10158	1242133	5337572	16122268	0	0	140143	140238	140334	130812	30	131385	80713	30566	10081	30363	60448	20244	30367	140237	140375	3	1	50201	100	99	100	40100	10000	10000	0	100	10003	0	1	10006	137	0	3	10000	1	0	0	0	0	0	0	0	3210	5	4	1	121	1	1	139736	50000	13	10	10	10000	20000	50100	140052	140053	140052	140055	140058

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	24	3a	3f	49	4d	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140052	1085	0	0	0	0	0	0	0	0	1	0	0	0	0	140020	0	139651	0	25	90013	50010	30003	10000	40010	30000	10000	1245874	5332706	16115526	0	140027	0	140051	140035	130750	3	131210	80010	30020	10000	30000	60020	20000	30000	140054	140051	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10013	2	1	10004	0	1	0	16108	10008	1	0	1	0	0	0	3140	0	7	87	5	5	139723	50000	13	10	13	10000	20000	50010	140055	140055	140055	140057	140058
70024	140054	1085	0	0	0	0	0	0	0	0	1	0	0	0	0	140038	110	139657	0	51	90013	50010	30003	10000	40010	30000	10000	1245916	5333446	16115998	0	140031	0	140057	140144	130756	3	131213	80010	30020	10000	30000	60512	20000	30000	140052	140051	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	1	10000	1	0	1	0	0	0	3140	6	3	87	6	5	139723	50000	13	10	10	10000	20000	50010	140055	140036	140055	140055	140036
70024	140054	1085	0	0	0	0	0	0	0	1	1	0	0	0	0	140039	0	139660	638	25	90013	50010	30003	10000	40010	30000	10038	1245943	5332823	16113346	0	140011	0	140051	140051	130750	3	131216	80010	35164	10486	30000	60020	20000	30000	140054	140051	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10005	0	1	0	138	10000	1	0	1	0	0	0	3186	0	5	87	3	5	139725	50000	0	10	14	10000	20000	50010	140052	140036	140055	140036	140148
70024	140054	1086	0	0	0	0	0	1	0	0	1	0	0	1	0	140039	0	139635	0	25	90013	50010	30007	10000	40010	30000	10000	1245943	5332706	16113346	0	140027	0	140051	140051	130750	3	131211	80010	30020	10000	30000	60020	20000	30000	140051	140051	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	0	3140	0	6	87	5	5	139726	50010	10	10	10	10000	20000	50010	140053	140184	140058	140057	140053
70024	140054	1085	0	0	0	0	0	0	0	0	144	0	0	1	0	140042	0	139651	0	25	90013	50010	30003	10001	40010	30000	10000	1245934	5333327	16113346	0	140027	0	140054	140054	130750	3	131213	80010	30020	10000	30000	60020	20080	30000	140054	140051	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	0	0	0	0	0	3140	0	8	87	6	6	139724	50000	13	10	10	10000	20000	50010	140055	140055	140053	140055	140052
70024	140035	1085	0	0	0	0	1	0	0	0	1	0	0	1	0	140039	0	139651	0	25	90013	50010	30011	10001	40010	30000	10000	1245961	5334307	16163421	0	140030	0	140051	140056	130753	3	131210	80010	30020	10000	30000	60020	20080	30000	140051	140035	1	1	50021	10	9	0	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	0	3	10000	1	0	0	0	0	0	3140	0	5	87	5	7	139726	50000	10	10	11	10000	20000	50010	140058	140058	140062	140059	140058
70024	140060	1086	1	1	1	0	0	0	0	0	14	0	0	1	0	140026	0	139641	0	25	90016	50010	30006	10000	40010	30000	10039	1245997	5333669	16115841	0	140036	0	140041	140061	130727	3	131219	80010	30020	10000	30000	60020	20000	30000	140155	140058	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10002	1	1	10002	0	1	0	1	10000	1	1	1	1	1	0	3140	0	5	87	5	5	139729	50000	10	10	10	10000	20000	50010	140061	140061	140106	140058	140059
70024	140154	1086	1	0	1	1	0	0	0	0	134	0	0	1	0	140042	0	139635	0	25	90010	50010	30000	10000	40153	30000	10000	1245943	5333441	16113346	0	140030	0	140035	140051	130750	3	131210	80010	30020	10000	30000	60020	20080	30000	140054	140051	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	3	10000	1	0	1	0	0	0	3140	0	7	87	4	3	139707	50000	10	0	0	10000	20000	50010	140055	140036	140036	140052	140055
70024	140035	1085	0	0	0	0	0	0	0	0	1	0	1	0	0	140020	0	139654	0	25	90013	50010	30000	10000	40010	30000	10000	1245916	5333641	16115297	1	140027	0	140057	140054	130753	3	131329	80010	30020	10000	30000	60020	20080	30000	140054	140035	1	1	50021	10	9	0	10	40010	10000	10000	1	10	10000	0	0	10000	0	0	0	0	10000	1	0	1	0	0	0	3140	0	5	87	8	7	139723	50000	13	15	10	10000	20000	50010	140052	141472	140147	140233	140317
70024	140145	1087	0	1	0	1	0	1	2	2	397	176	1	0	0	140231	0	139703	0	81	90046	50034	30011	10002	40433	30353	10038	1250708	5338090	16119888	0	140176	0	140055	141198	131431	3	131213	80313	30020	10040	30122	60260	20000	30120	140144	140035	2	1	50021	10	9	0	10	40010	10000	10000	0	10	10001	0	1	10001	0	0	7	3233	10002	1	0	0	0	0	0	3140	0	6	87	6	7	139723	50000	10	13	0	10000	20000	50010	140036	140052	140036	140036	140052

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.4h, v1.4h }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0063

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst simd store (99)	inst ldst (9b)	9d	9e	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140069	1125	0	0	0	0	0	0	0	13	0	0	0	0	140052	139565	25	90103	50100	30003	10000	40100	30000	10000	1237083	5331499	16114980	140039	140063	140064	130741	3	131158	80100	30200	10000	30000	60200	20000	30000	140063	140066	1	1	50201	100	99	100	40100	10000	0	10000	0	0	100	10000	0	1	10001	0	2	3260	10001	1	1	0	0	3233	1	80	1	1	139735	50019	10	0	9	10000	20000	50100	140340	140221	140258	140345	140227
70204	140354	1127	1	0	1	0	0	1	3	396	264	0	0	0	140417	139770	83	90150	50139	30021	10001	40535	30354	10079	1251232	5335301	16120277	140169	140447	140351	130741	3	131158	80100	30200	10000	30000	60200	20000	30000	140056	140066	1	1	50201	100	99	100	40100	10000	0	10000	0	0	100	10000	0	1	10000	2	0	16523	10000	0	1	0	0	3210	1	80	1	1	139735	50000	9	9	9	10000	20000	50100	140064	140064	140064	140109	140067
70204	140112	1125	0	1	0	0	0	1	0	1	0	0	0	0	140040	139565	25	90100	50100	30003	10000	40100	30000	10000	1244902	5330530	16116477	140039	140063	140063	130739	3	131168	80100	30200	10000	30000	60200	20000	30000	140063	140055	1	1	50201	100	99	100	40100	10000	0	10000	0	0	100	10000	0	1	10000	0	0	0	10000	1	1	1	0	3210	1	80	1	1	139813	50000	0	6	9	10000	20000	50100	140064	140064	140056	140064	140064
70204	140063	1125	0	0	0	0	0	0	0	1	0	0	0	0	140048	139607	25	90103	50100	30003	10000	40100	30000	10000	1244911	5330530	16116236	140039	140063	140063	130739	3	131207	80100	30200	10000	30000	60200	20000	30000	140066	140066	1	1	50201	100	99	100	40100	10000	0	10000	1	0	100	10000	0	1	10000	1	0	18	10000	1	1	0	0	3210	1	80	1	1	139736	50000	9	10	9	10000	20000	50100	140071	140064	140067	140056	140064
70204	140063	1125	0	0	0	0	0	0	0	1	0	0	0	0	140040	139565	54	90103	50100	30003	10000	40100	30000	10000	1244902	5330530	16116708	140031	140066	140063	130739	3	131207	80100	30200	10000	30000	60200	20000	30000	140063	140066	1	1	50201	100	99	100	40100	10000	0	10000	0	0	100	10000	0	1	10000	1	0	6	10000	0	1	0	0	3210	1	80	1	1	139738	50000	6	9	9	10000	20000	50100	140071	140383	140067	140377	140064
70204	140063	1125	0	1	0	0	0	0	0	25	0	0	0	0	140048	139568	25	90103	50100	30003	10000	40100	30000	10000	1237096	5330530	16114980	140039	140063	140064	130740	3	131207	80100	30200	10000	30000	60200	20000	30000	140063	140066	1	1	50201	100	99	100	40100	10000	0	10000	0	0	100	10000	0	0	10000	0	0	6	10000	1	1	0	0	3210	1	80	1	1	139957	50000	9	9	9	10000	20000	50100	140056	140064	140064	140064	140068
70204	140066	1124	0	0	0	0	0	0	0	13	0	0	0	0	140048	139607	25	90103	50100	30003	10000	40100	30000	10000	1244902	5331917	16116236	140042	140066	140063	130731	3	131207	80100	30200	10000	30000	60200	20000	30000	140063	140063	1	1	50201	100	99	100	40100	10000	0	10000	0	0	100	10000	0	1	10000	1	0	0	10000	1	1	0	0	3210	1	80	1	1	139735	50000	9	9	9	10000	20000	50100	140066	140064	140064	140064	140064
70204	140091	1124	0	0	0	0	0	0	0	13	0	0	0	0	140048	139597	25	90103	50121	30003	10000	40100	30000	10000	1244902	5330530	16114980	140039	140055	140063	130731	3	131207	80100	30200	10000	30000	60200	20000	30000	140055	140068	1	1	50201	100	99	100	40100	10000	0	10000	0	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	3210	1	80	1	1	139735	50000	9	6	0	10000	20000	50100	140064	140064	140067	140064	140064
70204	140066	1125	0	0	0	0	0	0	0	21	0	0	0	0	140040	139597	25	90103	50100	30003	10002	40100	30000	10000	1244902	5331499	16116236	140039	140063	140063	130740	3	131168	80100	30200	10000	30000	60200	20000	30000	140064	140066	1	1	50201	100	99	100	40100	10000	0	10000	0	0	100	10002	0	1	10007	0	0	9346	10005	1	0	2	0	3280	1	329	3	1	141704	50049	9	9	9	10000	20000	50100	140251	140344	140250	140246	140252
70204	140416	1127	0	0	0	0	0	3	1	264	264	0	0	0	140229	139568	25	90100	50100	30000	10000	40100	30000	10000	1237083	5330608	16115448	140039	140063	140055	130739	3	131207	80100	30200	10000	30000	60200	20000	30000	140063	140061	1	1	50201	100	99	100	40100	10000	26	10000	0	2	100	10000	208	1	10000	6	0	3	10000	1	1	0	0	3233	1	80	1	1	139735	50000	0	6	9	10000	20000	50100	140162	140064	140064	140064	140067

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0058

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	18	19	1e	1f	23	24	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch call (8e)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140054	1086	0	1	0	1	0	0	1	0	0	0	0	140043	139659	25	90013	50010	30003	10000	40010	30000	10000	1245979	5333668	16115517	0	140103	0	140154	140159	130757	30	131268	80605	31727	11086	31325	60742	20324	30122	140427	140339	2	1	50021	10	0	9	0	10	40010	10000	10000	1	10	10017	2	1	10005	0	1	0	6520	10003	1	1	2	3210	0	3	102	5	8	141542	50020	13	13	13	10000	20000	50010	140148	140264	140434	140232	140333
70024	140350	1088	0	0	1	0	1	3	265	264	0	0	0	140043	139658	25	90010	50010	30003	10000	40010	30000	10000	1245979	5333591	16113460	0	140034	0	140106	140058	130735	3	131217	80010	30020	10000	30000	60020	20000	30000	140056	140054	1	1	50021	10	0	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	1	0	0	10000	1	1	0	3140	0	5	87	6	6	139731	50000	13	10	13	10000	20000	50010	140059	140059	140037	140059	140055
70024	140058	1086	0	0	0	0	0	0	0	0	0	0	0	140043	139658	25	90013	50010	30003	10000	40010	30000	10000	1245979	5333591	16116177	0	140020	0	140036	140058	130762	3	131217	80010	30020	10000	30000	60020	20000	30000	140058	140054	1	1	50021	10	0	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	1	0	3	10000	1	1	0	3140	0	4	87	4	4	139730	50000	13	10	13	10000	20000	50010	140059	140059	140059	140059	140037
70024	140036	1085	0	0	0	0	0	0	1	0	0	0	0	140021	139658	25	90013	50010	30000	10000	40010	30000	10000	1245856	5333591	16115751	0	140034	0	140058	140058	130757	3	131217	80010	30020	10000	30000	60020	20000	30000	140060	140058	1	1	50021	10	0	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	1	0	6	10000	1	1	0	3140	0	2	87	5	4	139708	50000	13	10	14	10000	20000	50010	140059	140059	140060	140059	140059
70024	140058	1085	0	0	0	0	0	0	0	0	0	0	0	140046	139636	25	90013	50010	30003	10000	40010	30000	10000	1245979	5333591	16115517	0	140034	0	140058	140061	130757	3	131217	80010	30020	10000	30000	60020	20000	30000	140060	140058	1	1	50021	10	0	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	3140	0	7	145	3	3	140151	50000	13	10	13	10000	20000	50010	140059	140059	140059	140038	140059
70024	140058	1086	1	0	1	0	5	5	883	584	0	0	0	140043	139658	25	90013	50010	30003	10000	40010	30000	10000	1245997	5333591	16115517	0	140034	0	140058	140058	130759	3	131217	80010	30020	10000	30000	60020	20000	30000	140058	140054	1	1	50021	10	0	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	0	1	0	3140	0	2	87	3	3	139730	50000	0	10	13	10000	20000	50010	140037	140059	140059	140060	140060
70024	140054	1086	0	0	0	0	0	0	1	0	0	0	0	140043	139658	25	90013	50010	30003	10000	40010	30000	10000	1245979	5333591	16115517	0	140012	0	140058	140058	130757	3	131217	80010	30020	10000	30000	60020	20000	30000	140058	140054	1	1	50021	10	0	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	3140	0	3	87	3	5	139730	50000	10	13	13	10000	20000	50010	140059	140062	140059	140059	140059
70024	140058	1087	0	0	0	0	0	0	0	0	0	0	0	140021	139654	25	90013	50010	30000	10000	40010	30000	10000	1245979	5333591	16113460	0	140034	0	140059	140061	130757	3	131217	80010	30020	10000	30000	60020	20000	30000	140058	140054	1	1	50021	10	0	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	1	0	3	10000	0	1	0	3140	0	3	87	5	4	139730	50000	13	13	13	10000	20000	50010	140037	140059	140060	140059	140059
70024	140106	1086	0	0	0	0	0	0	1	0	0	0	0	140043	139658	25	90013	50010	30003	10000	40010	30000	10000	1245997	5333630	16115517	0	140255	0	140342	140248	130850	29	131354	80905	30383	10080	30364	60506	20158	30243	140243	140354	3	1	50021	10	0	9	0	10	40010	10000	10000	0	10	10025	0	1	10026	1	0	2	71085	10000	1	0	0	3210	0	5	142	6	4	139955	50040	13	10	13	10000	20000	50010	140337	140244	140432	140253	140251
70024	140308	1087	0	0	1	0	0	0	1	0	0	0	0	140043	139658	25	90013	50010	30003	10000	40010	30000	10000	1245979	5333591	16113460	0	140034	0	140058	140058	130757	3	131218	80010	30020	10000	30000	60020	20000	30000	140061	140054	1	1	50021	10	0	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	1	0	0	10000	1	1	0	3140	0	3	87	2	4	139730	50000	13	13	13	10000	20000	50010	140059	140059	140059	140059	140059

Test 4: throughput

Count: 8

Code:

  ld2r { v0.4h, v1.4h }, [x6], x8
  ld2r { v0.4h, v1.4h }, [x6], x8
  ld2r { v0.4h, v1.4h }, [x6], x8
  ld2r { v0.4h, v1.4h }, [x6], x8
  ld2r { v0.4h, v1.4h }, [x6], x8
  ld2r { v0.4h, v1.4h }, [x6], x8
  ld2r { v0.4h, v1.4h }, [x6], x8
  ld2r { v0.4h, v1.4h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	d9	da	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240205	80041	643	0	1	0	1	0	1	0	0	0	0	80026	1	0	6	2	25	320100	80100	160040	80000	80100	160000	80000	4408215	3758376	9826340	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	14	80010	0	0	10	80013	6	0	13	14	0	5110	1	16	0	0	1	1	80038	1	80000	9	6	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	0	0	0	0	0	0	0	20	0	0	80026	1	6	6	46	25	320140	80100	160040	80000	80100	160000	80000	4408215	3758376	9826345	80022	80041	80182	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80014	1	0	9	80010	6	1	14	14	0	5110	1	16	0	0	1	1	80038	0	80000	9	11	80000	160000	80100	80184	80042	80042	80042	80042
240204	80041	644	0	0	0	0	0	1	0	29	0	0	80026	0	6	6	0	25	320138	80205	160040	80000	80378	160000	80000	4410529	3761926	9826337	80127	80181	80182	49924	0	31	50052	320100	200	80133	160000	200	163780	164026	82284	82448	18	1	80201	100	99	100	100	80000	80000	1	100	80266	0	18	80102	67	0	3543	80191	0	1	13	18	4	5127	1	25	0	0	1	1	80143	1	80094	11	6	80000	160000	80100	82017	80042	80323	80325	80183
240204	80181	644	0	0	1	0	0	1	2	1049	264	1	80306	1	6	6	139	114	320874	80284	160392	80092	80381	160537	80133	4412819	3761921	9843803	80022	80041	80182	49924	16	3	50080	320100	200	80000	160265	200	160000	160000	80183	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80000	2	0	80014	0	0	13	80013	6	1	10	0	0	5110	1	16	0	0	2	1	80038	1	80185	7	9	80000	160000	80100	80042	80042	80042	80183	80042
240204	80041	643	0	0	0	0	0	0	0	32	0	0	80026	1	6	6	44	25	320146	80201	160040	80000	80100	160272	80000	4408215	3758359	9834739	80022	80041	80041	49924	20	3	50080	320100	200	80000	160265	200	160000	160000	80181	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80014	1	0	9	80013	6	0	10	18	0	5110	1	16	0	0	1	1	80143	1	80000	9	9	80000	160000	80100	80042	80042	80182	80042	80042
240204	80041	643	0	0	0	0	0	0	0	20	0	0	80026	1	6	6	0	25	320140	80100	160040	80000	80100	160000	80000	4408215	3758376	9825900	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80013	0	0	19	80013	6	1	10	18	0	5110	1	16	0	0	1	1	80038	0	80000	9	9	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	0	0	0	0	0	0	0	19	0	0	80026	1	6	6	0	25	320138	80100	160040	80000	80100	160000	80000	4408215	3758376	9825967	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80014	0	4	0	80014	6	1	9	18	0	5110	1	16	0	0	1	2	80038	1	80000	9	9	80000	160000	80100	80042	80432	80042	80430	80042
240204	80430	642	0	0	0	0	0	0	0	32	0	0	80026	1	6	0	5	25	320146	80100	160000	80000	80100	160000	80000	4408197	3758379	9826291	80129	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160272	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80089	0	18	80017	0	0	21	80000	6	1	13	0	0	5110	1	16	0	1	4	2	80038	1	80000	13	0	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	0	0	0	0	0	0	0	35	0	0	80026	1	0	6	4	25	320148	80100	160046	80000	80100	160000	80000	4408215	3758375	9825673	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80017	1	0	20	80018	6	1	14	18	0	5110	1	16	0	0	1	1	80038	1	80000	10	13	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	0	0	0	1	1	0	0	44	0	0	80026	1	6	6	4	25	320138	80100	160040	80000	80100	160000	80000	4408209	3758378	9826343	80022	80041	80041	49924	0	3	49999	320100	200	80000	164036	212	161326	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	14	80014	1	0	17	82046	6	0	10	18	0	5110	1	24	0	0	2	1	80038	0	80095	9	6	80000	160000	80100	80042	80042	80042	80042	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4e	4f	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240025	80041	620	1	0	0	0	1	0	0	0	24	0	1	0	0	80026	1	6	0	0	0	0	25	320010	80010	160000	80000	80010	160000	80000	4407591	3758361	9826287	0	80022	80041	80041	49947	0	3	50021	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	0	80014	0	2	0	0	80013	0	1	14	18	0	5022	2	15	2	2	80038	0	80000	13	10	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	620	0	0	0	0	1	1	0	0	23	0	1	0	0	80026	1	6	6	0	0	0	25	320050	80010	160048	80000	80010	160000	80000	4407687	3758366	9825741	0	80022	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80017	0	0	0	0	80000	6	0	0	22	0	5020	1	15	1	2	80038	1	80000	13	10	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	621	0	0	0	0	0	0	0	0	20	0	1	0	1	80026	0	6	6	0	0	2	25	320058	80010	160048	80000	80010	160000	80000	4407696	3758361	9825745	0	80022	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80000	0	0	0	14	80014	6	0	14	18	0	5022	2	15	1	2	80038	1	80000	10	10	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	621	0	0	0	0	0	0	0	0	12	0	1	0	0	80026	1	6	6	0	0	0	25	320050	80010	160000	80000	80010	160000	80000	4407696	3758361	9825741	0	80022	80041	80041	49947	0	3	50087	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80013	0	0	0	1315	80088	6	1	14	22	0	5022	2	15	2	2	80038	0	80000	10	0	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	620	0	0	0	0	0	0	0	0	24	0	1	0	0	80026	1	6	6	0	0	0	25	320058	80010	160048	80000	80010	160000	80000	4407617	3758371	9826285	0	80022	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	18	80017	0	0	0	17	80000	6	1	13	18	0	5022	2	15	2	2	80038	1	80000	13	13	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	620	0	0	0	0	0	0	0	0	0	0	1	0	1	80026	0	0	6	0	4	0	25	320050	80010	160000	80000	80010	160000	80000	4407696	3758371	9825745	0	80022	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80014	0	0	0	0	80018	6	1	0	22	0	5022	1	15	1	2	80038	1	80000	0	10	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	621	0	0	0	0	1	1	0	0	0	0	1	0	1	80026	1	6	6	0	0	0	25	320056	80010	160046	80000	80010	160000	80000	4407696	3758361	9825741	0	80022	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80000	0	0	0	14	80013	6	1	14	0	0	5022	1	15	2	1	80038	0	80000	0	13	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	621	0	0	0	0	1	1	0	0	24	0	1	0	0	80026	0	6	6	0	0	0	25	320058	80010	160048	80000	80010	160000	80000	4407682	3758376	9825741	0	80022	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80014	0	0	0	0	80014	6	1	13	18	0	5022	2	15	3	2	80038	0	80000	10	10	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	620	0	0	0	0	0	0	0	0	36	0	0	1	1	80026	1	6	6	0	0	0	25	320058	80010	160000	80000	80010	160000	80000	4407696	3758378	9826277	0	80022	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	0	80018	0	0	0	17	80000	0	1	18	22	0	5022	1	15	1	1	80038	1	80000	13	10	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	622	0	0	0	0	0	1	0	0	20	0	0	1	1	80026	0	0	6	0	0	0	68	320010	80010	160000	80000	80010	160000	80000	4407696	3758376	9825154	0	80022	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80181	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80014	0	0	0	0	80018	6	1	18	0	0	5022	2	16	1	1	80038	1	80000	10	10	80000	160000	80010	80042	80042	80042	80042	80042

LD2R (post-index, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations