Firestorm: LD2R (post-index, 4S) measurements

Code:

  ld2r { v0.4s, v1.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.004

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	0e	0f	18	1e	23	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
63005	29291	219	3	6	0	2	1	0	1	0	2	0	4619	28842	0	0	17217	4004	1000	2004	1000	1000	2000	1000	5000	5000	23862	0	22728	29073	29333	3	10	4000	1000	2000	2000	2000	29143	29121	1	1	61001	1000	1000	1000	2	1000	0	0	1000	2	0	2	13056	9518	7027	3182	0	43	20612	3133	3821	15	51	45	28417	1000	16168	13367	14201	1000	2000	1000	29338	29302	29298	29333	29291
63004	29340	219	0	0	0	0	0	0	0	0	2	0	4668	28878	0	0	17148	4004	1000	2004	1000	1000	2000	1000	5000	5000	23866	2	22694	29094	29263	3	10	4000	1000	2000	2000	2000	29186	29201	1	1	61001	1000	1000	1000	2	1000	0	0	1000	2	0	2	13180	9277	6864	3182	0	49	20606	3225	3824	15	50	54	28604	1000	16213	13260	14576	1000	2000	1000	29254	29243	29194	29264	29198
63004	29267	220	1	0	0	0	0	0	0	0	11	0	4640	28774	0	0	17119	4004	1000	2004	1000	1000	2000	1000	5000	5000	23864	0	22740	29055	29245	3	10	4000	1000	2000	2000	2000	29130	29115	1	1	61001	1000	1000	1000	2	1000	0	0	1000	2	0	2	13211	9395	6947	3195	0	45	20534	3050	3823	10	54	56	28580	1000	16351	13273	14404	1000	2000	1000	29261	29182	29198	29276	29241
63004	29301	219	0	0	0	0	0	0	0	0	0	0	4724	28760	0	0	17238	4004	1000	2004	1000	1000	2000	1000	5000	5000	23849	0	22712	29090	29296	3	10	4000	1000	2000	2000	2000	29153	29296	1	1	61001	1000	1000	1000	2	1000	0	0	1000	2	0	2	12862	9178	6988	3106	1	44	20579	3121	3823	17	51	46	28372	1000	15939	13348	14495	1000	2000	1000	29367	29308	29241	29292	29346
63004	29293	220	0	0	0	0	0	0	1	0	0	0	4764	28763	0	0	17127	4004	1000	2004	1000	1000	2000	1000	5000	5000	23868	0	22709	29056	29192	3	10	4000	1000	2000	2000	2000	29122	29124	1	1	61001	1000	1000	1000	2	1000	0	0	1000	2	0	2	12906	9145	6870	3209	0	56	20637	3091	3825	10	54	51	28520	1000	16254	13284	14482	1000	2000	1000	29187	29262	29250	29260	29329
63004	29300	219	1	0	0	0	0	1	1	1	0	0	4587	28787	0	0	17140	4004	1000	2004	1000	1000	2000	1000	5000	5000	23858	0	22732	28994	29322	3	10	4000	1000	2000	2000	2000	29137	29261	1	1	61001	1000	1000	1000	2	1000	0	0	1000	2	0	2	12917	9097	6950	3102	0	48	20677	3107	3817	13	48	55	28359	1000	16276	13346	14428	1000	2000	1000	29331	29302	29208	29275	29256
63004	29321	219	1	0	0	0	0	0	0	0	0	0	4631	28786	0	0	17154	4004	1000	2004	1000	1000	2000	1000	5000	5000	23860	0	22756	29066	29291	3	10	4000	1000	2000	2000	2000	29144	29199	1	1	61001	1000	1000	1000	2	1000	0	3	1000	2	0	2	12908	9232	6884	3147	0	44	20562	3115	3824	12	54	52	28513	1000	16311	13044	14311	1000	2000	1000	29242	29242	29223	29325	29297
63004	29262	219	0	0	0	0	0	0	0	0	2	0	4558	28767	0	0	17110	4004	1000	2004	1000	1000	2000	1000	5000	5000	23856	0	22751	29055	29230	3	10	4000	1000	2000	2000	2000	29211	29181	1	1	61001	1000	1000	1000	2	1000	0	0	1000	2	0	2	13019	9108	6923	3198	0	45	20572	3094	3815	12	44	46	28370	1000	16100	13110	14319	1000	2000	1000	29306	29331	29218	29245	29256
63004	29309	227	0	0	0	0	0	0	0	0	0	0	4547	28778	0	0	17190	4004	1000	2004	1000	1000	2000	1000	5000	5000	23856	0	22689	29099	29367	3	10	4000	1000	2000	2000	2000	29106	29094	1	1	61001	1000	1000	1000	2	1000	0	0	1000	2	0	2	12805	9384	6857	3091	0	47	20524	3089	3824	10	46	77	28528	1000	16280	13309	14363	1000	2000	1000	29294	29327	29318	29349	29233
63004	29247	219	0	0	0	0	0	1	0	0	0	0	4669	28775	0	0	17219	4004	1000	2004	1000	1000	2000	1000	5000	5000	23848	0	22722	29067	29196	3	10	4000	1000	2000	2000	2000	29103	29228	1	1	61001	1000	1000	1000	2	1000	0	0	1000	2	0	2	13172	9185	6908	2994	3	50	20586	3080	3822	12	57	46	28369	1000	16320	13282	14434	1000	2000	1000	29363	29341	29232	29310	29265

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.4s, v1.4s }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	24	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140198	1087	1	0	0	0	0	0	0	3	2	503	176	0	0	140237	139602	83	90121	50100	30007	10002	40100	30230	10040	1240595	5331549	16120345	0	141550	142180	141937	131393	0	43	131291	81018	30567	10121	30234	61180	20080	30366	140250	140227	3	1	50201	100	99	100	40100	10000	10000	0	100	10003	2	1	10004	1	3	9850	10003	1	0	1	0	0	3210	1	121	1	1	139730	50000	15	10	13	10000	20000	50100	140058	140058	140058	140061	140036
70204	140054	1085	0	1	0	0	0	0	0	0	0	1	0	0	1	140045	139603	54	90106	50100	30003	10000	40100	30000	10000	1236990	5331699	16115305	1	140030	140060	140063	130736	0	3	131157	80100	30200	10000	30000	60200	20000	30000	140060	140057	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10002	0	0	1	10000	1	1	1	1	1	3210	1	121	1	1	139730	50000	13	13	13	10000	20000	50100	140063	140061	140061	140061	140060
70204	140060	1085	0	0	0	0	0	1	1	0	0	14	0	0	0	140045	139602	25	90106	50100	30006	10000	40100	30000	10000	1236903	5331471	16115305	0	140030	140060	140062	130736	0	3	131157	80445	30200	10000	30000	60200	20000	30000	140060	140060	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10001	0	0	0	10000	0	1	1	0	0	3210	1	121	1	1	139724	50000	13	13	0	10000	20000	50100	140061	140061	140061	140061	140055
70204	140056	1085	0	1	1	0	1	1	0	0	0	1	0	0	0	140045	139602	25	90106	50100	30006	10000	40100	30000	10000	1236990	5331471	16114560	0	140030	140060	140060	130736	0	3	131158	80100	30200	10000	30000	60200	20000	30000	140060	140057	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10000	1	0	1	10000	1	0	1	1	1	3210	1	121	1	1	139730	50000	0	12	13	10000	20000	50100	140061	140062	140061	140061	140055
70204	140054	1085	0	0	0	0	0	0	0	0	0	1	0	0	0	140045	139602	25	90106	50100	30006	10000	40100	30000	10000	1236990	5331471	16114560	0	140030	140060	140041	130717	0	3	131185	80100	30200	10000	30000	60200	20000	30000	140061	140060	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10001	1	0	1	10000	1	1	1	0	0	3210	1	121	1	1	139724	50000	13	15	0	10000	20000	50100	140055	140061	140042	140042	140042
70204	140055	1086	0	0	0	0	0	0	0	0	0	2	0	0	1	140020	139604	25	90103	50100	30000	10000	40100	30000	10000	1237044	5332385	16115305	0	140036	140060	140060	130730	0	3	131157	80100	30200	10000	30000	60200	20000	30000	140035	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10001	0	0	0	10000	1	0	0	1	1	3210	1	121	1	1	139705	50000	10	10	13	10000	20000	50100	140055	140055	140058	140065	140061
70204	140051	1086	0	0	1	0	1	0	0	0	0	13	0	0	1	140045	139596	25	90103	50100	30003	10000	40100	30000	10000	1237044	5331471	16114560	0	140036	140035	140054	130736	0	3	131160	80100	30200	10000	30000	60200	20000	30000	140054	140055	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	0	1	10000	0	0	0	10000	0	0	1	0	0	3210	1	121	1	1	139730	50000	13	10	13	10000	20000	50100	140055	140055	140055	140061	140055
70204	140054	1085	0	0	0	0	0	0	0	0	0	13	0	0	1	140020	139596	25	90103	50100	30003	10000	40100	30000	10000	1239824	5331699	16114560	0	140036	140055	140054	130736	0	3	131163	80100	30200	10000	30000	60200	20000	30000	140060	140057	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10001	1	0	1	10000	1	1	1	0	0	3210	1	121	1	1	139730	50000	0	10	13	10000	20000	50100	140243	140430	140239	140246	140333
70204	140377	1087	0	0	0	0	0	0	0	2	3	398	176	0	0	140045	139703	112	90130	50137	30016	10003	40527	30236	10116	1244334	5336145	16124319	0	140258	140392	140253	130792	0	29	131329	80714	30444	10120	30366	60690	20244	30487	140224	140335	2	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	1	10001	0	0	3	10000	1	0	1	1	1	3210	1	121	1	1	139724	50000	13	12	0	10000	20000	50100	140061	140061	140061	140061	140055
70204	140061	1086	0	1	1	0	0	0	0	0	0	1	0	0	0	140046	139602	25	90106	50100	30003	10000	40100	30000	10000	1236999	5331471	16115305	0	140011	140041	140060	130736	0	3	131157	80100	30200	10000	30000	60200	20000	30000	140060	140052	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10002	0	1	6435	10001	1	1	1	0	0	3210	1	121	1	0	139724	50000	14	13	13	10000	20000	50100	140055	140055	140055	140055	140061

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0061

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140061	1086	0	1	0	1	0	0	1	1	0	0	15	0	0	0	0	0	140046	0	1	139653	25	90016	50010	30006	10000	40010	30000	10000	1246015	5333251	16118233	0	0	140043	140061	140061	130758	3	131217	80010	30020	10000	30000	60020	20000	30000	140062	140053	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	2	10003	0	0	2	10001	1	2	0	1	1	0	3140	0	3	87	3	3	139728	50000	0	6	6	10000	20000	50010	140054	140057	140057	140057	140054
70024	140056	1086	0	1	0	0	1	1	1	1	0	0	2	0	0	0	0	0	140048	0	0	139663	25	90016	50010	30006	10000	40010	30000	10000	1246006	5333251	16116309	0	0	140025	140049	140056	130760	3	131215	80010	30020	10000	30000	60020	20000	30000	140049	140061	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	2	10002	0	0	2	10000	0	2	1	1	1	0	3140	0	3	87	3	3	139729	50000	0	6	6	10000	20000	50010	140062	140050	140050	140050	140062
70025	140061	1086	0	1	0	0	0	0	0	0	0	0	2	0	1	0	0	1	140034	0	0	139661	25	90016	50010	30006	10000	40010	30000	10000	1245898	5333251	16115020	0	0	140032	140061	140056	130748	3	131215	80010	30020	10000	30000	60020	20000	30000	140056	140049	1	1	50021	10	9	10	40010	10000	10000	1	10	10003	1	2	10003	0	0	1	10001	1	2	0	1	0	0	3140	0	2	87	4	3	139733	50000	9	10	0	10000	20000	50010	140062	140057	140050	140050	140050
70024	140049	1086	0	1	0	1	0	1	0	0	0	0	3	0	0	0	0	0	140042	0	0	139661	25	90016	50010	30006	10000	40010	30000	10000	1245934	5333520	16115415	0	0	140025	140056	140056	130748	3	131215	80010	30020	10000	30000	60020	20000	30000	140063	140061	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	2	1	10002	0	0	23	10000	0	1	1	1	1	0	3140	0	4	87	4	3	139733	50000	0	6	9	10000	20000	50010	140050	140062	140062	140062	140062
70024	140061	1085	0	1	0	0	0	0	1	0	0	0	14	0	0	0	0	0	140034	0	0	139649	25	90016	50010	30006	10000	40010	30000	10000	1245934	5333251	16115415	0	0	140029	140049	140056	130760	3	131208	80309	30020	10000	30000	60020	20000	30000	140061	140063	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	2	10003	1	2	5	10001	1	1	1	1	1	0	3140	0	2	87	2	2	139733	50000	6	6	6	10000	20000	50010	140062	140050	140050	140062	140062
70024	140061	1085	0	1	0	1	0	0	0	0	0	0	15	0	0	0	0	0	140046	1	0	139651	25	90019	50010	30009	10000	40010	30000	10000	1245988	5333707	16115020	0	0	140037	140061	140049	130748	3	131220	80010	30020	10000	30000	60020	20000	30000	140056	140061	1	1	50021	10	9	10	40010	10000	10000	1	10	10002	1	0	10002	0	1	2	10001	1	2	1	1	0	0	3140	0	2	87	2	2	139728	50000	0	0	6	10000	20000	50010	140050	140062	140062	140144	140057
70024	140049	1085	0	1	0	2	1	0	0	1	0	0	3	0	0	1	0	0	140044	1	0	139649	25	90016	50010	30009	10000	40010	30000	10000	1245961	5333290	16115020	0	0	140025	140154	140061	130755	3	131220	80010	30020	10000	30000	60020	20000	30000	140049	140061	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	0	10002	0	1	2	10000	1	2	1	1	0	0	3140	0	2	87	2	2	139733	50000	9	0	6	10000	20000	50010	140062	140054	140054	140062	140063
70024	140059	1086	0	1	0	0	0	0	1	0	0	0	2	0	0	0	0	0	140037	1	1	139661	25	90016	50010	30006	10000	40010	30000	10000	1245898	5333517	16115415	0	0	140032	140149	140061	130748	3	131215	80010	30020	10000	30000	60020	20000	30000	140049	140049	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	2	10006	0	2	2	10001	1	2	1	1	3	0	3140	0	2	87	4	2	139733	50000	0	6	6	10000	20000	50010	140057	140050	140062	140062	140054
70024	140049	1085	0	1	0	0	1	1	0	0	1	0	2	0	0	0	0	0	140046	1	1	139661	53	90019	50010	30006	10000	40010	30000	10000	1246006	5333290	16115415	0	0	140037	140144	140061	130748	3	131220	80010	30020	10000	30000	60020	20000	30000	140061	140053	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	1	10001	0	1	1	10000	0	2	1	1	0	0	3140	0	2	87	3	2	139734	50000	0	6	9	10000	20000	50010	140062	140057	140063	140062	140062
70024	140056	1086	0	1	0	0	2	1	0	0	0	0	134	88	0	0	0	0	140133	1	0	139638	83	90034	50023	30014	10001	40010	30120	10079	1269583	5380957	16278069	0	0	140175	140346	140238	130827	29	131407	80909	30507	10080	30362	60750	20080	30365	140334	140335	3	1	50021	10	9	10	40010	10000	10000	0	10	10034	1	0	10008	0	3	9707	10005	1	2	1	1	0	0	3233	0	5	104	3	4	139881	50000	6	0	6	10000	20000	50010	140062	140062	140063	140050	140062

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.4s, v1.4s }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0063

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140055	1086	0	1	0	0	0	1	0	1	0	0	0	140048	139613	53	90103	50100	30003	10000	40100	30000	10000	1244902	5331499	16116236	140042	140064	140156	130739	0	3	131207	80100	30200	10040	30000	60200	20000	30000	140099	140093	1	1	50201	100	99	0	100	40100	10000	10000	0	100	10000	0	1	10000	0	1	0	3	10000	1	1	0	3210	1	121	1	1	139735	50000	9	6	9	10000	20000	50100	140065	140064	140064	140064	140064
70204	140063	1086	0	0	1	0	0	0	0	25	0	0	0	140051	139565	25	90103	50100	30003	10000	40241	30000	10000	1244911	5330647	16116236	140039	140063	140063	130739	0	3	131169	80100	30200	10000	30000	60200	20000	30000	140173	140065	1	1	50201	100	99	0	100	40100	10000	10000	0	100	10003	0	0	10000	0	1	0	3	10000	1	1	0	3210	1	121	1	1	139725	50000	9	9	9	10000	20000	50100	140067	140064	140066	140064	140056
70204	140066	1086	0	0	0	0	0	0	0	43	0	0	0	140051	139565	25	90103	50100	30007	10000	40100	30000	10000	1244911	5330647	16116236	140041	140066	140063	130731	0	3	131207	80100	30200	10000	30000	60200	20000	30123	140121	140066	1	1	50201	100	99	0	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	0	3210	1	106	1	1	139735	50000	9	6	9	10000	20000	50100	140064	140064	140064	140064	140067
70204	140063	1086	0	0	0	0	0	0	0	13	0	0	0	140048	139565	25	90103	50100	30003	10001	40100	30000	10000	1244902	5330530	16107932	140039	140063	140063	130739	0	3	131207	80100	30200	10000	30000	60448	20000	30000	140153	140069	1	1	50201	100	99	0	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	0	3210	1	107	1	1	139735	50000	9	9	9	10000	20000	50100	140064	140064	140064	140064	140067
70204	140112	1085	0	0	0	0	0	0	0	133	0	0	0	140048	139565	25	90103	50100	30003	10002	40100	30000	10000	1244902	5330530	16116236	140039	140065	140055	130739	0	3	131209	80100	30200	10000	30000	60200	20080	30000	140146	140065	1	1	50201	100	99	0	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	3	10000	1	1	0	3210	2	121	1	1	139735	50000	9	9	9	10000	20000	50100	140064	140065	140064	140064	140072
70204	140063	1086	0	0	0	0	0	0	0	1	0	1	0	140049	139597	25	90103	50100	30006	10000	40100	30000	10000	1237096	5331499	16114980	140039	140063	140063	130754	0	3	131207	80100	30200	10000	30000	60494	20000	30000	140139	140074	1	1	50201	100	99	0	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	0	3210	1	121	1	1	139725	50000	9	6	9	10000	20000	50100	140064	140064	140064	140064	140067
70204	140063	1086	0	0	0	0	0	0	0	1	0	0	0	140048	139565	25	90120	50100	30003	10000	40100	30000	10000	1244902	5330530	16116236	140031	140063	140063	130739	7	3	131169	80100	30200	10000	30000	60200	20000	30000	140099	140434	1	1	50201	100	99	0	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	0	3210	1	121	1	1	139725	50000	9	6	0	10000	20000	50100	140064	140065	140056	140064	140056
70204	140063	1085	0	0	1	0	1	4	2	396	176	0	0	140328	139785	82	90103	50110	30004	10002	40243	30238	10000	1250224	5333267	16122468	140180	140321	140315	130781	0	45	131262	80713	30321	10160	30358	60690	20244	30482	140291	140342	4	1	50201	100	99	0	100	40100	10000	10000	0	100	10001	0	0	10003	2	0	0	3194	10000	1	1	0	3256	1	121	1	1	139736	50000	9	0	0	10000	20000	50100	140102	140064	140056	140064	140064
70204	140067	1086	0	0	0	0	0	0	0	1	0	0	0	140048	139565	25	90103	50100	30003	10000	40100	30000	10000	1244902	5330530	16116236	140039	140055	140063	130739	0	3	131207	80100	30200	10000	30000	60200	20000	30000	140085	140063	1	1	50201	100	99	0	100	40100	10000	10000	0	100	10000	0	1	10000	0	2	0	0	10000	1	1	0	3210	1	121	1	1	139736	50000	9	6	9	10000	20000	50100	140056	140067	140056	140064	140067
70204	140066	1085	0	0	0	0	0	0	0	0	0	0	0	140048	139565	25	90103	50100	30003	10000	40100	30000	10000	1237096	5330530	16116236	140031	140063	140071	130739	0	3	131207	80100	30200	10000	30000	60200	20000	30000	140138	140076	1	1	50201	100	99	0	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	0	3	10000	0	1	0	3210	1	121	1	1	139736	50000	9	6	9	10000	20000	50100	140067	140064	140064	140064	140095

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0063

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	24	3a	3f	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140046	1085	1	0	0	0	1	1	0	0	14	0	0	0	0	140048	0	139663	25	90016	50010	30006	10000	40010	30000	10000	1246024	5333782	16116528	0	140037	0	140063	140063	130730	3	131223	80010	30020	10000	30000	60020	20000	30000	140063	140060	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	1	1	10001	1	0	1	10000	1	1	1	1	0	0	3140	5	91	4	4	139732	50000	10	13	13	10000	20000	50010	140045	140064	140064	140064	140064
70024	140063	1085	1	0	1	0	0	0	0	0	1	0	0	0	0	140048	0	139644	25	90016	50010	30006	10000	40010	30000	10000	1246024	5333782	16116528	0	140036	0	140063	140044	130730	3	131199	80010	30020	10000	30000	60020	20000	30000	140060	140044	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	1	1	10001	0	0	1	10000	1	1	0	1	0	0	3140	5	91	5	4	139716	50000	13	10	0	10000	20000	50010	140045	140064	140064	140045	140061
70024	140044	1085	1	1	1	2	0	0	0	0	2	0	0	0	0	140049	0	139663	25	90016	50010	30006	10000	40010	30000	10000	1246024	5333782	16116528	0	140039	0	140044	140063	130762	3	131219	80010	30020	10000	30000	60020	20000	30000	140047	140060	1	1	50021	10	9	10	40010	10000	10000	1	10	10004	1	0	10002	0	1	1	10000	0	1	1	1	2	0	3140	4	87	4	4	139737	50000	0	10	13	10000	20000	50010	140045	140045	140045	140064	140061
70024	140066	1086	1	0	0	1	0	0	0	0	14	0	0	0	0	140049	0	139630	25	90016	50010	30006	10000	40010	30000	10000	1246789	5333668	16182519	0	140036	0	140512	140455	131161	3	131199	80010	30020	10000	30610	60502	20000	30000	140063	140044	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	1	10002	0	0	1	10000	1	1	0	1	0	0	3140	4	87	4	4	139735	50000	13	13	13	10000	20000	50010	140064	140065	140064	140064	140061
70024	140045	1085	1	0	1	1	0	0	0	0	11	0	0	0	0	140048	0	139644	25	90013	50010	30006	10000	40010	30000	10000	1246024	5334317	16116177	0	140039	0	140063	140063	130762	3	131222	80010	30020	10000	30000	60020	20000	30000	140064	140061	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	0	10001	1	0	7	10000	1	1	1	1	0	0	3140	4	87	5	5	139735	50000	13	0	13	10000	20000	50010	140064	140064	140045	140065	140045
70024	140044	1086	1	0	0	1	0	0	0	0	2	0	0	0	0	140045	0	139644	25	90016	50020	30006	10000	40010	30000	10000	1246024	5333782	16116177	0	140039	0	140060	140063	130768	3	131222	80010	30020	10000	30124	60020	20000	30000	140063	140044	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	1	10001	0	2	1	10000	1	1	1	1	0	0	3140	5	87	5	4	139816	50000	13	0	0	10000	20000	50010	140061	140064	140064	140064	140061
70024	140054	1086	1	0	0	2	0	1	0	1	2	0	0	0	0	140048	0	139663	25	90033	50010	30003	10000	40010	30000	10000	1246024	5333782	16116294	0	140020	0	140044	140162	130759	3	131222	80010	30143	10000	30000	60020	20000	30000	140044	140063	1	1	50021	10	9	10	40010	10000	10000	1	10	10001	2	1	10002	2	1	1	10000	1	1	1	1	0	0	3140	4	87	5	5	139735	50000	13	13	13	10000	20000	50010	140066	140064	140064	140064	140061
70024	140063	1085	1	0	0	0	0	0	0	0	14	0	0	0	0	140048	0	139663	25	90013	50010	30006	10000	40010	30000	10000	1246789	5333668	16116177	0	140039	0	140063	140063	130762	3	131222	80010	30020	10000	30000	60020	20000	30000	140063	140060	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	1	10001	0	1	1	10000	1	1	1	1	1	0	3140	4	91	4	5	139735	50010	13	13	13	10000	20000	50010	140068	140064	140164	140062	140065
70024	140063	1085	1	0	0	0	0	0	0	0	11	0	0	0	0	140146	0	139624	25	90016	50010	30006	10000	40010	30000	10000	1246024	5333782	16119423	0	140039	0	140063	140064	130762	3	131222	80010	30020	10040	30000	60020	20000	30122	140158	140063	2	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	1	10001	0	0	1	10000	1	1	1	1	3	0	3164	5	107	4	4	139947	50022	0	10	13	10000	20000	50010	140162	140343	140165	140155	140247
70024	142167	1103	1	0	1	2	0	1	4	3	398	176	0	0	0	140333	0	139663	25	90013	50010	30006	10000	40010	30000	10000	1246024	5331725	16116294	0	140023	0	140045	140060	130762	3	131224	80010	30020	10000	30000	60020	20000	30000	140044	140063	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	1	10002	0	1	1	10000	1	1	1	1	1	0	3140	4	87	5	5	139736	50000	13	10	13	10000	20000	50010	140064	140045	140064	140045	140061

Test 4: throughput

Count: 8

Code:

  ld2r { v0.4s, v1.4s }, [x6], x8
  ld2r { v0.4s, v1.4s }, [x6], x8
  ld2r { v0.4s, v1.4s }, [x6], x8
  ld2r { v0.4s, v1.4s }, [x6], x8
  ld2r { v0.4s, v1.4s }, [x6], x8
  ld2r { v0.4s, v1.4s }, [x6], x8
  ld2r { v0.4s, v1.4s }, [x6], x8
  ld2r { v0.4s, v1.4s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240205	80041	621	1	0	1	1	0	0	0	0	0	20	0	1	0	1	80026	1	6	6	4	25	320140	80100	160040	80000	80100	160000	80000	4407946	3758362	9826200	0	80022	80041	80041	49924	0	3	49999	320642	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	15	80013	0	0	148	80014	6	1	10	18	2	5112	0	5	16	7	5	80038	0	80000	9	6	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	620	1	0	0	1	1	0	0	0	0	19	0	0	0	1	80026	0	6	6	0	25	320140	80100	160176	80000	80100	160000	80000	4408215	3758376	9826353	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80181	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	14	80010	0	0	171	80000	6	0	10	0	0	5112	0	5	16	5	5	80038	1	80000	9	6	80000	160000	80100	80042	80042	80042	80042	80181
240204	80041	620	1	0	0	1	0	1	1	0	0	0	0	1	0	1	80026	1	6	0	0	25	320100	80100	160040	80000	80100	160000	80000	4408172	3758361	9826355	0	80022	80041	80041	49924	0	32	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	14	80110	0	0	184	80000	6	1	0	18	0	5112	0	3	16	5	4	80038	0	80000	10	6	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	620	1	0	0	1	0	0	1	0	0	31	0	0	0	1	80026	1	0	6	0	25	320100	80100	160040	80000	80100	160000	80000	4408203	3758360	9825411	0	80022	80041	80041	49924	0	3	49999	320100	200	80133	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	14	80013	1	0	178	80013	6	0	9	18	0	5113	0	5	16	5	5	80038	1	80000	9	9	80000	160000	80100	80184	80042	80042	80042	80042
240204	80041	624	1	0	0	1	0	1	0	0	0	19	0	1	0	1	80026	1	0	0	0	25	320140	80196	160040	80000	80100	160000	80000	4408215	3758375	9826353	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	2	1	80201	100	99	100	100	80000	80000	1	100	80000	0	0	80014	1	0	18	80013	0	1	10	18	0	5112	0	4	16	5	5	80038	0	80000	6	6	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	620	1	0	0	1	0	1	1	0	0	19	0	1	0	1	80026	0	6	6	0	25	320100	80100	160040	80000	80100	160000	80000	4408194	3758371	9826337	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	14	80000	0	0	137	80014	0	0	14	18	0	5112	0	5	16	3	5	80038	0	80000	6	6	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	622	1	0	0	1	0	0	0	0	0	31	0	0	0	1	80026	0	6	6	0	25	320140	80100	160038	80000	80100	160000	80000	4408199	3758359	9826353	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80000	0	0	187	80009	6	1	14	18	0	5112	0	5	16	5	5	80038	1	80000	9	6	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	621	1	1	0	1	0	0	0	0	0	12	0	0	0	1	80026	1	0	6	44	25	320138	80100	160032	80000	80100	160000	80000	4408194	3758361	9825411	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160269	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80014	0	0	145	80000	6	0	9	18	0	5112	0	3	16	6	5	80038	0	80000	6	6	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	620	1	0	0	1	0	0	0	0	0	31	0	0	0	1	80026	1	6	6	0	25	320140	80100	160216	80000	80100	160000	80000	4408212	3758361	9825411	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80181	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	14	80013	0	0	156	80000	0	1	10	18	0	5112	0	4	16	3	5	80038	1	80000	6	9	80000	160000	80100	80042	80042	80042	80042	80042
240204	80603	620	1	0	0	1	0	0	0	0	0	12	0	0	1	1	80026	1	6	6	0	25	320140	80100	160000	80000	80100	160000	80000	4408215	3758376	9826181	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	14	80010	7	0	155	80010	0	1	14	18	0	5112	0	5	16	3	5	80038	1	80000	9	6	80000	160000	80100	80042	80042	80042	80042	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	18	19	1e	1f	23	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d0	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240025	80041	620	1	0	0	0	1	0	0	32	0	0	0	80182	1	6	6	1	2	25	320072	80010	160062	80000	80010	160000	80000	4407692	3758373	9826285	0	80022	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80007	7	23	80026	0	1	29	80018	6	1	26	23	6	0	0	5020	0	0	1	15	1	1	80038	0	80000	10	9	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	620	1	1	0	1	0	0	0	32	0	0	0	80026	1	6	6	1	2	25	320072	80010	160064	80000	80010	160000	80000	4407692	3758374	9827218	0	80022	80041	80041	49947	0	3	50022	320010	20	80133	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80008	7	23	80027	1	0	1190	80018	6	1	25	23	7	0	0	5020	0	0	1	15	3	1	80038	1	80000	9	9	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	620	1	0	0	1	0	0	0	31	0	0	0	80026	1	6	6	1	6	25	320072	80102	160064	80000	80010	160000	80000	4407692	3758377	9827216	0	80022	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	2	1	80021	10	9	10	10	80000	80000	0	10	80006	7	23	80025	0	0	26	80019	6	1	26	23	6	0	0	5020	0	0	1	17	1	1	80038	0	80000	9	9	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	621	1	0	0	0	0	0	0	32	0	0	0	80026	1	6	6	1	10	25	320072	80010	160064	80000	80010	160000	80000	4407692	3758374	9827216	0	80022	80041	80041	49947	0	3	50021	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80007	6	23	80025	0	0	25	80019	6	1	25	23	7	1	0	5020	0	0	1	15	1	1	80038	1	80000	9	9	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	620	1	1	0	0	0	0	0	32	0	0	1	80026	1	6	6	1	2	25	320072	80010	160062	80000	80010	160000	80000	4407692	3758377	9827061	0	80022	80044	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80006	7	23	80032	1	0	29	80018	6	1	26	23	6	0	0	5020	0	0	2	15	1	1	80038	1	80000	9	9	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	620	1	0	0	0	0	0	0	31	0	0	0	80168	1	6	6	1	57	70	320802	80197	160242	80090	80680	165058	82406	4422202	3761944	9853749	0	80136	80179	80333	49975	20	31	50103	320541	20	80269	160265	20	160538	160265	80183	80322	3	1	80021	10	9	10	10	80000	80000	1	10	80007	13	23	80026	0	0	26	80107	6	1	26	23	6	3	0	5039	0	0	1	37	1	1	80144	0	80196	9	9	80000	160000	80010	80042	81778	80042	80042	80182
240024	80181	621	1	1	0	0	0	1	0	163	88	0	0	80166	1	6	6	1	2	25	320074	80102	160062	80000	80010	160000	80263	4407692	3761830	9826173	0	80022	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80007	7	23	80026	0	1	26	80018	6	1	26	23	7	0	0	5020	0	0	2	15	1	1	80038	0	80000	9	9	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	621	1	1	0	1	0	0	0	32	0	0	0	80026	1	6	6	1	2	25	320074	80010	160064	80000	80010	160000	80000	4407686	3758373	9827216	0	80022	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80008	6	23	80026	0	0	26	80018	6	1	26	23	7	0	0	5020	0	0	1	15	1	1	80038	1	80000	9	9	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	620	1	0	0	0	0	0	0	42	0	0	0	80026	1	6	6	1	0	25	320072	80010	160062	80000	80010	160000	80000	4407692	3758377	9827216	0	80022	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80007	7	23	80026	1	1	26	80023	6	1	25	23	7	0	0	5020	0	0	1	15	1	1	80038	1	80000	9	9	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	621	1	1	0	0	0	0	0	31	0	0	0	80026	1	6	6	1	2	25	320072	80010	160064	80000	80010	160000	80000	4407676	3758377	9827216	0	80022	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80006	8	23	80025	0	1	25	80019	6	1	26	23	6	1	1	5020	0	0	1	15	1	1	80038	0	80000	9	9	80000	160000	80010	80042	80042	80042	80042	80042

LD2R (post-index, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations