Firestorm: LD2 (multiple, 2D) measurements

Code:

  ld2 { v0.2d, v1.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.006

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	1f	22	23	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
64005	29288	219	5	1	4	1	0	1	0	0	0	6	0	1	0	4589	28841	0	2	0	17165	4006	2006	2000	2000	2000	10000	23870	5	0	0	22788	29068	29327	3	10	4000	2000	2000	2000	4000	29124	29075	1	1	61001	1000	1000	1	2004	4	4	2004	0	0	1	2	2002	4	2	4	2	0	13424	9216	6853	3296	2	74	20304	3083	3816	11	60	56	28348	16481	13514	14975	2000	2000	29322	29298	29303	29396	29375
64004	29254	219	4	1	0	1	0	1	0	0	0	6	0	0	0	4545	28838	0	2	2	17011	4008	2008	2000	2000	2000	10000	23919	2	0	0	22916	29186	29348	3	10	4000	2000	2000	2000	4000	29190	29098	1	1	61001	1000	1000	0	2003	4	4	2003	0	0	1	4	2000	4	2	6	2	2	12804	9189	6895	3097	0	60	20359	3007	3813	14	60	51	28333	16313	13487	15127	2000	2000	29289	29413	29385	29380	29347
64004	29399	219	6	1	1	1	0	0	0	0	0	8	0	0	0	4703	28787	0	2	0	17114	4008	2008	2000	2000	2000	10000	23912	7	0	0	22767	29110	29338	3	10	4000	2000	2000	2000	4000	29099	29066	1	1	61001	1000	1000	0	2002	2	4	2006	0	0	0	2	2002	4	2	4	2	0	12949	9168	6865	3023	2	56	20296	3090	3812	12	60	51	28442	16484	13521	15014	2000	2000	29350	29215	29334	29321	29330
64004	29390	219	6	1	0	1	0	1	1	1	0	62	132	0	0	4552	28916	0	0	0	17145	4008	2008	2000	2000	2000	10001	23883	2	0	0	22818	29089	29278	3	10	4000	2000	2000	2000	4000	29208	29124	1	1	61001	1000	1000	0	2003	3	6	2002	0	0	0	2	2002	4	4	6	2	2	12980	9168	6951	3073	2	59	20178	3126	3811	19	64	57	28410	16327	13543	15135	2000	2000	29307	29347	29282	29276	29181
64004	29281	218	7	1	0	1	0	1	0	0	0	8	0	0	0	4544	28756	0	0	0	17140	4008	2008	2000	2000	2000	10000	23904	4	0	0	22761	29149	29235	3	10	4000	2000	2000	2000	4000	29133	29163	1	1	61001	1000	1000	0	2004	2	4	2002	0	0	0	2	2001	4	8	4	2	1	12898	9061	6922	3079	4	54	20366	3090	3816	15	57	53	28374	16485	13545	14922	2000	2000	29322	29289	29222	29234	29326
64004	29260	220	7	1	0	1	0	1	1	1	0	10	0	0	0	4652	28832	0	0	0	16997	4008	2008	2000	2000	2000	10003	23924	4	0	0	22847	29137	29202	3	28	4000	2000	2000	2000	4000	29111	29203	1	1	61001	1000	1000	0	2003	3	4	2002	0	0	1	485	2000	4	4	4	2	0	12953	9088	6927	3066	0	65	20269	3059	3812	12	63	64	28372	16537	13371	15137	2000	2000	29229	29141	29288	29203	29309
64004	29383	219	3	1	0	0	0	1	0	0	0	8	0	1	0	4578	28904	2	2	1	16975	4006	2008	2000	2000	2002	10010	23890	1	0	0	22937	29080	29277	17	10	4000	2000	2000	2000	4000	29187	29146	1	1	61001	1000	1000	0	2002	3	4	2002	0	0	0	5	2000	6	2	6	2	2	13099	9212	6892	3146	3	58	20223	3119	3812	10	62	59	28734	16121	13576	14828	2000	2000	29297	29175	29200	29291	29284
64004	29259	219	8	1	0	0	0	0	1	1	0	6	0	0	0	4532	28851	0	2	2	17177	4008	2008	2000	2000	2000	10000	23886	2	0	0	22822	29091	29345	3	10	4000	2000	2000	2000	4000	29126	29195	1	1	61001	1000	1000	0	2004	2	4	2004	0	0	1	5	2000	4	2	4	2	1	12973	9134	6907	3104	2	58	20196	3086	3813	18	53	58	28427	16371	13302	15019	2000	2000	29302	29352	29280	29243	29310
64004	29215	220	4	1	0	1	0	1	0	1	0	6	0	0	0	4486	28810	0	2	0	16998	4006	2010	2000	2000	2000	10000	23899	3	0	0	22801	29041	29237	3	10	4000	2000	2000	2000	4000	29183	29219	1	1	61001	1000	1000	0	2004	2	4	2006	0	0	0	6	2000	4	4	6	2	0	13068	9116	6908	3111	1	70	20293	3059	3811	11	61	63	28495	16485	13335	14961	2000	2000	29301	29380	29301	29305	29209
64004	29322	219	7	1	0	1	0	0	0	0	0	7	0	0	0	4668	28823	0	0	0	17190	4008	2006	2000	2000	2000	10000	23924	5	0	0	22872	28982	29419	3	10	4000	2000	2000	2000	4000	29098	29132	2	1	61001	1000	1000	0	2003	2	4	2004	0	0	0	2	2000	4	4	4	2	0	13053	9244	6880	3151	1	62	20226	3088	3817	10	59	66	28372	16392	13452	14890	2000	2000	29328	29271	29232	29339	29286

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.2d, v1.2d }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80205	140051	1049	0	0	1	1	0	0	2	0	1	0	0	0	140036	84775	129686	25	90103	40100	30000	20000	30100	30000	20000	12044185	6692068	12182779	1	140011	140051	140084	129505	3	129934	80100	30200	20000	30000	60200	20000	50000	140051	140036	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	0	0	0	20000	2	2	2	0	0	0	0	3210	2	16	1	1	139791	40000	10	0	10	20000	20000	40100	140036	140052	140052	140036	140052
80204	140051	1049	0	0	0	0	0	0	0	0	1	0	0	0	140036	84775	129686	25	90103	40100	30013	20000	30100	30002	20000	12043796	6691876	12182602	0	140023	140047	140047	129520	6	129925	80102	30203	20004	30005	60206	20004	50009	140047	140047	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	0	0	0	20000	2	0	0	0	1	1	1	3217	1	16	0	0	139803	40000	0	0	6	20000	20000	40100	140048	140048	140048	140048	140048
80204	140047	1085	0	0	1	1	32	32	4097	2728	0	1	0	0	142882	95842	130953	839	90573	40332	30131	20064	32726	32790	21550	12164382	6770750	12310277	0	141564	141661	142054	129979	3	129918	80100	30200	20000	30000	60200	20000	50000	140047	140047	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	2	20000	2	0	0	20000	2	0	2	0	0	0	0	3210	1	16	1	1	139787	40000	6	6	6	20000	20000	40100	140049	140048	140048	140048	140048
80204	140047	1049	0	0	0	0	0	0	14	0	0	1	0	0	140032	84771	129688	25	90103	40100	30000	20000	30100	30000	20000	12043837	6691876	12182337	1	140023	140047	140047	129501	3	129932	80100	30200	20000	30000	60200	20000	50155	140139	140051	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	2	20007	1	0	3	20000	2	0	0	0	0	0	0	3210	1	16	1	1	139787	40000	6	6	6	20000	20000	40100	140048	140038	140049	140048	140048
80204	140039	1099	0	0	0	0	0	0	14	0	0	1	0	0	140032	84771	129682	25	90100	40100	30000	20000	30100	30000	20000	12043837	6691290	12182337	0	140023	140047	140035	129489	3	129930	80100	30200	20000	30000	60574	20062	50000	140047	140047	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	0	0	0	20000	2	0	0	0	0	0	0	3210	1	16	1	1	139787	40008	0	6	6	20000	20000	40100	140050	140048	140048	140036	140048
80204	140035	1049	0	0	0	0	3	1	278	88	0	0	0	0	140032	84771	129682	25	90100	40100	30000	20000	30100	30000	20000	12043837	6691876	12181242	1	140023	140047	140047	129501	3	129930	80100	30200	20000	30000	60200	20000	50000	140047	140035	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	0	0	0	20000	2	0	2	0	0	0	0	3210	1	16	1	1	139787	40000	6	6	6	20000	20000	40100	140048	140036	140036	140048	140036
80204	140047	1049	0	0	0	0	0	0	2	0	0	1	0	0	140032	80130	129682	25	90103	40100	30000	20000	30100	30000	20000	12043837	6691876	12181242	0	140023	140047	140047	129501	3	129930	80100	30200	20000	30000	60200	20000	50000	140047	140047	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	0	0	0	20000	0	0	2	0	0	0	0	3210	1	16	1	1	139787	40000	0	6	6	20000	20000	40100	140048	140048	140048	140048	140048
80204	140048	1049	0	0	0	0	0	0	0	0	0	0	0	0	140032	84771	129682	25	90103	40100	30003	20000	30100	30000	20000	12042832	6691876	12182337	0	140023	140035	140035	129501	3	129929	80100	30200	20000	30000	60200	20000	50000	140035	140047	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	1	0	3	20000	0	0	2	0	0	0	0	3210	1	16	1	1	139787	40000	0	0	6	20000	20000	40100	140036	140036	140048	140048	140048
80204	140047	1049	0	0	0	0	0	0	6	0	0	1	0	0	140032	80132	129682	25	90103	40100	30003	20000	30100	30000	20000	12043837	6691876	12181242	0	140023	140047	140047	129501	3	129930	80100	30200	20000	30000	60200	20000	50000	140047	140047	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	0	20000	0	0	0	20000	2	0	2	0	0	0	0	3210	1	16	1	0	139787	40000	6	6	6	20000	20000	40100	140048	140102	140076	140050	140048
80204	140047	1049	0	0	0	0	0	0	0	0	0	1	0	0	140032	84771	129682	25	90100	40100	30003	20000	30100	30000	20000	12042832	6691876	12182337	0	140023	140035	140047	129501	3	129930	80100	30200	20000	30000	60200	20000	50000	140035	140035	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	2	20000	0	0	0	20000	2	0	2	0	1	0	0	3210	1	16	1	1	139787	40000	6	6	6	20000	20000	40100	140048	140048	140048	140036	140036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80025	140047	1049	0	0	0	0	0	0	0	0	2	0	0	0	140032	84771	129682	25	90013	40010	30003	20000	30010	30000	20000	12043387	6691924	12182517	1	140023	140096	140047	129591	3	130022	80010	30020	20000	30000	60020	20000	50000	140035	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	1	0	20000	2	0	2	0	0	0	0	3140	9	16	8	9	139781	40000	6	6	6	20000	20000	40010	140054	140054	140054	140054	140054
80024	140053	1049	1	0	1	1	1	0	0	0	8	1	0	1	140038	84777	129688	25	90016	40010	30006	20000	30010	30000	20000	12043909	6692164	12183051	0	140073	140047	140047	129591	3	130020	80010	30020	20000	30000	60020	20000	50000	140047	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	20000	2	0	2	0	0	0	0	3140	8	16	8	7	139787	40000	6	6	6	20000	20000	40010	140050	140048	140048	140048	140052
80024	140047	1049	0	0	0	0	0	0	1	0	2	1	0	0	140032	84771	129670	25	90013	40010	30003	20000	30010	30000	20000	12043387	6691290	12182517	0	140023	140047	140047	129591	27	130020	80010	30020	20000	30000	60020	20000	50000	140047	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	20000	2	0	2	0	0	0	0	3140	9	16	8	8	139787	40000	6	6	6	20000	20000	40010	140048	140048	140048	140048	140048
80024	140047	1049	0	0	0	0	0	0	0	0	2	1	0	0	140032	84771	129682	25	90013	40010	30003	20000	30010	30000	20000	12043387	6691876	12182517	0	140023	140047	140035	129591	3	130020	80010	30020	20000	30000	60020	20000	50000	140048	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	20000	2	0	2	0	0	0	0	3140	10	16	8	9	139787	40000	6	6	6	20000	20000	40010	140048	140048	140048	140048	140048
80024	140047	1049	0	0	0	0	0	0	0	0	2	1	0	0	140020	84771	129682	25	90013	40010	30003	20000	30010	30000	20000	12043387	6691876	12182517	0	140023	140035	140047	129591	3	130020	80010	30020	20000	30000	60020	20066	50000	140047	140140	1	1	50021	10	9	10	40010	10000	10000	0	10	20004	0	0	20000	0	0	0	20000	2	0	2	0	0	0	0	3140	9	16	8	7	139787	40000	6	6	6	20000	20000	40010	140048	140048	140048	140036	140048
80024	140047	1049	0	0	0	0	0	0	0	0	2	1	0	0	140032	84771	129682	25	90013	40010	30003	20000	30010	30000	20000	12043387	6691876	12182517	0	140023	140047	140047	129591	3	130020	80010	30020	20000	30000	60020	20000	50000	140047	140035	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	20000	2	0	2	0	0	0	0	3140	7	16	8	8	139787	40000	6	6	0	20000	20000	40010	140048	140036	140048	140048	140048
80024	140047	1049	0	1	0	0	0	0	1	0	2	1	0	0	140310	84771	129682	25	90013	40010	30007	20000	30010	30000	20000	12072825	6691876	12182517	0	140023	140047	140389	129591	52	130020	80010	30020	20000	30000	60206	20000	50164	140573	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	20000	2	0	2	0	0	0	0	3140	10	16	13	11	139787	40056	6	6	6	20000	20000	40010	140048	140048	140048	140577	140048
80024	140136	1049	0	0	0	0	0	0	0	0	17	0	0	0	140032	84771	129682	25	90013	40010	30003	20000	30010	30000	20000	12043387	6691876	12183563	0	140023	140047	140047	129591	3	130020	80010	30020	20000	30000	60020	20000	50000	140047	140035	1	1	50021	10	9	10	40010	10000	10000	0	10	20004	0	0	20000	0	0	0	20000	2	0	2	0	0	0	0	3140	8	16	8	9	139787	40000	6	6	6	20000	20000	40010	140048	140048	140048	140048	140048
80024	140047	1048	0	0	0	0	0	0	0	0	2	1	0	0	140032	84771	129682	25	90010	40010	30003	20000	30010	30000	20000	12043387	6691876	12182517	1	140023	140047	140047	129591	3	130020	80010	30020	20000	30000	60020	20000	50000	140047	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20004	0	45	0	20000	2	0	2	0	0	0	0	3140	9	16	8	7	139787	40000	6	6	6	20000	20000	40010	140048	140048	140048	140048	140048
80024	140047	1049	0	0	0	0	0	0	0	0	2	0	0	0	140032	84771	129670	25	90013	40015	30003	20000	30010	30000	20000	12043387	6691876	12182517	0	140011	140047	140047	129591	3	130020	80010	30020	20000	30000	60020	20000	50000	140047	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	20000	2	0	2	0	0	0	0	3140	8	16	8	7	139787	40000	6	6	6	20000	20000	40010	140048	140048	140048	140048	140048

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.2d, v1.2d }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80205	140051	1049	1	0	0	24	0	1	0	0	140042	84775	129670	25	90103	40100	30000	20000	30100	30000	20000	12042832	6692116	12182693	1	140011	0	140055	140054	129509	3	129938	80100	30200	20000	30000	60200	20000	50000	140055	140035	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	20000	0	0	20000	2	0	0	0	3210	1	16	1	1	139795	40000	0	11	10	20000	20000	40100	140036	140036	140056	140056	140056
80204	140051	1049	0	0	0	0	0	0	0	1	140036	84779	129690	25	90103	40100	30003	20000	30100	30000	20000	12042832	6692068	12182693	0	140011	0	140121	140038	129509	3	129918	80100	30200	20000	30000	60200	20000	50000	140055	140035	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	1	0	20000	2	2	0	0	3210	1	16	1	1	139775	40000	10	14	10	20000	20000	40100	140056	140056	140036	140056	140036
80204	140035	1049	0	0	0	2	0	1	0	1	140089	84775	129690	25	90103	40100	30003	20000	30100	30000	20050	12050139	6692260	12181242	0	140027	0	140051	140051	129505	3	129934	80100	30200	20000	30000	60200	20000	50000	140055	140051	1	1	50202	100	99	100	40100	10000	10000	0	100	20000	0	20000	1	0	20000	2	2	0	0	3210	1	16	1	1	139775	40009	10	14	14	20000	20000	40100	140056	140036	140036	140052	140052
80204	140055	1049	0	0	0	2	0	1	0	0	140036	84779	129690	25	90100	40100	30000	20000	30100	30000	20000	12044533	6692260	12182693	0	140027	0	140035	140055	129509	3	129938	80100	30200	20000	30000	60200	20000	50000	140055	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	20000	0	0	20000	0	2	0	0	3210	1	16	1	1	139775	40000	0	14	10	20000	20000	40100	140107	140097	140056	140036	140036
80204	140035	1049	0	0	0	0	0	0	0	0	140078	80130	129690	25	90103	40100	30003	20000	30100	30000	20000	12042832	6692260	12181242	0	140031	0	140035	140035	129489	3	129938	80100	30200	20000	30000	60200	20000	50000	140051	140035	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	20000	0	0	20000	0	0	0	0	3210	1	16	1	1	139775	40000	0	10	10	20000	20000	40100	140036	140052	140052	140036	140036
80205	140055	1049	0	0	0	0	0	1	0	0	140020	80130	129690	25	90100	40100	30000	20000	30100	30000	20000	12044533	6692260	12181242	0	140031	0	140055	140055	129509	3	129924	80100	30200	20000	30000	60200	20000	50000	140055	140035	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	0	20000	0	0	20000	0	2	0	0	3210	1	16	1	1	139791	40000	10	0	10	20000	20000	40100	140036	140056	140036	140056	140036
80204	140051	1049	0	0	0	0	0	0	0	0	140132	80130	129670	25	90103	40100	30003	20000	30100	30000	20000	12044533	6692260	12181242	0	140031	0	140035	140035	129505	3	129918	80100	30200	20000	30000	60200	20000	50000	140055	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	0	0	20000	2	0	0	0	3210	1	16	1	1	139797	40000	0	10	0	20000	20000	40100	140052	140036	140056	140036	140036
80204	140055	1049	0	0	0	2	0	0	0	1	140037	84779	129686	25	90103	40100	30003	20000	30100	30000	20000	12042832	6692068	12182693	0	140011	0	140035	140035	129509	3	129938	80100	30200	20000	30000	60200	20000	50000	140051	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	20001	2	20000	0	0	20000	2	2	0	0	3210	1	16	1	1	139795	40000	10	14	0	20000	20000	40100	140056	140056	140056	140036	140056
80204	140055	1049	0	0	0	2	0	0	0	0	140076	80130	129687	25	90100	40100	30003	20000	30100	30000	20000	12044185	6691290	12181242	0	140011	0	140055	140055	129489	3	129934	80100	30200	20000	30000	60200	20000	50000	140035	140035	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	0	0	20000	2	2	0	0	3210	1	16	1	1	139775	40000	0	0	10	20000	20000	40100	140056	140036	140056	140056	140056
80204	140035	1049	0	0	0	2	0	0	0	0	140036	80130	129686	25	90100	40100	30003	20000	30100	30000	20000	12042832	6691290	12183049	0	140031	0	140055	140035	129509	3	129918	80100	30200	20000	30000	60200	20000	50000	140055	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	20000	0	3	20000	0	2	0	0	3210	1	16	1	1	139795	40000	0	0	0	20000	20000	40100	140041	140056	140056	140052	140036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80025	140051	1049	0	0	0	0	0	6	1	0	1	140026	80138	129676	25	90016	40010	30003	20000	30010	30000	20000	12044257	6691588	12183407	1	140037	140061	140061	129605	3	130024	80010	30020	20000	30000	60020	20000	50000	140051	140051	2	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	20000	0	3	20000	2	0	0	0	3221	4	2	16	1	1	139801	40000	14	0	0	20000	20000	40010	140062	140042	140062	140062	140062
80024	140061	1049	1	1	1	0	0	4	1	0	1	140020	84775	129670	25	90013	40010	30003	20000	30010	30000	20000	12042322	6692068	12181422	1	140027	140051	140051	129579	3	130008	80010	30020	20000	30000	60020	20000	50000	140051	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	3	20000	0	0	0	0	3140	5	1	16	1	1	139795	40000	14	14	14	20000	20000	40010	140107	140077	140036	140052	140056
80024	140055	1049	0	0	0	0	0	0	0	0	1	140040	80130	129670	25	90013	40010	30000	20000	30010	30000	20000	12044083	6692260	12182873	0	140011	140036	140055	129599	3	130028	80010	30020	20000	30000	60020	20000	50000	140055	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	20000	0	0	20000	0	2	0	0	3140	4	2	16	1	1	139795	40000	0	10	0	20000	20000	40010	140056	140036	140056	140056	140056
80024	140055	1049	0	0	0	0	0	0	1	0	1	140040	80130	129670	25	90010	40010	30003	20000	30010	30000	20000	12043735	6692068	12181422	1	140027	140055	140035	129595	3	130028	80010	30020	20000	30000	60020	20000	50000	140055	140035	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	20000	0	0	20000	2	2	0	0	3140	4	1	16	1	1	139775	40008	10	10	10	20000	20000	40010	140036	140056	140052	140056	140052
80024	140051	1049	0	0	0	0	0	2	0	0	0	140040	84779	129690	25	90013	40010	30003	20000	30010	30000	20000	12043735	6691290	12182873	1	140011	140055	140055	129599	3	130024	80010	30020	20000	30000	60020	20000	50000	140055	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	1	0	20000	0	0	0	0	3140	4	1	16	1	1	139775	40000	10	0	10	20000	20000	40010	140052	140053	140052	140052	140052
80024	140051	1049	0	0	0	0	0	2	1	0	0	140020	84775	129686	25	90013	40010	30000	20000	30010	30000	20000	12044083	6692260	12182873	1	140031	140055	140055	129600	3	130008	80010	30020	20000	30000	60020	20000	50000	140055	140035	1	1	50021	10	9	10	40010	10000	10000	1	10	20000	2	20000	0	0	20000	2	2	0	0	3140	5	2	16	1	1	139775	40000	0	0	0	20000	20000	40010	140036	140036	140056	140052	140036
80024	140055	1049	0	0	0	0	0	0	0	0	0	140020	84779	129690	25	90013	40010	30000	20000	30010	30000	20000	12042322	6692068	12182873	0	140105	140055	140055	129635	3	130028	80010	30020	20000	30000	60020	20000	50000	140055	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	20000	0	2	0	0	3140	4	1	16	1	1	139791	40000	14	10	0	20000	20000	40010	140036	140036	140036	140036	140036
80024	140055	1049	0	0	0	0	0	2	0	0	0	140020	84779	129671	25	90013	40010	30003	20000	30010	30000	20000	12044083	6692068	12182873	1	140031	140055	140035	129599	3	130028	80010	30020	20000	30000	60020	20000	50000	140051	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	20000	2	2	0	0	3140	5	1	16	1	1	139791	40000	10	10	10	20000	20000	40010	140052	140052	140036	140036	140052
80024	140051	1049	0	0	0	0	0	2	1	0	1	140020	84779	129670	25	90013	40010	30000	20000	30010	30000	20000	12044083	6692068	12182873	0	140030	140035	140035	129599	3	130024	80010	30020	20000	30000	60020	20000	50000	140051	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	20000	0	2	0	0	3140	5	1	16	1	1	139795	40000	10	10	10	20000	20000	40010	140052	140052	140036	140052	140052
80024	140079	1049	0	0	0	1	1	32	1	0	0	140040	84780	129686	25	90010	40010	30003	20000	30010	30000	20000	12042322	6692068	12182873	0	140031	140055	140035	129579	3	130008	80010	30020	20000	30000	60020	20000	50000	140035	140051	1	1	50021	10	9	10	40010	10000	10000	1	10	20000	2	20000	0	0	20000	2	2	0	0	3140	4	1	16	1	1	139775	40000	10	0	14	20000	20000	40010	140056	140052	140054	140036	140052

Test 4: throughput

Count: 8

Code:

  ld2 { v0.2d, v1.2d }, [x6]
  ld2 { v0.2d, v1.2d }, [x6]
  ld2 { v0.2d, v1.2d }, [x6]
  ld2 { v0.2d, v1.2d }, [x6]
  ld2 { v0.2d, v1.2d }, [x6]
  ld2 { v0.2d, v1.2d }, [x6]
  ld2 { v0.2d, v1.2d }, [x6]
  ld2 { v0.2d, v1.2d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320205	80069	599	0	0	1	0	0	0	38	0	0	0	2	80026	2	0	5	3	25	320152	100	160052	160000	100	160090	160000	500	800374	1921052	1	80022	80041	80041	0	3	23	320100	200	160000	160000	200	160000	320000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	35	160032	0	0	32	160032	6	1	32	35	0	0	0	0	5109	1	17	1	1	80038	0	13	13	2	160000	160000	100	80042	80042	80042	80042	80042
320204	80041	599	1	0	1	0	0	1	58	0	0	0	2	80026	2	5	6	3	25	320154	100	160056	160000	100	160000	160000	500	801372	1922540	0	80022	80041	80041	0	3	23	320100	200	160000	160000	200	160000	320000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160014	13	43	160054	0	0	52	160039	6	1	51	43	12	2	0	0	5109	1	17	1	1	80038	0	13	13	2	160000	160000	100	80042	80042	80042	80042	80042
320204	80041	600	1	1	0	0	0	0	57	0	0	0	0	80026	2	12	12	0	25	320138	100	160038	160000	100	160000	160000	500	800374	1921052	0	80022	80041	80041	0	3	23	320100	200	160000	160000	200	160000	320000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	160000	0	35	160032	0	0	32	160032	6	1	32	35	0	0	1	0	5109	1	17	1	1	80038	1	10	10	0	160000	160000	100	80042	80042	80042	80042	80042
320204	80041	600	0	0	0	0	0	0	38	0	0	0	0	80026	2	12	12	0	25	320138	100	160038	160000	100	160000	160000	500	800377	1921082	0	80022	80041	80041	0	3	23	320100	200	160000	160000	200	160000	320000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	35	160032	0	0	32	160032	6	1	32	35	0	0	0	0	5109	1	17	1	1	80038	1	10	10	0	160000	160000	100	80042	80042	80042	80042	80042
320204	80041	600	0	0	0	0	0	0	38	0	1	0	0	80026	2	12	12	0	25	320138	100	160038	160000	100	160000	160000	500	800377	1921094	1	80022	80041	80041	0	3	23	320100	200	160000	160000	200	160000	320000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	35	160032	0	0	32	160032	6	1	32	35	0	0	0	0	5109	1	17	1	1	80038	1	10	10	0	160000	160000	100	80042	80042	80042	80042	80042
320204	80041	599	0	0	0	0	0	0	38	0	0	0	0	80026	2	12	12	0	25	320138	100	160038	160000	100	160000	160000	500	800342	1921064	0	80022	80041	80041	0	3	23	320100	200	160000	160000	200	160000	320000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	35	160032	0	0	32	160032	6	1	32	35	0	0	0	0	5109	1	17	1	1	80038	1	10	10	0	160000	160000	100	80042	80042	80042	80042	80042
320204	80041	600	0	0	0	0	0	0	38	0	0	0	0	80026	2	12	12	0	25	320138	100	160038	160000	100	160000	160000	500	800377	1921082	0	80022	80041	80041	0	25	23	320100	200	160000	160000	200	160000	320000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	35	160032	0	0	32	160032	6	1	32	35	0	0	0	0	5109	1	17	1	1	80038	1	10	10	0	160000	160000	100	80042	80042	80042	80042	80042
320204	80041	600	0	0	0	0	0	0	38	0	0	0	0	80026	2	12	12	0	25	320100	100	160038	160000	100	160000	160000	500	800377	1921070	0	80022	80041	80041	0	3	23	320100	200	160000	160092	200	160000	320000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	35	160032	2	0	39	160032	6	1	32	40	0	0	0	0	5109	1	17	1	1	80038	1	10	10	0	160000	160000	100	80042	80042	80042	80042	80042
320204	80041	600	0	0	0	0	0	0	38	0	0	0	0	80026	2	12	12	0	25	320138	100	160038	160000	100	160000	160000	500	800377	1921086	0	80022	80041	80041	0	3	23	320100	200	160000	160000	200	160000	320000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	35	160032	0	0	32	160032	6	1	32	35	0	0	0	0	5109	1	17	1	1	80038	1	10	14	0	160000	160000	100	80042	80042	80042	80042	80042
320204	80041	600	0	0	0	0	0	0	38	0	1	0	0	80026	2	12	12	0	43	320138	100	160038	160000	100	160000	160000	500	800377	1921402	0	80022	80041	80041	0	3	23	320100	200	160000	160000	200	160000	320000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	35	160032	0	0	32	160032	6	1	32	0	0	0	0	0	5109	1	17	1	1	80038	1	10	10	0	160000	160000	100	80042	80042	80042	80042	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	80055	599	0	0	0	0	0	1	0	0	0	38	0	1	0	0	0	80026	2	12	12	0	25	320048	10	160000	160000	10	160000	160000	50	800374	1921104	1	80022	0	80041	80041	0	3	23	320010	20	160000	160000	20	160000	320000	80041	80041	1	1	80021	10	9	10	10	80000	80000	1	10	160000	0	35	0	160032	0	0	32	160032	6	1	32	35	0	0	0	5019	0	11	17	0	12	12	80038	1	10	10	160000	160000	10	80042	80042	80042	80128	80042
320024	80041	600	0	0	0	0	0	0	0	0	0	38	0	1	0	0	0	80026	2	12	12	0	25	320048	10	160038	160000	10	160000	160000	50	800374	1920000	0	80022	0	80041	80041	0	3	33	320010	20	160000	160000	20	160000	320000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	35	0	160032	1	0	32	160032	6	1	32	35	0	0	0	5019	0	12	17	0	12	7	80038	1	10	10	160000	160000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	0	0	38	0	1	0	0	0	80026	2	12	12	0	25	320048	10	160038	160000	10	160000	160000	50	800377	1921064	0	80022	0	80041	80041	0	3	23	320010	20	160000	160000	20	160000	320000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	35	8	160032	0	0	0	160032	6	1	32	35	0	0	0	5019	0	11	17	0	11	11	80038	1	10	0	160000	160000	10	80042	80042	80042	80042	80042
320024	80041	600	0	0	0	0	0	0	0	0	0	38	0	1	0	0	0	80026	2	12	12	0	25	320048	10	160038	160000	10	160000	160000	50	800377	1921100	0	80022	0	80041	80041	0	3	23	320010	20	160000	160000	20	160000	320000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	35	0	160032	0	0	35	160032	6	1	32	35	0	0	0	5019	0	12	17	0	11	7	80038	1	10	10	160000	160000	10	80042	80042	80042	80042	80042
320024	80041	600	0	0	0	0	0	0	0	0	0	38	0	1	0	0	0	80026	2	12	12	0	25	320048	10	160038	160000	10	160000	160000	50	800377	1921064	0	80022	0	80041	80041	0	3	23	320010	20	160000	160000	20	160000	320000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	35	0	160032	0	0	32	160032	6	1	32	35	0	0	0	5019	0	14	17	0	9	13	80038	1	10	10	160000	160000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	1	1	0	0	38	0	1	0	0	0	80026	2	12	12	0	25	320010	10	160038	160000	10	160000	160000	50	800377	1921064	0	80022	0	80041	80041	0	3	23	320010	20	160000	160000	20	160000	320184	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	35	0	160032	0	0	32	160032	6	1	32	35	0	0	0	5019	0	11	17	0	11	10	80038	1	10	10	160000	160000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	1	0	0	0	38	0	1	0	0	0	80026	2	12	12	0	25	320048	10	160038	160000	10	160000	160000	50	800377	1921118	0	80022	0	80041	80041	0	3	23	320010	20	160000	160000	20	160000	320000	80041	80041	1	1	80021	10	9	10	10	80000	80000	1	10	160000	0	35	0	160032	0	0	32	160032	6	1	32	35	0	0	0	5019	0	10	17	0	10	10	80038	1	10	10	160000	160000	10	80042	80042	80042	80042	80042
320024	80041	600	0	0	0	0	0	0	0	0	0	47	0	1	0	0	0	80026	2	12	12	0	25	320048	10	160038	160000	10	160000	160000	50	800377	1921030	0	80022	0	80041	80041	0	3	23	320010	20	160000	160000	20	160000	320000	80041	80041	1	1	80021	10	9	10	10	80000	80000	1	10	160000	0	35	0	160032	0	0	32	160032	6	1	32	35	0	0	0	5019	0	9	17	0	10	7	80038	1	10	0	160000	160000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	0	0	38	0	1	0	0	0	80026	2	12	12	0	25	320048	10	160038	160000	10	160000	160000	50	800377	1921064	1	80022	0	80041	80041	0	3	30	320010	20	160000	160000	20	160000	320000	80041	80041	1	1	80021	10	9	10	10	80000	80000	1	10	160000	0	35	0	160032	0	0	32	160032	6	1	32	35	0	0	0	5019	0	7	17	0	6	12	80038	1	10	10	160000	160000	10	80042	80042	80042	80042	80042
320024	80041	600	0	0	0	0	0	0	0	0	0	38	0	1	0	0	0	80026	0	12	12	0	25	320048	10	160038	160000	10	160000	160000	50	800372	1921052	0	80022	0	80041	80041	0	3	23	320010	20	160000	160000	20	160000	320000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	35	0	160032	0	0	32	160032	6	1	0	35	0	0	1	5019	0	13	17	0	11	11	80038	1	10	10	160000	160000	10	80042	80042	80042	80042	80042

LD2 (multiple, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations