Firestorm: LD2 (multiple, 2S) measurements

Code:

  ld2 { v0.2s, v1.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.008

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	1f	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
63005	28299	212	2	1	2	1	0	1	0	0	85	0	1	0	5251	27822	0	1	0	16020	3004	2006	1000	2000	1000	5000	23864	12	22815	28245	28363	3	10	3000	1000	2000	1000	2000	28152	27931	1	1	61001	1000	1000	1	1003	2	3	1004	1	2	3	1002	2	0	3	0	0	13814	10297	7293	3535	0	53	19547	3401	3827	15	47	46	27975	14033	12364	12979	1000	2000	28029	28199	28043	28254	28035
63004	28512	210	0	1	2	1	2	1	0	0	55	0	0	0	5262	27933	0	1	1	16011	3008	2008	1000	2000	1000	5000	23884	9	22776	28303	28446	3	10	3000	1000	2000	1000	2000	28071	28075	1	1	61001	1000	1000	0	1003	3	2	1003	0	0	2	1000	2	2	3	1	0	14100	10496	7332	3492	0	46	19624	3513	3826	11	49	46	27798	13955	12638	12820	1000	2000	28073	28044	28016	28002	28417
63004	28024	211	0	1	2	1	2	1	0	0	5	0	0	0	5086	27985	0	0	1	15949	3006	2006	1000	2000	1000	5000	23879	16	22791	28260	28534	3	10	3000	1000	2000	1000	2000	28100	28013	1	1	61001	1000	1000	0	1002	3	3	1005	2	1	3	1001	2	3	2	1	0	13864	10129	7192	3329	1	43	19493	3407	3821	19	45	42	27947	14001	12214	12811	1000	2000	28350	28202	28170	27950	28111
63004	28115	213	0	1	1	1	0	1	0	0	3	0	1	0	5056	27884	0	0	1	15992	3006	2006	1000	2000	1000	5000	23918	9	22775	28136	28400	3	10	3000	1000	2000	1000	2000	28202	28154	1	1	61001	1000	1000	0	1002	1	2	1003	0	2	1	1000	2	2	3	1	0	13422	10082	7311	3486	0	46	19795	3440	3829	13	43	40	27809	15054	12305	12862	1000	2000	28041	28133	28035	28244	28307
63004	28105	212	0	1	2	1	2	1	0	0	22	0	1	0	5203	28002	0	0	0	16068	3010	2006	1000	2000	1000	5000	23918	1	22754	28316	28519	3	10	3000	1000	2000	1000	2000	28333	28241	1	1	61001	1000	1000	0	1002	2	2	1004	0	1	3	1001	2	2	3	1	0	14143	10274	7233	3556	1	40	19881	3205	3823	15	42	42	27767	14543	12358	13968	1000	2000	28500	28445	28452	28256	28022
63004	28387	210	0	1	1	1	4	1	0	0	29	0	1	0	5206	28146	0	1	1	16078	3008	2006	1000	2000	1000	5000	23882	8	22796	28360	28115	3	10	3000	1000	2000	1000	2000	27822	28284	1	1	61001	1000	1000	0	1003	2	2	1002	0	1	3	1002	2	2	3	1	0	13858	10148	7205	3420	0	48	19757	3393	3823	14	44	39	27994	14506	12508	13687	1000	2000	28395	28008	28254	28058	28110
63004	28431	212	0	1	2	1	2	1	1	0	287	0	1	0	5119	27903	0	0	0	16054	3010	2010	1000	2000	1000	5000	23878	3	22768	28552	28205	3	10	3003	1000	2000	1000	2000	28418	28094	1	1	61001	1000	1000	0	1001	3	3	1003	0	1	2	1001	2	2	3	1	0	13922	9578	7173	3373	1	51	19608	3370	3825	14	42	45	27920	14098	12410	12774	1000	2000	28460	28401	28278	28072	28227
63004	28197	212	0	1	2	1	2	1	0	0	5	0	1	0	4809	27947	0	1	1	16083	3006	2006	1000	2000	1000	5000	23862	14	22769	28331	28455	3	10	3000	1000	2000	1000	2000	28542	28238	1	1	61001	1000	1000	0	1003	2	3	1003	0	2	3	1002	2	2	2	1	0	13719	10013	7133	3497	0	48	19444	3436	3828	14	41	44	27985	14480	12807	12912	1000	2000	28217	28144	28223	28103	28196
63004	28107	213	0	1	3	1	2	1	0	0	9	0	1	0	4946	27938	0	0	0	16170	3010	2008	1000	2000	1000	5000	23886	11	22770	28347	28294	3	10	3000	1000	2000	1000	2000	28083	28161	1	1	61001	1000	1000	0	1003	2	3	1005	0	2	3	1001	3	2	2	1	1	14140	9775	7402	3550	0	47	19530	3447	3822	17	47	49	27851	14008	12355	12691	1000	2000	28202	28226	28193	28097	28455
63004	28086	211	0	1	3	0	0	0	0	0	5	0	0	0	5346	27923	0	1	0	16237	3006	2010	1000	2000	1000	5000	23874	9	22755	28501	28351	3	10	3000	1000	2000	1000	2000	27971	27934	1	1	61001	1000	1000	0	1002	3	2	1005	0	0	3	1002	2	2	2	1	0	13364	10038	7175	3245	0	47	19677	3400	3825	15	48	44	27874	14501	12248	12959	1000	2000	28258	28156	28275	28086	28158

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.2s, v1.2s }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3f	4d	4e	4f	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140058	1049	0	0	0	0	0	0	1	0	1	0	140020	139608	139346	129360	0	25	80106	40100	30006	10000	30100	30000	10000	1266450	6694118	20082745	0	140036	0	140041	140060	130568	3	131147	70100	30200	10000	30000	60200	10000	30000	140054	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10003	0	0	0	1	10000	1	1	0	1	0	0	3210	1	128	1	1	139572	40000	13	10	13	10000	20000	40100	140058	140061	140042	140061	140055
70204	140035	1049	0	0	0	0	0	0	1	0	0	0	140039	139608	139346	129360	0	25	80103	40100	30003	10000	30100	30000	10000	1264354	6693731	20079451	0	140011	0	140054	140054	130559	3	131150	70100	30200	10000	30000	60200	10000	30000	140035	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	1	0	10000	1	0	1	0	0	0	3210	1	128	1	1	139566	40000	13	10	10	10000	20000	40100	140100	140055	140055	140055	140052
70204	140054	1049	0	0	0	0	0	0	1	0	1	0	140039	139404	139346	129360	0	81	80100	40100	30003	10000	30100	30000	10000	1264390	6693731	20081843	0	140011	0	140035	140035	130531	3	131150	70100	30200	10000	30000	60200	10000	30000	140035	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	6	10000	0	0	1	0	0	0	3210	1	133	1	1	139544	40000	13	10	13	10000	20000	40100	140055	140055	140055	140055	140036
70204	140035	1049	0	0	0	0	0	0	0	0	0	0	140036	139608	139346	129360	0	25	80100	40100	30003	10000	30100	30000	10000	1264310	6693584	20081843	0	140030	0	140054	140054	130562	3	131150	70100	30200	10000	30000	60200	10000	30000	140035	140035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	0	0	0	0	3210	1	133	1	1	139544	40000	13	13	13	10000	20000	40100	140052	140052	140055	140036	140036
70204	140054	1049	0	0	0	0	0	0	0	0	0	0	140039	139608	139346	129341	0	25	80103	40100	30000	10000	30100	30160	10000	1264390	6693731	20081843	0	140030	0	140054	140054	130568	3	131126	70100	30200	10000	30000	60200	10000	30000	140051	140035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	0	3210	1	128	1	1	139566	40000	0	10	13	10000	20000	40100	140055	140055	140052	140055	140052
70204	140035	1049	0	0	0	0	0	0	1	0	0	0	140039	139608	139344	129360	0	25	80103	40100	30000	10000	30100	30000	10000	1264390	6693731	20083340	0	140030	0	140054	140051	130531	3	131126	70100	30200	10000	30000	60200	10000	30000	140054	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	0	0	0	0	0	0	3210	1	133	1	1	139544	40000	0	13	13	10000	20000	40100	140036	140055	140055	140055	140036
70204	140054	1049	0	0	0	0	0	0	1	0	1	0	140039	139608	139346	129341	0	25	80103	40100	30003	10000	30100	30000	10000	1264390	6693731	20081843	0	140011	0	140054	140054	130562	3	131150	70100	30200	10000	30000	60200	10000	30000	140054	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	0	0	0	0	3210	1	128	1	1	139544	40000	13	13	13	10000	20000	40100	140055	140055	140036	140055	140055
70204	140051	1048	1	0	0	0	0	0	22	0	1	0	140039	139608	139325	129360	0	57	80103	40100	30003	10000	30100	30000	10000	1264390	6693731	20081843	0	140011	0	140051	140051	130562	3	131150	70100	30200	10000	30000	60200	10000	30000	140054	140035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	0	0	0	0	3210	1	128	1	1	139566	40000	13	13	13	10000	20000	40100	140055	140063	140036	140036	140036
70204	140035	1049	0	0	0	1	0	0	1	0	0	1	140248	139608	139346	129374	0	25	80103	40100	30003	10000	30100	30000	10000	1264310	6692791	20079451	0	140030	0	140357	140346	130568	3	131128	70100	30200	10000	30000	60200	10000	30000	140055	140054	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	2	0	0	10000	1	0	1	0	0	0	3210	1	128	1	1	139569	40000	13	13	13	10000	20000	40100	140055	140055	140055	140055	140052
70204	140054	1049	0	0	0	1	0	0	13	0	0	0	140039	139608	139325	129360	0	25	80100	40100	30003	10000	30100	30000	10000	1264337	6693731	20081843	0	140030	0	140054	140054	130531	3	131150	70100	30200	10000	30000	60200	10000	30000	140054	140038	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	1	0	3	10000	0	0	1	0	0	0	3210	1	128	1	1	139566	40000	13	0	10	10000	20000	40100	140052	140055	140055	140052	140052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0e	0f	19	1e	1f	22	23	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140047	1049	0	0	0	0	1	0	1	0	140032	139446	139342	129355	25	80013	40010	30003	10000	30010	30000	10000	1264748	6693388	20081263	140023	0	140047	140047	130565	3	131173	70010	30020	10000	30000	60020	10000	30000	140047	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	3140	0	0	0	4	120	2	2	139569	40000	6	6	6	10000	20000	40010	140048	140048	140098	140048	140048
70024	140047	1049	0	0	0	0	1	0	0	0	140032	139451	139338	129353	25	80013	40010	30003	10000	30010	30000	10000	1264748	6693388	20081263	140023	0	140050	140047	130565	3	131173	70010	30020	10000	30000	60020	10000	30000	140108	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	68	0	10000	0	1	0	3140	0	0	0	2	120	2	2	139569	40000	6	6	6	10000	20000	40010	140048	140054	140088	140051	140048
70024	140047	1049	0	0	0	0	1	0	1	0	140032	139531	139370	129355	25	80013	40010	30003	10000	30010	30000	10000	1264748	6693388	20081263	140023	0	140047	140047	130592	3	131173	70010	30020	10000	30000	60020	10000	30000	140047	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	3140	0	0	0	3	120	2	2	139569	40000	6	6	6	10000	20000	40010	140048	140134	140052	140048	140048
70024	140047	1049	0	0	0	0	1	0	1	0	140032	139543	139350	129353	25	80013	40010	30003	10000	30010	30000	10000	1264748	6693388	20081263	140023	0	140035	140047	130565	3	131173	70010	30020	10000	30000	60020	10000	30000	140047	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	3140	0	0	0	2	120	2	2	139569	40000	6	6	6	10000	20000	40010	140048	140048	140094	140048	140048
70024	140047	1049	0	0	0	0	1	0	1	0	140121	139508	139338	129353	25	80013	40010	30003	10000	30010	30159	10000	1264748	6693388	20081407	140023	0	140047	140047	130565	3	131173	70010	30020	10000	30000	60020	10000	30000	140047	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	3	10000	1	1	0	3140	0	0	0	2	120	2	2	139569	40000	6	6	6	10000	20000	40010	140049	140098	140079	140048	140048
70024	140047	1049	0	0	0	0	1	0	1	0	140032	139482	139339	129353	25	80013	40010	30003	10000	30010	30000	10000	1264748	6693388	20081263	140023	0	140047	140047	130565	3	131173	70010	30020	10000	30000	60020	10000	30000	140047	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	3140	0	0	0	2	120	2	2	139569	40000	6	6	17	10000	20000	40010	140048	140099	140049	140051	140049
70024	140047	1048	0	0	0	0	1	0	0	0	140032	139488	139343	129353	25	80013	40010	30003	10000	30010	30000	10000	1264748	6693388	20081263	140023	0	140047	140047	130565	3	131173	70010	30020	10000	30188	60020	10000	30000	140047	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	3140	0	0	0	2	120	2	2	139569	40000	6	6	6	10000	20000	40010	140048	140105	140062	140049	140048
70024	140047	1049	0	1	0	0	1	0	1	0	140032	139502	139340	129353	25	80013	40010	30003	10000	30010	30000	10000	1264748	6693388	20079451	140023	0	140047	140047	130565	3	131173	70010	30020	10000	30000	60020	10000	30000	140047	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	3140	0	0	0	1	120	2	1	139569	40000	6	6	6	10000	20000	40010	140048	140048	140121	140051	140048
70024	140047	1049	0	0	0	0	6	0	1	0	140032	139499	139413	129354	25	80013	40010	30003	10000	30010	30000	10000	1264748	6692791	20081263	140023	0	140047	140047	130565	3	131173	70010	30020	10000	30000	60020	10000	30000	140047	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	3140	0	0	0	2	120	2	2	139569	40000	6	6	6	10000	20000	40010	140048	140054	140110	140087	140048
70024	140047	1049	0	0	0	0	1	0	1	0	140032	139449	139338	129353	25	80013	40010	30003	10000	30010	30000	10000	1264748	6693388	20081263	140011	0	140047	140047	130565	3	131173	70010	30020	10000	30000	60020	10000	30000	140035	140047	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	10000	1	1	0	3140	0	0	1	3	120	2	2	139569	40000	6	6	6	10000	20000	40010	140048	140048	140102	140059	140048

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.2s, v1.2s }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0685

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140881	1054	1	0	0	0	1	2	1	0	0	140443	140279	139747	129681	63	80106	40100	30006	10000	30100	30000	10000	1269962	6723821	20172574	1	140661	140682	140685	131190	3	131780	70100	30200	10000	30000	60200	10000	30000	140458	140682	1	1	50201	100	99	100	40100	10000	10000	1	100	10002	2	1	10002	0	1	1	10000	1	1	1	1	0	0	3210	1	129	1	1	140195	40000	0	10	13	10000	20000	40100	140686	140459	140686	140686	140686
70205	140462	1054	1	0	1	0	1	2	1	0	0	140670	140279	139978	129987	25	80106	40100	30003	10000	30100	30000	10000	1269962	6723965	20172574	1	140661	140685	140685	131190	3	131780	70100	30200	10000	30000	60200	10000	30000	140458	140682	1	1	50201	100	99	100	40100	10000	10000	1	100	10002	1	1	10001	0	0	1	10000	1	1	1	1	2	0	3210	1	129	1	1	140192	40000	10	10	13	10000	20000	40100	140683	140686	140686	140459	140683
70204	140682	1054	1	1	0	0	0	2	0	0	0	140670	140279	139974	129987	25	80106	40100	30006	10000	30100	30000	10000	1268087	6713069	20172574	1	140661	140458	140685	131190	3	131780	70100	30200	10000	30000	60200	10000	30000	140685	140685	1	1	50201	100	99	100	40100	10000	10000	1	100	10003	2	1	10001	0	0	1	10000	1	1	1	1	0	0	3210	1	129	1	1	140195	40000	13	10	10	10000	20000	40100	140683	140683	140686	140686	140683
70204	140685	1054	1	1	1	0	0	2	0	0	0	140670	140279	139974	129985	25	80106	40100	30006	10000	30100	30000	10000	1269946	6723965	20172574	1	140434	140685	140685	131071	3	131777	70100	30200	10000	30000	60200	10000	30000	140685	140682	1	1	50201	100	99	100	40100	10000	10000	1	100	10002	2	1	10002	0	0	1	10001	1	1	0	1	1	0	3210	1	129	1	1	140195	40000	13	10	13	10000	20000	40100	140686	140686	140686	140686	140686
70204	140685	1053	1	0	0	0	0	2	0	0	0	140670	140276	139974	129985	25	80116	40100	30006	10000	30100	30000	10000	1269962	6723965	20172574	1	140661	140458	140685	131190	3	131777	70100	30200	10000	30000	60200	10000	30000	140685	140458	1	1	50201	100	99	100	40100	10000	10000	1	100	10002	1	1	10001	0	1	1	10000	1	1	1	1	0	0	3210	1	129	1	1	140195	40000	10	10	13	10000	20000	40100	140686	140683	140459	140686	140686
70204	140458	1054	1	1	1	0	0	2	0	0	0	140670	140276	139974	129987	25	80106	40100	30006	10000	30100	30000	10000	1269962	6723965	20140295	1	140661	140685	140458	131190	3	131553	70100	30200	10000	30000	60200	10000	30000	140685	140682	1	1	50201	100	99	100	40100	10000	10000	1	100	10003	1	1	10001	0	1	1	10000	1	1	0	1	1	0	3210	1	129	1	1	139969	40000	13	10	0	10000	20000	40100	140683	140683	140683	140683	140686
70204	140685	1053	1	0	0	0	0	1	0	0	1	140673	140279	139974	129987	25	80103	40100	30006	10000	30100	30000	10000	1269962	6723965	20172574	1	140661	140685	140685	131187	3	131780	70100	30200	10000	30000	60200	10000	30000	140685	140682	1	1	50201	100	99	100	40100	10000	10000	1	100	10002	3	1	10001	0	0	1	10000	1	1	1	1	2	0	3210	1	129	1	1	140195	40000	13	0	13	10000	20000	40100	140683	140683	140459	140686	140686
70204	140682	1053	1	0	1	0	0	68	1	0	0	140667	140279	139974	129985	25	80103	40100	30006	10000	30100	30000	10000	1269962	6713069	20172574	1	140434	140685	140464	131190	3	131780	70100	30200	10000	30000	60200	10000	30000	140685	140682	1	1	50201	100	99	100	40100	10000	10000	1	100	10002	1	1	10002	0	1	18141	10007	1	1	1	1	0	0	3210	1	129	1	1	139969	40000	10	13	13	10000	20000	40100	140685	140683	140459	140459	140686
70204	140458	1054	1	1	0	0	0	2	0	0	0	140670	139866	139974	129987	25	80106	40100	30006	10000	30100	30000	10000	1269962	6723821	20172574	1	140434	140685	140685	131187	3	131780	70100	30200	10000	30000	60200	10000	30000	140685	140682	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	3	0	10001	0	1	1	10000	1	1	1	1	0	2	3210	1	129	1	1	139970	40000	13	13	13	10000	20000	40100	140687	140459	140686	140459	140459
70204	140685	1053	1	0	1	0	0	2	0	0	0	140670	140282	139972	129985	25	80103	40100	30003	10000	30100	30000	10000	1269946	6723965	20172574	1	140661	140685	140685	130964	3	131777	70100	30200	10000	30000	60200	10000	30000	140685	140682	1	1	50201	100	99	100	40100	10000	10000	1	100	10003	1	1	10002	0	1	1	10000	1	1	1	1	2	0	3210	1	129	1	1	140192	40000	10	13	13	10000	20000	40100	140459	140686	140686	140686	140686

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0682

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140682	1054	0	1	1	0	0	0	1	0	0	26	0	0	0	0	1	140443	140238	139747	129987	25	80013	40010	30006	10004	30010	30000	10000	1270493	6723965	20172574	0	140434	0	140682	140682	131197	3	131583	70010	30020	10000	30000	60020	10000	30000	140685	140682	1	1	50021	10	9	0	10	40010	10000	10000	1	10	10003	1	1	10002	0	1	1	1	10000	1	1	1	1	1	0	0	3142	17	122	12	16	140201	40000	13	10	13	10000	20000	40010	140686	140459	140459	140686	140683
70024	140458	1053	1	1	1	0	2	0	0	0	1	19	0	0	0	0	1	140670	139826	139974	129986	25	80016	40010	30006	10000	30010	30000	10000	1268578	6723965	20172574	0	140661	0	140685	140458	131200	3	131801	70010	30020	10000	30000	60020	10000	30000	140419	140682	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10003	1	0	10006	0	0	0	1	10000	1	1	1	1	1	0	0	3142	13	122	17	12	140204	40000	10	10	10	10000	20000	40010	140664	140684	140683	140683	140686
70024	140682	1054	1	1	0	0	1	0	0	1	0	2	0	1	0	0	2	140443	139826	139975	129989	25	80013	40010	30006	10000	30010	30000	10000	1270493	6713069	20172574	0	140661	0	140458	140458	131200	3	131809	70010	30020	10000	30000	60020	10000	30000	140682	140682	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10003	2	1	10001	0	0	1	1	10000	1	1	1	1	2	0	0	3169	11	122	16	15	140201	40000	13	10	13	10000	20000	40010	140686	140686	140459	140686	140686
70024	140685	1053	1	1	0	0	1	0	0	0	0	2	0	0	0	0	1	140670	140238	139750	129987	25	80013	40010	30006	10000	30010	30000	10000	1270493	6713069	20172574	0	140661	0	140682	140458	131197	3	131812	70010	30020	10000	30000	60020	10000	30000	140685	140682	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10001	2	1	10001	0	0	0	1	10000	1	1	0	1	0	0	0	3142	16	121	15	12	139978	40000	13	0	13	10000	20000	40010	140683	140686	140459	140686	140683
70024	140685	1052	1	1	1	0	0	0	0	0	0	2	0	1	0	0	2	140670	139826	139974	129762	25	80016	40010	30006	10000	30010	30000	10000	1270547	6699180	20172574	0	140662	0	140682	140682	131200	3	131806	70010	30179	10000	30000	60020	10000	30000	140685	140682	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10003	3	0	10003	0	0	1	10	10000	1	1	1	1	1	0	0	3142	13	121	14	18	140204	40000	13	0	13	10000	20000	40010	140459	140459	140460	140687	140595
70024	140458	1054	1	1	0	0	1	0	0	0	0	1	0	1	0	0	1	140443	140235	139974	129987	25	80016	40010	30006	10000	30010	30000	10000	1270465	6723965	20173438	0	140658	3	140458	140685	131200	3	131583	70010	30020	10000	30000	60020	10000	30000	140682	140631	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10002	2	1	10002	0	0	0	1	10000	1	1	1	1	1	0	0	3142	13	122	12	16	140204	40000	10	10	10	10000	20000	40010	140683	140459	140686	140684	140686
70024	140458	1054	1	1	0	0	1	0	0	0	0	2	0	0	0	0	1	140670	140238	139747	129987	25	80016	40010	30006	10000	30010	30000	10000	1270493	6713069	20173015	0	140434	0	140458	140685	130974	3	131583	70010	30020	10000	30000	60020	10000	30000	140453	140686	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10001	2	1	10002	0	0	0	1	10000	1	1	1	1	0	0	0	3142	14	122	11	20	140094	40000	13	0	13	10000	20000	40010	140683	140683	140683	140683	140686
70024	140685	1054	1	1	1	0	2	0	0	0	0	2	0	0	0	0	2	140667	139826	139974	129762	25	80013	40010	30020	10000	30010	30000	10000	1270493	6723965	20173015	0	140434	0	140685	140458	131200	37	131502	71022	30020	10053	30316	60020	10106	30159	140504	140710	2	1	50021	10	9	0	10	40010	10000	10000	0	10	10002	1	1	10001	1	0	3	7	10003	1	1	0	1	1	0	0	3144	14	122	14	10	140201	40000	0	0	10	10000	20000	40010	140385	140459	140686	140634	140683
70024	140687	1054	1	1	1	0	1	1	1	0	0	2	0	1	0	0	1	140667	139750	139747	129985	25	80016	40010	30006	10000	30010	30000	10000	1270493	6713069	20172574	0	140661	0	140682	140458	130974	20	131812	70349	30336	10106	30000	60338	10106	30316	140201	140283	4	1	50021	10	9	0	10	40010	10000	10000	1	10	10001	2	1	10001	0	1	0	4	10000	1	1	1	1	0	0	1	3142	16	121	15	18	140201	40000	13	0	10	10000	20000	40010	140459	140686	140686	140426	140459
70024	140683	1053	1	1	1	0	0	0	1	0	0	176	0	0	0	0	1	140670	140241	139974	129727	25	80016	40010	30006	10001	30152	30295	10000	1270474	6723821	20172574	0	140661	0	140685	140685	130974	20	131809	70010	30178	10000	30000	60020	10000	30000	140682	140458	2	1	50021	10	9	0	10	40010	10000	10000	0	10	10002	1	1	10004	0	0	0	16	10000	1	1	1	1	3	0	0	3142	14	122	10	14	139978	40000	13	0	13	10000	20000	40010	140686	140459	140686	140686	140686

Test 4: throughput

Count: 8

Code:

  ld2 { v0.2s, v1.2s }, [x6]
  ld2 { v0.2s, v1.2s }, [x6]
  ld2 { v0.2s, v1.2s }, [x6]
  ld2 { v0.2s, v1.2s }, [x6]
  ld2 { v0.2s, v1.2s }, [x6]
  ld2 { v0.2s, v1.2s }, [x6]
  ld2 { v0.2s, v1.2s }, [x6]
  ld2 { v0.2s, v1.2s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	0e	0f	1e	22	23	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240205	40059	300	0	1	0	0	41	1	0	1	40049	8	8	25	240100	100	160082	80000	100	160000	80000	500	418403	4560014	1	40045	40064	40041	9973	0	3	10017	240100	200	80000	160000	200	80000	160000	40059	40059	1	1	80201	100	99	100	100	80000	80000	1	100	80000	37	80000	0	0	80035	6	0	31	0	0	5110	2	16	2	2	40061	18	10	10	80000	160000	100	40065	40065	40065	40060	40060
240204	40059	300	0	0	0	0	41	0	0	1	40028	8	0	25	240182	100	160000	80000	100	160000	80000	500	419004	1845094	0	40045	40041	40064	9973	0	3	10022	240100	200	80000	160000	200	80000	160000	40041	40064	1	1	80201	100	99	100	100	80000	80000	0	100	80000	37	80035	0	0	80035	6	0	31	41	0	5110	2	16	2	2	40061	0	10	14	80000	160000	100	40042	40042	40060	40060	40042
240204	40059	300	0	0	0	0	41	0	0	0	40044	10	8	25	240182	100	160000	80000	100	160000	80000	500	419006	5439994	1	40045	40041	40064	9973	0	3	9999	240100	200	80000	160000	200	80000	160000	40064	40059	1	1	80201	100	99	100	100	80000	80000	0	100	80000	37	80035	0	35	80035	0	1	31	41	0	5110	2	16	2	2	40038	0	14	14	80000	160000	100	40065	40065	40065	40065	40060
240204	40041	300	0	0	0	0	41	1	0	0	40049	0	8	25	240182	100	160082	80000	100	160000	80000	500	418996	4560014	0	40022	40059	40041	9973	0	3	10022	240100	200	80000	160000	200	80000	160000	40064	40059	1	1	80201	100	99	100	100	80000	80000	0	100	80000	37	80000	0	35	80035	6	1	35	41	0	5110	2	16	2	2	40038	0	14	14	80000	160000	100	40065	40065	40065	40042	40042
240204	40064	300	0	0	0	0	0	0	0	0	40044	8	8	25	240100	100	160000	80000	100	160000	80000	500	418996	5439994	0	40045	40064	40064	9973	0	3	10022	240100	200	80000	160000	200	80000	160000	40059	40059	1	1	80201	100	99	100	100	80000	80000	0	100	80000	41	80035	1	40	80000	0	1	31	41	0	5110	2	16	2	2	40047	0	14	14	80000	160000	100	40051	40060	40065	40065	40060
240204	40064	300	0	0	0	0	0	0	0	1	40044	8	8	25	240100	100	160082	80000	100	160000	80000	500	418973	4560014	0	40045	40064	40064	9973	0	3	10022	240100	200	80000	160000	200	80000	160000	40041	40059	1	1	80201	100	99	100	100	80000	80000	0	100	80000	37	80000	0	0	80031	0	0	35	41	0	5110	2	16	2	2	40056	0	14	14	80000	160000	100	40065	40042	40060	40060	40065
240204	40041	300	0	0	0	0	41	1	0	0	40049	8	8	25	240182	100	160000	80000	100	160000	80000	500	418403	4560014	0	40045	40059	40064	9973	0	3	10022	240100	200	80000	160000	200	80000	160000	40064	40059	1	1	80201	100	99	100	100	80000	80000	0	100	80000	37	80031	0	35	80035	6	0	0	0	0	5110	2	16	2	2	40061	0	14	10	80000	160000	100	40042	40065	40042	40065	40065
240204	40064	300	0	0	0	0	41	0	0	0	40049	8	10	25	240182	100	160082	80000	109	160000	80000	500	418420	4560014	0	40022	40064	40041	9973	0	3	10017	240100	200	80000	160000	200	80000	160000	40064	40059	1	1	80201	100	99	100	100	80000	80000	1	100	80000	37	80000	0	35	80035	6	1	35	41	0	5110	2	16	2	2	40061	0	14	10	80000	160000	100	40060	40042	40065	40065	40042
240204	40059	300	0	0	0	0	90	1	0	0	40044	10	0	25	240170	100	160082	80000	100	160192	80000	500	417950	1845094	0	40045	40064	40064	9973	0	3	10017	240100	200	80000	160000	200	80000	160000	40064	40059	1	1	80201	100	99	100	100	80000	80000	0	100	80000	37	80031	0	0	80035	6	1	31	41	0	5110	2	16	2	2	40038	0	14	10	80000	160000	100	40065	40065	40065	40065	40042
240204	40064	299	0	0	0	0	41	0	0	0	40049	8	8	25	240100	100	160082	80000	100	160000	80000	500	418996	4560014	0	40045	40064	40064	9973	0	3	9999	240100	200	80000	160000	200	80000	160000	40120	40059	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80035	0	31	80035	6	1	31	41	0	5110	2	16	2	2	40061	0	10	0	80000	160000	100	40065	40065	40065	40065	40065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	24	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240025	40055	300	0	0	1	0	1	1	0	0	30	1	0	0	0	40040	0	11	11	0	0	25	240064	10	160054	80000	10	160000	80000	50	418724	1845674	1	40036	0	40055	40055	9996	0	3	10035	240010	20	80000	160000	20	80000	160000	40055	40055	1	1	80021	10	9	0	10	10	80000	80000	0	10	80000	0	30	80024	0	0	0	24	80024	6	1	0	30	0	0	0	5020	1	16	11	1	40052	0	6	80000	160000	10	40056	40056	40060	40056	40056
240024	40059	300	0	0	0	0	0	0	0	0	0	1	0	0	0	40040	0	11	11	0	0	25	240064	10	160054	80000	10	160000	80000	50	418745	3920014	0	40036	0	40055	40041	9996	0	3	10035	240010	20	80000	160000	20	80000	160000	40055	40055	1	1	80021	10	9	0	10	10	80000	80000	0	10	80000	0	30	80024	0	0	0	27	80000	6	0	24	37	0	0	0	5020	1	16	5	1	40052	6	6	80000	160000	10	40042	40056	40056	40042	40056
240024	40055	299	0	0	0	0	0	0	0	0	30	0	0	0	0	40040	0	11	11	0	0	25	240064	10	160054	80000	10	160000	80000	50	418745	3920014	1	40036	0	40055	40055	9996	0	3	10035	240010	20	80000	160000	20	80000	160000	40059	40055	1	1	80021	10	9	0	10	10	80000	80000	0	10	80000	0	30	80000	0	0	0	24	80024	6	1	24	30	0	0	0	5020	1	16	8	1	40052	6	6	80000	160000	10	40056	40056	40056	40056	40056
240024	40055	300	0	0	0	0	0	0	0	0	0	1	0	0	0	40040	0	10	0	0	0	25	240010	10	160054	80000	10	160000	80000	50	418745	3920014	1	40036	0	40055	40041	9996	0	3	10021	240010	20	80000	160000	20	80000	160000	40055	40055	1	1	80021	10	9	0	10	10	80000	80000	0	10	80000	0	30	80024	0	0	0	24	80024	6	1	24	30	0	0	0	5020	1	16	7	2	40052	6	6	80000	160000	10	40056	40056	40056	40042	40056
240024	40055	300	0	0	0	0	0	0	0	0	30	0	0	0	0	40040	0	11	11	0	0	25	240064	10	160054	80000	10	160000	80000	50	419021	3920014	1	40036	0	40055	40055	9996	0	3	10023	240010	20	80000	160000	20	80000	160000	40055	40055	1	1	80022	10	9	0	10	10	80000	80000	1	10	80000	0	30	80024	0	0	0	24	80024	6	1	24	37	0	0	0	5020	1	16	1	1	40052	6	6	80000	160000	10	40042	40060	40056	40056	40056
240024	40055	300	0	0	0	0	0	0	0	0	30	1	0	0	0	40040	0	11	11	0	0	25	240064	10	160054	80000	10	160000	80000	50	418745	3920014	1	40036	0	40055	40055	9996	0	3	10035	240010	20	80000	160000	20	80000	160000	40056	40055	1	1	80021	10	9	0	10	10	80000	80000	0	10	80000	0	30	80024	0	0	0	24	80024	6	1	24	0	0	0	0	5020	1	16	1	1	40052	6	6	80000	160000	10	40042	40056	40056	40056	40042
240024	40055	300	0	0	0	0	0	0	0	0	30	0	0	0	0	40044	0	11	11	0	0	25	240064	10	160054	80000	10	160000	80000	50	418745	3920014	1	40036	0	40041	40055	9996	0	3	10035	240010	20	80000	160000	20	80000	160000	40055	40055	1	1	80021	10	9	0	10	10	80000	80000	0	10	80000	0	30	80024	0	0	0	24	80024	6	1	0	37	0	0	1	5020	1	16	1	1	40038	6	6	80000	160000	10	40056	40056	40060	40056	40056
240024	40055	300	0	0	0	0	0	0	0	0	30	1	0	0	0	40040	0	11	11	0	0	25	240064	10	160054	80000	10	160000	80000	50	418736	3920014	1	40036	0	40055	40055	9996	0	3	10035	240010	20	80000	160000	20	80000	160000	40055	40055	1	1	80021	10	9	0	10	10	80000	80000	0	10	80000	0	30	80024	0	0	0	31	80024	6	1	24	30	0	0	0	5020	1	16	1	1	40052	6	6	80000	160000	10	40042	40056	40042	40042	40056
240024	40041	300	0	0	0	0	0	0	0	0	0	1	0	0	0	40026	0	0	10	0	0	25	240080	10	160054	80000	10	160000	80000	50	418745	3920014	1	40036	0	40055	40055	9996	0	3	10028	240010	20	80000	160000	20	80000	160000	40055	40041	1	1	80021	10	9	0	10	10	80000	80000	0	10	80000	0	35	80024	0	0	0	24	80024	6	1	0	30	0	0	0	5020	1	16	1	1	40052	6	6	80000	160000	10	40056	40056	40042	40056	40056
240024	40055	300	0	0	0	0	0	0	0	0	30	0	0	0	0	40040	0	13	11	0	0	25	240064	10	160054	80000	10	160000	80000	50	418692	3920014	1	40036	0	40055	40055	9996	0	3	10045	240010	20	80000	160000	20	80000	160000	40065	40065	1	1	80021	10	9	0	10	10	80000	80000	1	10	80018	17	41	80053	1	0	2	57	80037	6	1	52	41	16	1	0	5046	1	16	1	1	40052	6	6	80000	160000	10	40056	40056	40056	40056	40056

LD2 (multiple, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations