Firestorm: LD2 (multiple, 4H) measurements

Code:

  ld2 { v0.4h, v1.4h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.006

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	0e	0f	1e	22	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
63005	29457	218	18	0	26	1	1	477	1	4647	28804	0	0	17162	3004	2004	1000	2000	1000	5000	23856	2	22747	29069	29263	3	10	3000	1000	2000	1000	2000	29177	29077	1	1	61001	1000	1000	1	1000	2	1000	1	0	0	1000	2	1	2	0	0	12855	9273	6831	3105	10	68	20696	3064	3813	11	52	51	28650	16492	13841	15101	1000	2000	29191	29236	29218	29177	29382
63004	29276	220	19	0	24	0	0	315	0	4537	28783	1	0	17178	3008	2006	1000	2000	1000	5000	23889	4	22420	29099	29312	3	10	3000	1000	2000	1000	2000	29167	29191	1	1	61001	1000	1000	0	1000	2	1000	0	0	0	1001	3	1	2	0	0	12788	9573	6898	3085	7	53	20518	3131	3812	11	53	51	28592	16149	13821	15007	1000	2000	29231	29092	29201	29224	29183
63004	29193	218	20	0	22	0	0	392	1	4639	28794	0	0	17107	3004	2006	1000	2000	1000	5000	23875	3	22688	29046	29345	3	10	3000	1000	2000	1000	2000	29209	29176	1	1	61001	1000	1000	0	1000	2	1000	0	0	0	1001	2	0	3	0	0	13029	9307	6909	3028	7	56	20613	3113	3817	13	50	48	28605	16171	14020	14969	1000	2000	29260	29226	29262	29274	29316
63004	29219	219	21	0	25	0	0	22	1	4552	28824	0	0	17139	3006	2004	1000	2000	1000	5000	23888	0	22701	29172	29287	3	10	3000	1000	2000	1000	2000	29153	29125	1	1	61001	1000	1000	0	1000	3	1001	0	0	0	1000	2	1	2	0	0	12847	9171	6891	3211	11	52	20556	3055	3814	9	43	51	28578	16059	13955	15087	1000	2000	29271	29239	29187	29203	29150
63004	29338	220	20	0	16	0	0	2	1	4664	28857	0	0	17134	3004	2004	1000	2000	1000	5000	23879	0	22723	29192	29261	3	10	3000	1000	2000	1000	2000	29237	29149	1	1	61001	1000	1000	0	1000	2	1000	0	0	0	1000	2	0	2	0	0	12964	9153	6848	3052	10	45	20595	3064	3816	8	48	52	28534	16306	13823	14787	1000	2000	29245	29269	29208	29278	29288
63004	29209	219	25	0	23	0	0	281	1	4634	28836	0	0	17095	3006	2006	1000	2000	1000	5000	23865	3	22725	29078	29232	3	10	3000	1000	2000	1000	2000	29216	29164	1	1	61001	1000	1000	0	1000	2	1000	0	0	3	1000	2	0	3	0	0	13173	9267	6827	3054	10	60	20607	3179	3819	7	58	54	28350	16113	13869	14974	1000	2000	29158	29171	29257	29267	29299
63004	29301	220	21	0	19	0	0	2	0	4964	28955	0	0	17170	3006	2006	1000	2000	1000	5000	23902	2	22777	29112	29364	3	10	3000	1000	2000	1000	2000	29088	29217	1	1	61001	1000	1000	0	1000	2	1000	0	0	0	1000	2	0	2	0	0	12905	9122	6833	3084	14	46	20431	3121	3814	9	58	55	28386	16090	13741	14970	1000	2000	29312	29224	29280	29252	29238
63004	29229	220	22	0	23	1	1	318	1	4558	28808	0	1	17185	3004	2004	1000	2000	1000	5000	23874	3	22737	29165	29232	3	10	3000	1000	2000	1000	2000	29165	29158	1	1	61001	1000	1000	0	1000	3	1000	0	0	0	1000	3	0	2	0	0	12922	9155	6901	3056	8	52	20576	3069	3816	13	47	55	28359	16222	13920	15011	1000	2000	29345	29273	29297	29248	29189
63004	29192	219	20	0	21	0	0	387	1	4720	28803	0	0	17184	3004	2004	1000	2000	1000	5000	23868	0	22704	29026	29262	3	10	3000	1000	2000	1000	2000	29158	29237	1	1	61001	1000	1000	0	1000	3	1000	0	0	0	1000	2	0	3	0	416	13045	9504	6902	3115	9	49	20831	3242	3815	9	60	54	28745	16229	13984	15070	1000	2000	29638	29270	29433	29633	29495
63004	29224	222	20	0	18	0	0	398	1	4556	28817	0	0	17109	3006	2004	1000	2000	1000	5000	23877	5	22712	29044	29381	3	10	3000	1000	2000	1000	2000	29280	29043	1	1	61001	1000	1000	0	1000	3	1001	0	0	0	1001	2	1	3	0	0	12942	9206	6825	3047	12	51	20617	3138	3816	5	48	48	28383	16415	13591	15017	1000	2000	29266	29209	29255	29266	29351

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.4h, v1.4h }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140051	1049	0	0	0	1	1	0	0	6	0	1	0	0	140036	139404	139344	129357	25	80103	40100	30003	10000	30100	30000	10000	1264354	6693584	20081843	1	140020	140051	140051	130559	3	131147	70100	30200	10000	30190	60200	10000	30000	140051	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	10000	1	1	0	0	3210	1	128	1	1	139564	40000	10	10	10	10000	20000	40100	140052	140052	140052	140052	140052
70204	140051	1049	0	0	0	0	0	0	0	10	0	1	0	0	140036	139561	139344	129357	25	80100	40100	30000	10000	30100	30165	10000	1264354	6693584	20081843	1	140086	140051	140051	130559	3	131147	70100	30200	10000	30000	60200	10000	30000	140051	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	0	1	0	0	3210	1	128	1	1	139564	40000	10	10	10	10000	20000	40100	140075	140057	140054	140052	140052
70204	140051	1049	0	0	0	0	0	0	0	1	0	1	0	0	140020	139561	139344	129357	25	80103	40100	30003	10000	30100	30000	10000	1264354	6693584	20081843	1	140066	140051	140035	130559	3	131126	70100	30200	10000	30000	60200	10000	30000	140051	140035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	0	0	3210	1	128	1	1	139564	40000	0	10	0	10000	20000	40100	140052	140052	140052	140052	140052
70204	140051	1049	0	0	0	0	0	0	0	1	0	1	0	0	140036	139404	139344	129341	25	80103	40100	30003	10000	30100	30000	10000	1264354	6693632	20081843	1	140058	140051	140051	130559	3	131147	70100	30200	10000	30000	60200	10000	30000	140036	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	0	0	3210	1	128	1	1	139544	40000	10	0	10	10000	20000	40100	140052	140052	140052	140052	140052
70204	140035	1049	0	0	0	0	0	0	0	1	0	0	0	0	140036	139561	139344	129357	25	80100	40100	30000	10000	30100	30000	10000	1264310	6692791	20081843	1	140032	140051	140035	130531	3	131147	70100	30200	10000	30000	60200	10000	30000	140051	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	10000	1	1	0	0	3210	1	128	1	1	139544	40000	10	10	10	10000	20000	40100	140052	140052	140052	140052	140055
70204	140051	1049	0	0	0	0	1	0	0	1	0	1	0	0	140036	139561	139348	129360	25	80103	40100	30000	10000	30100	30000	10000	1264354	6693584	20081843	1	140030	140051	140035	130559	3	131147	70100	30200	10000	30000	60200	10000	30000	140035	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	3210	1	128	1	1	139564	40000	10	13	10	10000	20000	40100	140052	140052	140052	140052	140036
70204	140051	1049	0	0	0	0	0	0	0	1	0	1	0	0	140036	139561	139325	129357	25	80103	40100	30003	10000	30100	30000	10000	1264354	6693584	20081843	1	140045	140051	140051	130624	3	131147	70100	30200	10000	30000	60200	10000	30000	140051	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	3210	1	128	1	1	139544	40000	0	10	10	10000	20000	40100	140052	140036	140052	140052	140052
70204	140051	1049	0	1	0	0	0	0	0	1	0	0	0	0	140036	139561	139325	129357	25	80100	40100	30003	10000	30100	30000	10000	1264354	6692791	20081843	1	140034	140056	140054	130559	3	131126	70100	30200	10000	30000	60200	10000	30000	140035	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	3210	1	128	2	1	139564	40000	10	10	10	10000	20000	40100	140036	140036	140036	140036	140036
70204	140051	1049	0	0	0	0	0	0	0	0	0	1	0	0	140037	139404	139344	129357	25	80103	40100	30003	10000	30100	30000	10000	1264310	6693584	20081843	1	140098	140051	140051	130559	3	131147	70100	30200	10000	30000	60200	10000	30000	140035	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	10000	1	1	0	0	3210	1	128	1	1	139564	40000	10	10	10	10000	20000	40100	140052	140052	140036	140052	140055
70204	140051	1048	0	1	0	0	0	0	0	0	0	1	0	0	140020	139561	139344	129357	25	80103	40100	30000	10000	30100	30000	10000	1264310	6692791	20081843	1	140095	140035	140051	130559	3	131126	70100	30200	10000	30000	60200	10000	30000	140051	140051	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	0	10000	0	1	0	0	3210	1	17	1	1	139564	40000	10	10	0	10000	20000	40100	140052	140052	140052	140052	140052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	23	24	3a	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140051	1049	0	1	0	0	1	0	0	1	1	1	0	0	1	140047	139564	139346	129360	25	80013	40010	30003	10000	30010	30000	10000	1264819	6693731	20081843	1	140033	0	140054	140051	130553	3	131179	70010	30020	10000	30000	60020	10000	30000	140054	140051	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	3142	13	121	15	11	139576	40000	0	10	13	10000	20000	40010	140052	140052	140052	140052	140052
70024	140035	1049	0	1	0	0	1	0	0	1	2	0	0	0	3	140045	139614	139332	129365	25	80016	40015	30003	10000	30010	30000	10000	1264756	6694022	20080361	1	140033	3	140060	140057	130572	3	131179	70010	30020	10000	30000	60020	10000	30000	140054	140035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3142	13	121	9	13	139573	40000	13	10	0	10000	20000	40010	140052	140055	140055	140036	140036
70024	140035	1049	0	1	0	0	1	0	0	1	0	1	0	0	2	140039	139564	139344	129360	25	80013	40010	30003	10000	30010	30000	10000	1264819	6693731	20081843	0	140036	0	140041	140057	130578	3	131185	70010	30020	10000	30000	60020	10000	30000	140060	140057	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	3	1	10003	0	0	1	10000	0	0	1	0	0	3144	14	121	12	16	139576	40000	13	10	10	10000	20000	40010	140055	140055	140055	140055	140055
70024	140054	1049	0	1	0	0	1	0	0	1	1	0	0	0	1	140020	139564	139346	129357	25	80013	40010	30003	10000	30010	30000	10000	1264819	6693731	20081843	1	140027	0	140054	140054	130572	3	131179	70010	30020	10000	30000	60020	10000	30000	140035	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	1	0	3142	12	120	11	13	139582	40000	0	10	0	10000	20000	40010	140058	140061	140061	140042	140061
70024	140060	1049	1	1	1	1	1	0	0	1	23	0	0	0	1	140045	139611	139350	129365	25	80013	40010	30003	10000	30010	30000	10000	1264728	6693878	20080361	1	140030	0	140054	140054	130572	3	131179	70010	30020	10000	30000	60020	10000	30000	140054	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	0	10000	1	0	1	0	0	3142	15	121	12	12	139577	40000	13	10	13	10000	20000	40010	140055	140055	140036	140055	140055
70024	140054	1049	0	1	0	0	1	0	0	1	1	1	0	0	1	140039	139564	139344	129360	25	80013	40010	30000	10000	30010	30000	10000	1264819	6693731	20081843	1	140036	0	140057	140057	130578	3	131167	70010	30020	10000	30000	60020	10000	30000	140041	140057	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	3	1	10000	0	0	0	10000	1	1	1	1	1	3142	15	121	18	10	139583	40000	13	10	13	10000	20000	40010	140061	140042	140058	140061	140115
70024	140057	1049	1	1	0	1	1	1	0	1	2	0	0	0	1	140045	139614	139352	129365	25	80016	40010	30003	10000	30010	30000	10000	1264728	6694022	20082745	1	140030	0	140054	140054	130572	3	131179	70010	30020	10000	30000	60020	10000	30000	140051	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3142	15	121	13	13	139557	40000	13	10	13	10000	20000	40010	140055	140055	140055	140055	140112
70024	140054	1049	0	1	0	0	1	0	0	1	10	0	0	0	1	140039	139564	139346	129357	25	80013	40010	30005	10000	30010	30000	10000	1264783	6693731	20081843	1	140027	0	140051	140051	130572	3	131179	70010	30020	10000	30000	60020	10000	30000	140054	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3142	13	121	12	9	139576	40000	13	0	13	10000	20000	40010	140055	140055	140055	140055	140055
70024	140054	1049	0	1	0	0	1	0	0	1	2	0	0	0	1	140026	139410	139352	129365	25	80016	40010	30006	10000	30010	30000	10000	1264794	6693878	20082745	1	140033	0	140041	140060	130578	3	131185	70010	30020	10000	30000	60020	10000	30000	140060	140041	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10003	6	0	0	10004	1	0	1	0	2	3142	13	120	9	12	139557	40000	9	6	9	10000	20000	40010	140036	140051	140144	140051	140037
70024	140050	1048	0	1	0	0	1	0	1	1	5	0	0	1	1	140038	139608	139345	129359	25	80013	40010	30006	10000	30010	30000	10000	1264717	6693877	20082149	0	140026	0	140047	140342	130568	3	131203	70685	30020	10000	30000	60020	10000	30000	140149	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	0	10000	0	0	1	0	0	3142	15	121	10	13	139572	40000	9	6	9	10000	20000	40010	140051	140051	140051	140036	140051

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.4h, v1.4h }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0458

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140285	1052	0	1	0	1	1	1	1	0	0	0	1	0	0	0	1	140449	139405	139551	129564	25	80103	40100	30003	10000	30100	30000	10000	1266220	6703564	20079595	1	140440	140259	140259	130532	3	131354	70100	30200	10000	30000	60200	10000	30000	140259	140464	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3212	6	129	7	7	139771	40000	9	6	9	10000	20000	40100	140260	140260	140037	140260	140037
70204	140036	1052	0	1	0	0	1	0	0	0	0	0	7	0	0	0	1	140024	139405	139551	129564	25	80103	40100	30003	10000	30100	30000	10000	1264319	6703564	20079595	1	140235	140464	140036	130769	3	131354	70100	30200	10000	30000	60200	10000	30000	140041	140467	2	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	2	0	0	10000	0	0	1	0	0	3212	8	155	7	7	139771	40000	9	6	9	10000	20000	40100	140260	140260	140663	140260	140037
70204	140259	1052	0	6	0	0	1	0	1	1	0	0	2	0	0	0	1	140443	139866	139967	129762	25	80103	40100	30006	10000	30100	30000	10000	1270024	6723625	20172426	1	140434	140759	140678	131183	3	131774	70100	30200	10000	30000	60200	10000	30000	140682	140685	5	1	50201	100	99	100	40100	10000	10000	0	100	10003	2	1	10001	1	1	1	10000	1	1	1	1	0	3212	5	129	7	7	139969	40000	0	9	9	10000	20000	40100	140682	140682	140459	140679	140679
70204	140681	1054	1	1	1	0	1	0	0	0	0	0	2	0	0	0	1	140666	140262	139972	129984	154	80103	40100	30006	10000	30100	30000	10000	1270024	6723625	20140295	1	140657	140681	140678	131186	3	131834	70100	30200	10000	30000	60200	10000	30633	140458	140678	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10006	0	1	1	10000	1	1	0	1	0	3212	6	129	7	5	140191	40000	9	0	0	10000	20000	40100	140679	140682	140459	140682	140877
70204	140678	1054	1	1	0	0	1	0	0	1	0	0	2	0	0	0	2	140666	140262	139970	129762	154	80106	40100	30006	10000	30100	30000	10000	1268087	6723772	20140295	1	140235	140036	140464	130766	3	131127	70100	30200	10000	30000	60200	10000	30000	140464	140465	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	1	0	3212	9	129	8	6	140191	40000	9	9	0	10000	20000	40100	140682	140682	140679	140459	140682
70204	140678	1054	1	1	0	0	1	0	0	0	0	0	2	0	0	0	1	140443	139866	139970	129981	25	80106	40100	30006	10000	30100	30000	10000	1268087	6713069	20171978	1	140434	140458	140681	131186	3	131776	70100	30200	10000	30000	60200	10000	30000	140458	140458	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	1	0	10001	0	0	1	10000	1	1	0	1	1	3214	7	129	7	8	139969	40000	9	9	9	10000	20000	40100	140459	140682	140682	140459	140459
70204	140458	1054	1	1	0	0	1	0	0	1	0	0	2	0	0	0	2	140663	140262	139747	129981	25	80103	40100	30009	10000	30100	30000	10000	1268087	6713069	20172714	1	140657	140681	140681	131183	3	131776	70100	30200	10000	30634	60200	10000	30000	140681	140458	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10006	0	0	1	10000	1	1	1	1	0	3212	8	129	6	7	140003	40000	9	9	9	10000	20000	40100	140459	140459	140682	140682	140682
70204	140681	1053	1	1	1	0	1	0	1	1	0	0	1	0	0	0	1	140758	139787	139970	129762	25	80103	40100	30006	10000	30100	30000	10000	1270042	6713165	20140295	1	140657	140681	140681	131186	3	131776	70100	30200	10000	30639	60200	10000	30000	140678	140458	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10001	0	0	1	10000	1	1	1	1	1	3322	7	129	7	7	140191	40000	0	0	0	10000	20000	40100	140459	140682	140679	140459	140682
70204	140681	1054	1	3	1	0	1	0	1	1	0	0	14	352	1	0	2	140666	140216	139747	129981	25	80106	40100	30006	10000	30665	30000	10000	1268087	6713069	20171978	1	140434	140678	140678	131186	3	131669	70100	30200	10000	30000	60200	10000	30000	140681	140678	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	1	1	10001	1	2	1	10000	1	1	1	1	1	3212	8	129	9	5	140194	40021	9	0	9	10000	20000	40100	140682	140459	140682	140682	140682
70204	140458	1052	1	1	1	0	1	0	1	1	0	0	1	0	0	0	2	140666	140262	139970	129984	25	80106	40100	30006	10000	30100	30000	10000	1270024	6723772	20172426	1	140655	140681	140458	130964	3	131699	70100	30200	10000	30000	60200	10000	30000	140681	140458	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	3	1	10001	3	0	1	10000	0	1	1	1	1	3212	7	129	8	9	140191	40000	9	9	6	10000	20000	40100	140662	140459	140682	140682	140679

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0678

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140594	1054	1	1	0	0	1	0	0	2	1	0	1	140663	140173	139747	129981	25	80016	40010	30006	10000	30010	30000	10000	1270547	6723625	20171978	0	140654	140678	140678	131193	0	3	131802	70010	30020	10000	30000	60020	10000	30000	140296	140496	1	1	50021	10	9	10	40010	10000	10000	1	10	10003	2	1	10002	0	0	1	136	10000	1	1	1	1	2	0	0	3140	2	122	2	2	140197	40000	6	6	0	10000	20000	40010	140679	140679	140679	140679	140679
70024	140680	1053	1	0	0	0	0	0	0	1	0	0	0	140449	139862	139753	129768	25	80013	40010	30003	10000	30010	30000	10000	1270547	6723625	20171978	0	140654	140678	140678	131193	0	3	131802	70010	30020	10000	30000	60020	10000	30000	140678	140678	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	2	1	10002	0	0	0	16563	10000	1	1	1	1	0	0	0	3140	2	122	2	2	140197	40000	6	0	6	10000	20000	40010	140679	140679	140679	140679	140679
70024	140712	1054	1	1	1	0	1	0	0	10	1	0	1	140663	140173	139967	129981	25	80016	40010	30003	10000	30010	30000	10000	1270547	6723625	20171978	0	140654	140678	140678	131193	0	3	131802	70010	30020	10000	30000	60020	10000	30000	140678	140678	1	1	50021	10	9	10	40010	10000	10000	1	10	10003	2	1	10002	0	69	1	37	10000	1	1	0	1	0	0	0	3140	2	122	2	2	140197	40000	6	0	6	10000	20000	40010	140679	140679	140679	140681	140704
70024	140458	1053	1	0	1	0	0	0	0	2	1	0	1	140663	140173	139967	129981	25	80016	40010	30003	10000	30010	30000	10000	1270547	6723625	20171978	0	140654	140678	140678	131193	0	3	131802	70010	30020	10000	30000	60020	10000	30000	140678	140678	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10001	0	58	0	1	10000	1	1	1	1	1	0	0	3140	2	122	2	2	140197	40000	6	6	6	10000	20000	40010	140679	140679	140679	140679	140681
70024	140678	1054	1	1	0	0	1	0	0	2	0	0	1	140663	140173	139967	129981	25	80016	40010	30006	10000	30010	30000	10000	1270547	6723625	20171978	0	140654	140678	140678	131193	0	3	131802	70010	30020	10000	30000	60020	10000	30000	140678	140678	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	1	10001	0	2	0	1	10000	1	1	1	1	0	0	0	3140	2	122	2	2	140198	40000	6	6	6	10000	20000	40010	140679	140679	140679	140679	140679
70024	140680	1054	1	1	1	0	1	0	0	2	1	0	1	140663	140173	139967	129981	25	80016	40010	30006	10000	30010	30000	10000	1270547	6723625	20171978	0	140655	140678	140678	131193	0	3	131802	70010	30020	10000	30000	60020	10000	30000	140678	140678	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	1	10001	0	2	2	1	10000	1	1	0	1	1	0	0	3140	2	122	2	2	140197	40000	6	6	0	10000	20000	40010	140679	140679	140679	140679	140684
70024	140678	1054	1	1	1	1	1	0	0	31	0	0	1	140663	140173	139967	129981	25	80016	40010	30006	10000	30010	30000	10000	1270547	6723625	20171978	0	140654	140678	140678	131193	0	3	131802	70010	30020	10000	30000	60020	10000	30000	140678	140678	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	0	10001	0	2	1	1	10000	1	1	1	1	1	0	0	3140	2	121	2	2	140197	40000	0	6	6	10000	20000	40010	140679	140679	140470	140679	140679
70024	140678	1054	1	1	1	0	1	0	0	2	0	0	0	140663	140173	139967	130046	25	80016	40010	30006	10000	30010	30000	10000	1270547	6723625	20171978	0	140654	140678	140678	131193	0	3	131802	70010	30020	10000	30000	60020	10000	30000	140678	140678	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	1	10001	0	3	1	1	10000	1	1	1	1	0	1	0	3140	2	122	2	2	140197	40000	6	6	6	10000	20000	40010	140679	140679	140679	140679	140679
70024	140678	1053	1	0	0	0	0	0	0	443	1	0	1	140663	140173	139969	129981	25	80016	40010	30006	10000	30010	30000	10000	1270547	6723625	20171978	1	140654	140678	140678	131193	0	3	131583	70010	30020	10000	30000	60020	10000	30000	140678	140678	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	1	10002	0	0	1	1	10000	1	1	1	1	1	0	0	3140	2	122	2	2	140197	40000	6	6	6	10000	20000	40010	140679	140680	140679	140683	140679
70024	140678	1054	1	1	0	0	1	0	0	1	0	0	1	140663	140173	139973	130072	25	80016	40010	30006	10000	30010	30000	10000	1270547	6723625	20171978	0	140654	140681	140678	131193	0	3	131678	70010	30020	10000	30000	60020	10000	30000	140678	140678	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	1	10001	0	0	2	1	10000	1	1	1	1	2	0	0	3140	2	122	2	2	140197	40000	6	6	6	10000	20000	40010	140679	140679	140679	140679	140679

Test 4: throughput

Count: 8

Code:

  ld2 { v0.4h, v1.4h }, [x6]
  ld2 { v0.4h, v1.4h }, [x6]
  ld2 { v0.4h, v1.4h }, [x6]
  ld2 { v0.4h, v1.4h }, [x6]
  ld2 { v0.4h, v1.4h }, [x6]
  ld2 { v0.4h, v1.4h }, [x6]
  ld2 { v0.4h, v1.4h }, [x6]
  ld2 { v0.4h, v1.4h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	24	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240205	40079	300	1	0	0	1	1	41	1	0	0	0	40050	0	10	8	0	0	25	240100	100	160082	80000	100	160000	80000	500	417975	4560014	0	40040	0	40064	40064	9973	0	3	10022	240100	200	80000	160000	200	80000	160000	40064	40041	1	1	80201	100	99	0	100	100	80000	80000	1	100	80000	0	37	0	80000	0	1	0	35	80000	6	1	0	0	0	0	0	5110	1	16	1	1	40154	0	10	80000	160000	100	40065	40065	40042	40065	40065
240204	40064	300	0	0	0	0	0	41	1	0	0	1	40049	0	8	0	0	0	25	240100	100	160082	80000	100	160000	80000	500	418420	4560014	0	40040	0	40059	40064	9978	0	3	10017	240100	200	80000	160000	200	80000	160000	40064	40059	1	1	80201	100	99	0	100	100	80000	80000	0	100	80000	0	37	0	80000	0	0	0	35	80035	0	1	31	41	0	0	0	5110	1	16	1	1	40038	0	0	80000	160000	100	40070	40070	40070	40070	40065
240204	40041	300	0	0	0	0	0	37	0	0	0	0	40049	0	8	0	0	0	25	240100	100	160082	80000	100	160000	80000	500	417950	4560014	1	40045	0	40041	40064	9973	0	3	10022	240100	200	80000	160000	200	80000	160000	40064	40059	1	1	80201	100	99	0	100	100	80000	80000	0	100	80000	0	41	0	80035	0	44	0	3508	80031	6	0	31	37	0	0	0	5110	1	16	1	1	40056	0	14	80000	160000	100	40065	40042	40042	40065	40218
240204	40064	300	0	0	0	0	0	50	1	0	0	1	40049	0	10	8	0	0	25	240182	100	160070	80000	100	160000	80000	500	419022	1845094	0	40045	0	40064	40041	9973	0	3	10022	240100	200	80000	160000	200	80000	160000	40064	40059	1	1	80201	100	99	0	100	100	80000	80000	0	100	80000	0	37	0	80035	0	32	0	56	80035	6	0	0	41	0	0	0	5110	1	16	1	1	40061	14	0	80000	160000	100	40042	40060	40065	40042	40044
240204	40041	300	0	0	0	0	0	41	1	0	0	1	40049	0	0	8	0	0	25	240190	100	160084	80000	100	160000	80000	500	419216	5440750	1	40050	0	40041	40064	9978	0	3	10027	240100	200	80000	160000	200	80000	160000	40069	40047	1	1	80201	100	99	1	100	100	80000	80000	0	100	80000	0	0	0	80000	0	1	0	62	80000	0	0	0	41	0	0	0	5110	1	16	1	1	40066	13	13	80000	160000	100	40070	40070	40070	40070	40060
240204	40064	300	0	0	0	0	0	41	0	0	0	1	40044	0	8	8	0	0	25	240182	100	160082	80000	100	160000	80000	500	418996	4560014	0	40045	0	40041	40064	9973	0	3	10017	240100	200	80000	160000	200	80000	160000	40064	40041	1	1	80201	100	99	0	100	100	80000	80000	0	100	80000	0	41	0	80000	0	1	0	38	80031	6	1	31	41	0	0	0	5110	1	16	1	1	40061	14	14	80000	160000	100	40042	40065	40065	40042	40065
240204	40041	300	0	0	0	1	0	41	0	0	0	1	40044	0	8	8	0	0	25	240184	100	160084	80000	100	160000	80000	500	417950	4560014	0	40045	0	40064	40064	9973	0	3	10017	240100	200	80000	160000	200	80000	160000	40041	40059	1	1	80201	100	99	0	100	100	80000	80000	0	100	80000	0	37	0	80031	0	1	1	0	80000	6	1	31	0	0	0	0	5110	1	16	1	1	40061	10	0	80000	160000	100	40042	40042	40060	40060	40044
240204	40059	300	0	0	0	0	0	41	1	0	0	1	40026	0	8	8	0	0	25	240100	100	160084	80000	100	160000	80000	500	419006	5439994	1	40045	0	40041	40064	10014	65	23	10112	240100	200	80000	160000	200	80000	160000	40064	40041	1	1	80201	100	99	0	100	100	80000	80000	0	100	80000	0	0	0	80130	0	49	0	34	80000	6	0	0	41	0	0	0	5110	1	16	1	1	40061	0	10	80000	160000	100	40042	40042	40065	40065	40070
240204	40059	300	0	0	0	1	1	41	0	0	0	1	40049	0	8	8	0	0	25	240170	100	160082	80000	100	160000	80000	500	418420	4560014	0	40045	0	40064	40064	9973	0	3	10022	240100	200	80000	160000	200	80000	160000	40059	40059	1	1	80201	100	99	0	100	100	80000	80000	0	100	80000	0	37	0	80031	0	11	0	31	80035	6	1	58	45	16	0	0	5110	1	16	1	1	40061	14	0	80000	160000	100	40065	40065	40065	40065	40065
240204	40041	300	0	0	0	0	0	41	0	0	0	1	40026	0	0	8	0	0	25	240184	100	160090	80000	100	160000	80000	500	417950	4560014	0	40022	0	40064	40041	9973	0	3	9999	240100	200	80000	160000	200	80000	160000	40041	40041	1	1	80201	100	99	0	100	100	80000	80000	0	100	80000	0	37	0	80031	0	0	0	0	80000	6	1	0	41	0	0	0	5110	1	16	1	1	40056	0	10	80000	160000	100	40065	40065	40065	40065	40060

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5009

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240025	40070	300	1	1	1	0	0	87	1	0	3	40055	15	18	31	6	25	240106	10	160100	80000	10	160000	80000	50	415963	5440824	0	40037	40070	40070	9996	3	10050	240010	20	80000	160000	20	80000	160000	40070	40054	1	1	80021	10	9	10	10	80000	80000	0	10	80016	17	0	0	80068	1	1	2	72	80053	6	1	69	44	16	1	0	5020	2	16	2	4	40067	6	6	0	80000	160000	10	40071	40071	40071	40071	40167
240024	40055	300	1	1	0	0	1	78	0	0	2	40055	22	0	30	0	25	240104	10	160096	80000	10	160000	80000	50	419875	5440824	0	40051	40070	40065	10001	3	10050	240010	20	80000	160000	20	80000	160000	40070	40070	1	1	80021	10	9	10	10	80000	80000	0	10	80016	16	0	0	80069	1	0	2	73	80052	6	1	30	44	16	1	0	5020	3	16	3	4	40067	6	6	0	80000	160000	10	40071	40056	40071	40071	40071
240024	40070	300	1	1	1	0	0	42	0	0	1	40040	22	18	0	1	25	240114	10	160078	80000	10	160000	80000	50	419007	5440082	0	40036	40070	40070	10001	3	10035	240010	20	80000	160000	20	80000	160000	40055	40054	2	1	80021	10	9	10	10	80000	80000	0	10	80016	18	56	0	80069	0	0	1	41	80052	6	1	68	44	16	0	0	5020	3	16	3	1	40067	0	6	0	80000	160000	10	40071	40071	40056	40071	40056
240024	40070	300	1	0	0	0	0	78	1	0	1	40040	15	18	30	6	25	240066	10	160096	80000	10	160000	80000	50	416038	5440822	0	40036	40070	40070	10001	3	10050	240010	20	80000	160000	20	80000	160000	40055	40070	1	1	80021	10	9	10	10	80000	80000	0	10	80016	19	56	0	80069	2	1	2	73	80052	6	1	69	0	16	0	0	5020	6	16	4	4	40067	6	0	0	80000	160000	10	40680	40211	40080	40071	40071
240024	40056	300	1	1	1	0	0	78	0	0	0	40055	15	18	30	6	25	240066	10	160096	80000	10	160000	80000	50	415963	5440824	1	40051	40070	40070	9996	3	10050	240010	20	80000	160000	20	80000	160000	40070	40070	1	1	80021	10	9	10	10	80000	80000	0	10	80016	17	56	0	80068	2	0	1	72	80053	6	0	69	43	16	0	0	5020	3	16	4	5	40052	6	6	0	80000	160000	10	40071	40056	40074	40071	40056
240024	40070	300	1	0	0	1	0	77	0	0	1	40055	15	0	30	6	25	240064	10	160056	80000	10	160000	80000	50	416023	5440892	0	40051	40070	40070	10001	3	10050	240010	20	80000	160000	20	80000	160000	40055	40055	1	1	80021	10	9	10	10	80000	80000	0	10	80016	19	56	0	80068	0	0	1	70	80052	6	0	38	44	16	0	0	5020	3	16	5	3	40067	6	6	0	80000	160000	10	40071	40056	40071	40056	40071
240024	40055	300	1	0	1	0	0	79	1	0	0	40040	14	18	30	0	25	240064	10	160058	80000	10	160000	80000	50	415963	5440824	1	40051	40070	40070	10001	3	10050	240010	20	80000	160000	20	80000	160000	40070	40070	1	1	80021	10	9	10	10	80000	80000	0	10	80016	18	56	0	80068	1	0	0	60	80036	6	1	54	0	16	0	0	5020	3	16	5	2	40067	9	6	0	80000	160000	10	40071	40071	40071	40071	40056
240024	40070	300	1	1	1	0	0	79	1	0	1	40055	15	18	30	6	25	240066	10	160104	80000	10	160000	80000	50	415714	4000032	1	40036	40070	40055	10001	3	10035	240010	20	80000	160000	20	80000	160000	40070	40070	1	1	80021	10	9	10	10	80000	80000	0	10	80016	16	56	0	80068	1	0	1	72	80053	6	1	68	44	16	1	0	5020	4	16	3	5	40067	6	6	0	80000	160000	10	40071	40071	40056	40076	40071
240024	40070	300	1	1	1	0	0	78	1	0	1	40055	14	18	30	6	25	240066	10	160104	80000	10	160000	80000	50	415704	5440822	1	40051	40070	40055	10001	3	10050	240010	20	80000	160000	20	80000	160000	40055	40070	1	1	80021	10	9	10	10	80000	80000	0	10	80016	19	57	5	80038	2	54	0	72	80052	6	1	69	44	16	1	0	5020	2	16	4	4	40052	6	6	0	80000	160000	10	40071	40071	40071	40071	40071
240024	40070	300	1	1	1	0	0	78	1	0	1	40055	14	0	0	6	25	240114	10	160104	80000	10	160000	80000	50	416371	5440824	0	40036	40070	40070	10001	3	10050	240010	20	80000	160000	20	80000	160000	40055	40055	1	1	80021	10	9	10	10	80000	80000	0	10	80016	18	56	0	80068	1	0	1	73	80022	0	1	68	44	16	1	0	5020	3	16	3	1	40067	6	6	0	80000	160000	10	40071	40056	40071	40071	40071

LD2 (multiple, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations