Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2 (multiple, 4S)

Test 1: uops

Code:

  ld2 { v0.4s, v1.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.004

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.006

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)0e0f191e22243a3f43464951schedule uop (52)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f696b6d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd load (98)inst ldst (9b)9dl1d tlb access (a0)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)acafb5bbl1d cache miss ld nonspec (bf)cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaebec? ldst retires (ed)? simd retires (ee)f5f6f7f8fd
6400529346219151900090104630288020021711440062006200020002000100002390452279602908629237310400020002000200040002915129143116100110001000020006200200200444612953914069153082856202353118381016464928458162811337015024200020002924429297292332919629223
6400429305220181800030004608288170201705140002006200020002000100002381032279102894429338310400020002000200040002911529140116100110001000120000200205200200412855913568293077943202132986381215504528330164321334714997200020002923729307292832932629255
64004292792191616000650045812886000217029400420062000200020001000023892522762028997292373104000200020002000400029156291401161001100010000200042002002000626129199257686930681144203643053381016505428394160691342114919200020002928829301293252924829291
64004292652191618000371046052878602017064400020042000200020001000023898822803029083293513104000200020002000400029191291091161001100010000200042000022000404130269070682030461046203043110382014495028386162641348114828200020002925629226292122925129209
64004293092191717010570046242870800017131400420042000200020001000023886822762029113293473104000200020002000400029164291911161001100010000200062000022002404130139247683931691046202683062380910454228424162801336814608200020002913929220292732920929236
64004292992191716000281046622892200017098400420002000200020001000023884522852029069292773104000200020002000400029190290941161001100010000200062000002000404132219219683930851342202343081380912474828384161651344014930200020002925629317292342923629260
64004292612191513000800045712887200017101400020082000200020001000323873122900029072293083104000200020002000400029143290711161001100010000200042000072000406132189141689230441149202653108381913504728373164891324014990200020002928829256292542927329262
640042926521914150006004605288520001713740062006200020002000100002387862281902900729352310400020002000200040002915729081116100110001000020006200400200240613144923469243056646202873110381210484128520160671343214948200020002926329338293662934029270
6400429387219141400018104714287660001702340062006200020002000100002388632277402909029138310400020002000200040002907829096116100110001000020006200004200200612956923068203044854203563112381711504728472161981331914858200020002925629298293572929629216
6400429299219191800036104626286770201718440042006200020002000100002381452283702920529230310400020002000200040002920729087116100110001000120004200200200040412851922068833064844203083078381416475028403163401328214994200020002924829178292912927929325

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.4s, v1.4s }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0051

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f22233a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5l1d cache miss ld nonspec (bf)c2branch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020514004710490100000200011400328477112967025901034010030003200003010030000200001204418566920681218233711400851400511400511294893129934801003020020000300006020020000500001400511400471150201100991004010010000100000100200000220000000200002000032101161113978740000060200002000040100140052140036140052140052140052
802041400511049000000020001140032852941296822590103401003000320000301003000020000120441856692068121823371140023140035140047129505312991880100302002000030000602002000050000140047140035115020110099100401001000010000010020000002000000020000000003210116111397914000010010200002000040100140036140036140052140052140052
80204140051104900000006010114002184775129682259010340100300032000030100300002000012042832669187612181242114008714005114003512948931299348010030200200003000060200200005000014003514005111502011009910040100100001000001002000002200000002000022000321011611139787400001066200002000040100140052140036140052140052140052
80204140051104900000000010114003680130129682259010340100300032000030100300002000012044185669129012182337114002314003514003512948931299308010030200200003000060200200005000014003514004711502011009910040100100001000001002000000200001002000022000321011611139791400006610200002000040100140052140052140036140052140036
80204140051104900000002010114002084775129686259010340100300032000030100300002000012044185669206812182337114007614004914005412950131299348010030200200003000060200200005000014003514003511502011009910040100100001000001002000002200000002000022000321011611139791400006010200002000040100140036140036140036140048140036
802041400511049000000000001140020801301296862590103401003000320000301003000020000120438376692068121812421140050140125140047129507211299188010030200200003000060200200005000014004714004711502011009910040100100001000001002000002200045002000020000321011611139791400000610200002000040100140052140052140048140052140052
8020414005110490000000200011400208477512968725901004010030003200003010030000200001204383766920681218233711400231400511400511295053129934801003020020066300006020020000500001400541400361150201100991004010010000100000100200000220000000200002200032101161113978740000660200002000040100140048140048140099140036140048
80204140047104900000003300001400218477512969025901034010030003200003010030000200001204283266920681218233711400231400891400401295053129934801003020020000300006020020000500001400351400471150201100991004010010000100000100200000220000000200002000032101161113978740000660200002000040100140048140036140036140048140048
80204140088104900011002000114003680130129670259010340100300032000030100300002000012042832669206812181242114002314004714004712950531299348010030200200003000060200200005000014003514004711502011009910040100100001000001002000002200020002000020000321011611139775400006010200002000040100140048140053140052140052140052
8020414005110490001100600101400368477512968225901034010030003200003010030000200001204418566912901218233711400231400471400471295053129934801003020020000300006020020000500001400511400471150201100991004010010000100000100200000220000000200000200032101161113979140000666200002000040100140052140052140052140052140036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0057

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f191e1f223a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80025140035104900001020101400208477512967025900134001030000200003001030000200001204373566920681218287314001114005114005112957931300248001030020200003000060020200005000014005114005111500211091040010100001000001020004322000200122000022220031404167713979740000101010200002000040010140058140058140042140058140058
80024140057104911110040011400428478112969225900164001030006200003001030000200001204425766915881218340714003314005714004112960131300308001030116200003000060020200005000014005714005711500211091040010100001000001020003422000300122000022222031407163413979740000101010200002000040010140058140058140058140058140058
800241400571049111000370101400268478112969225900164001030006200043001030000200001204425766915881218340714003414005714005712960131300148001030020200003000060020200005000014005714005711500211091040010100001000001020004322000200022000022220031406166713978140000101010200002000040010140058140058140058140058140058
80024140057104911100040011400428478112969225900134001030006200003001030000200001204286266923561218340714003314005714005712960131300308001030020200003000060020200005000014005714005711500211091040010100001000001020002422000200122000022221031404164313979740000101010200002000040010140058140058140058140058140058
80024140057104911100020111400428478112967625900164001030003200003001030000200001204425766915881218340714003314005714005712960131300308001030020200003000060020200005000014005714005711500211091040010100001000001020003322000300222000022221031404644313994740000101010200002000040010140058140042140058140058140058
800241400581049110000470111400428013812969225900164001030006200003001030000200001204425766923561218340714003314004114005712960131300308001030020200003000060020200005000014005714005711500211091040010100001000001020003322000300022000022221031403163413980040000101010200002000040010140058140142140058140058140131
8002414015510851000102013142256959891306955389042240242301262003432716327002155012145633675672012310577142298142882142766130104236131608857643281021848313026560221984534101420491410292815002110910400101000010000110200715220059110683102006622226031404164313979740000101010200002000040010140144140058140058140042144536
8002414321611151200005010140387847811307264990016400103000620004325343270021450121528376742846121839131400331401541403401299351101305928231031045214883102364112215505170514223014106424150021109104001010000100000102001822200530132535020040222230342661281091409894012910100200002000040010141496141491141585141510141012
800241421561054100001449242241314530899252131665126490562404103020620102346023468022550122401956813516123536911431531438401440061309173661322478921433309221703325566718213645542514358714318737150021109104001010000100000102000432200040022200002222103140316471397974000010010200002000040010140042140043140042140058140058
80024140057104910100022011140042847811296922590016400103000620000300103000020000120442576692356121834071400331400571400581296013130030800103029920124300006002020000500001400571400581150021109104001010000100000102000322200020002200002222003140423341397814000001010200002000040010140058140058140061140042140058

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.4s, v1.4s }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0047

retire uop (01)cycle (02)030e0f1e22233a3f43494d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80205140102105000610014003220847791296832590103401003000320000301003000020000120438376692068121823371400231400471400471295013129926801003020020000300006020020000500001400431400431150201100991004010010000100000100200002200001002000020000032102321113978740000666200002000040100140048140048140048140048140056
80204140047104900200114003200818751296822590119401003000320000301003000020000120438376691876121828531400231400471400471295013129938801003020020000300006020020000500001400471400471150201100991004010010000100000100200002200000002000020200032101161113978740000666200002000040100140048140048140048140044140048
80204140047104900600014003220847711296822590103401003000320000301003000020000120438376692260121823371400231400471400471295013129930801003020020000300006020020000500001400471400471150201100991004010010000100000100200000200000022000200000032101161113978740000666200002000040100140044140048140044140048140048
80204140047104800210014004400847871296822590103401003000320000301003000020000120434866694276121828531400321400961400471295013129930801003020020000300006020020000500001400471400431150201100991004010010000100000100200002200020002000020200032101161113978740000606200002000040100140048140048140048140048140048
80204140043104900210014002800847711296822590103401003000320000301003000020000120438376691876121823371400231400471400471295013129930801003020020000300006020020000500001400471400471150201100991004010010000100000100200002200003032000020200032101161113978740000666200002000040100140134140048140051140048140048
80204140047104800200014004000847711296822590103401003000320000301003000020000120438376691684121819781400231400431400471295093129926801003020020000300006020020000500001400431400471150201100991004010010000100000100200002200020002000000200032101161113978340000666200002000040100140048140048140048140048140044
80204140047104801610114003200818751296902590103401003000320000301003000020000120438376691876121823371400231400471400471295013129930801003020020000300006020020000500001400471400431150201100991004010010000100000100200002200000002000000200032101161113983940000666200002000040100140048140048140048140048140048
80204140047104911200114003200818751296822590103401003000320000301003000020000120438376691684121819781400231400471400471295013129930801003020020000300006020020066500001400471400441150201100991004010010000100000100200002200000002000020200032101161113978740000666200002000040100140048140048140048140048140048
80204140047104901200014002800818751296822590103401003000320000301003000020000120438376691876121823371400231400471400471295013129930801003020020000300006020020000500001400471400471150201100991004010010000100000100200002200000022000020200032101161113978740000666200002000040100140048140048140048140044140056
80204140047104900200014003200847711296822590103401003000320000301003000020000120438376691684121823371400191400471400471295013129931801003020020000300006020020000500001400471400471150201100991004010010000100000100200004200000002000000200132101161113978740000066200002000040100140048140048140048140048140048

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0057

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f191e1f22233a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80025140109104911100040100140046847811296762590016400103000320000300103000020000120442576691588121834070140017014005714005712960131300308001030020200003000060020200005000014005714005711500211091040010100001000001020004202000300141920000222213140516671397814000001010200002000040010140058140058140042140058140058
80024140095104911111040101140042847811296922590016400103000620002300103000020000120442576694180121835791140033014005714005712960131300308001030020200003000060020200005000014004114005711500211091040010100001000001020003322000200127220000222203140416431397974000001010200002000040010140058140062140058140058140058
80024140081104910100020100140026847811296922590016400103000320000300103000020000120442576692356121834071140033014005714005712962831300158001030020200003000060020200005000014005714005711500211091040010100001000001020002222000200026320000222203140716431397974000001010200002000040010140058140058140058140042140042
8002414006010501100004000014004284785129692259001640010300062000030010300002000012044257669235612183407014003501400411400571296013130030800103002020000300006002020000500001400411400571150021109104001010000100000102000322200040323220000222223140423341398024002410010200002000040010140058140042140475140145140058
800241400691049100100401011400428661012969274900164001030014200003001030180200001204286267092081220934411400340140041140057129601313003080010300202000030000600202000050000140057140057115002110910400101000010000010200033220002001233200002222031404164313979740000101010200002000040010140062140058140058140058140042
800241400411049111000800011400468478112969225900164001030006200003001030000200001204286266923561218197411400170140057140057129601313001480010300202000030000600202000050000140041140057115002110910400101000010000010200022220002001350200002222031406166713979740000101010200002000040010140058140058140058140058140062
80024140057104911100020101140042801381296762590013400103000620000300103000020000120445096692356121834071140033014010114006712960131300308001030020200003000060020200005000014005714005711500211091040010100001000001020003302000200017020000220223140716441397974000001010200002000040010140058140058140042140058140058
80024140058104911110040101140042801381296764690016400103000620000300103000020000120446056692644121836650140033014005714004112960131300308001030020200003000060020200005000014005714009211500211091040010100001000001020003422000300022000022220314041643139797400001000200002000040010140058140058140058140058140058
800241400601049101000201011400428478112969225900164001030006200003001030000200001204425766929821218532801400170140041140123129601313001480010301162000030000600202000050000140057140057115002110910400101000010000010200043020003000220000220213140816761397974000510100200002000040010140058140102140042140107140098
800241400571049110100201011400428478212969225900134001030006200003001030000200001204425766923561218340701400330140057140057129585313003080010300202000030000600202000050000140057140057115002110910400101000010000010200033220002000520000022213167616761398014000010010200002000040010140042140058140058140058140061

Test 4: throughput

Count: 8

Code:

  ld2 { v0.4s, v1.4s }, [x6]
  ld2 { v0.4s, v1.4s }, [x6]
  ld2 { v0.4s, v1.4s }, [x6]
  ld2 { v0.4s, v1.4s }, [x6]
  ld2 { v0.4s, v1.4s }, [x6]
  ld2 { v0.4s, v1.4s }, [x6]
  ld2 { v0.4s, v1.4s }, [x6]
  ld2 { v0.4s, v1.4s }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f22233a3f4346494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0e7eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
320205800565990010100038010080026250325320152100160054160000100160000160000500800042192255818002208004180041032332010020016000016009220016000032000080041800411180201100991001008000080000110016001413431600510291511600006151012100510911711800380131301600001600001008004280042800428004280042
320204800416001000000013010280026255325320154100160056160000100160000160000500801372192254008002208004180041032332010020016000016000020016000032000080041800411180201100991001008000080000010016001513431600510115216003901514313200510911711800380131321600001600001008004280042800428004280042
320204800415991101000413000280026055325320154100160056160000100160000160000500801386192254018002208004180041032332010020016000016000020016000032000080041800411180201100991001008000080000010016001213431600530001516003961124313100510913511800380131321600001600001008004280042800428004280042
320204800416001001000028000080026255325320156100160056160000100160304160000500800048192252818002208004180041032332010020016000016000020016000032000080041803861180201100991001008000080000010016001314431600520015516000001514313100515711711800380131321600001600001008004280042800428004280042
320204800416001102000058010080026255325320154100160056160000100160000160000500800042192254008002208004180041032332010020016030416000020016000032000080041800411180201100991001008000080000010016001412431600530115616003961524313001510911711800380131321600001600001008004280042800428004280042
32020480041600120101005701028002625032532011410016005616000010016000016000050080138619225401800220800418004103233201002001600001600002001600003200008004180041118020110099100100800008000001001600131243160055040521600400152012200510911711800380131321600001600001008004280042800428004280042
32020480041600110100005801028002605532532015410016005416000010016000016000050080138019225400800220800418004103233201002001600001600002001600003200008004180041118020110099100100800008000001001600141243160053011521600396113431210051091171180038001321600001600001008004280042800428004280042
320204800416001100000012010280026255325320156100160056160000100160000160000500801386192255618002208004180041032332010020016000016000020016000032000080041800411180201100991001008000080000010016001412431600520117216000061514313100510911711800380131321600001600001008004280042800428004280042
320204800415991001110458010280026050325320154100160054160000100160000160000500801380192254018002208004180041032332010020016000016000020016000032000080041800411180201100991001008000080000010016001514431600530115216000061524313200510911711800380131321600001600001008004280042800428004280042
3202048004159911010000570102800262551072532015410016005416000010016000016000050080004219225680800220800418004103233201002001600001600002001600003200008004180041118020110099100100800008000001001600141243160052000541600396151431300051091171180038001321600001600001008004280042800428004280042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss data (0b)0e0f18191e1f2223243a3f4346494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)a5ld unit uop (a6)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)c2cfd5map dispatch bubble (d6)dbddfetch restart (de)e0e7eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
32002580055600001100380100080026200025320048101600381600001016000016000050800377192066408002280041800410323320010201600001600002016000032000080041800411180021109101080000800000101600000270160032003216002461035050197170428003811060160000160000108004280042800428004280042
32002480041599000000001000800262000253200481016003816000010160000160000508004041920760080097800418004103233200102016000016000020160000320000800418004111800211091010800008000001016000000016003200321600326124270501941703380038110100160000160000108004280042800428004280042
3200248004159900000038000008002621212025320048101600301600001016000016000050800000192105218002280041800410323320010201600001600002016000032000080041800411180021109101080000800000101600000001600000032160032613235050192170348003810100160000160000108004280042800428004280042
320024800416000000003001000800260120025320048101600381600001016000016000050800378192065618002280041800410323320010201600001600002016000032000080041800411180021109101080000800000101600000270160032003216003260243525019217035800381060160000160000108004280042800428004280042
3200248004159900000038000008002601212025320048101600381600001016000016000050800377192000018002280041800410323320010201600001600002016000032000080041800411180021109101080000800000101600000270160032000160032600005019417042800381060160000160000108004280042800428004280042
32002480041600000000000000800262012025320042101600321600001016000016000050800219192067018002280041800410323320010201600001600002016000032000080041800411180021109101080000800000101600000270160000003516003261243505019217024800381060160000160000108004280042800428004280042
320024800416000000000000018002621212025320010101600301600001016000016000050800377192065218002280041800410323320010201600001600002016000032000080041800411180021109101080000800000101600000270160032000160032613227050194170428003811060160000160000108004280042800428004280042
3200248004160000000000100080026212120253200481016000016000010160000160000508003781920006180022800418004103233200102016000016000020160000320000800418004111800211091010800008000001016000002701600320027160024012435050192170428003801040160000160000108004280042800428004280042
320024800415990000003800001800262180025320048101600381600001016000016000050800000192109418002280041800410323320010201600001600002016000032000080041800411180021109101080000800000101600000270160042103216003261323505019417024800381060160000160000108004280042800428004280042
320024800415990010003000000800262121202532004810160038160000101600001600005080037619206701800228004180041032332001020160000160000201600003200008004180041118002110910108000080000010160000027016003200321600000132005019417024800380060160000160000108004280042800428004280042