Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2 (multiple, 8H)

Test 1: uops

Code:

  ld2 { v0.8h, v1.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.004

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.004

retire uop (01)cycle (02)03l1i tlb fill (04)09l2 tlb miss data (0b)0e0f18191e1f22243a3f43464951schedule uop (52)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd load (98)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)acafb5bbl1d cache miss ld nonspec (bf)cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaebec? ldst retires (ed)? simd retires (ee)f5f6f7f8fd
6400529351220910000018901047862884420017069400620042000200020001000023925210228282911729369310400020002000200040002919129247116100110001000120000620000020000001285892346877308127120256307938128535228385165181350314871200020002929029310292932932329320
6400429334219800000048010488328803000170364004200020002000200010000239013002284429168293303104000200020002000400029122291411161001100010000200006200000200040612965911268303111350203333121381410545228366164811349715055200020002922029317292192926529293
64004292452193000000247010462728844002171234004200420002000200010000238903002282229058293083104000200020002000400029146292101161001100010000200004200000200040412933932668843107151202373061380913626028485165361317914984200020002931029277292132924729238
640042929921950000003801047262875800017106400420062000200020001000023806100228422914829261310400020002000200040002936829146116100110001000020000420001020000041288990346901327014920308309838137444528450157411330914977200020002926829326293042930929206
6400429306220500000050010463728858000170794006200420002000200010000238152152286029146293283104000200020002000400029099292101161001100010000200004200000200040012862915268893138149203133097381714525628812163871326214825200020002926929340292592924129306
6400429196219300003288000451928748000171104004200020002000200010000238781152285829097293063104000200020002000400029127290991161001100010000200004200000200040412955925969543172256202913040381510545128463163901345114709200020002924029313292292918729269
640042922321940000006000459228825000171404004200420002000200010000238592052282429144292543104000200020002000400029203292011161001100010000200000200000200060412770909668963139146202563124381212525528369163701330114770200020002933129288293022930229298
640042939221950000001800048782877200017039400420042000200020001000023868100228352914329371310400020002000200040002916529160116100110001000020000620000020000041290592356855310824720286310938128485328379163071347015023200020002927229275291662934629213
6400429372220400000046000456628805000170514004200420002000200010000238815102288628975293253104000200020002000400029142291111161001100010000200000200002200040613142924368623047057203193258381514484328416159751342914893200020002931529230292902934729240
640042933421930000004901045722899300017117400420002000200020001000023868205228262923429342310400020002000200040002915029125116100110001000020000620000020000061274592226848309304820240307538148505428307162031330714898200020002918929288292162925629293

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.8h, v1.8h }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0051

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f22233a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)acafb5l1d cache miss ld nonspec (bf)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020514004710490100100200011400328478912968225901034010030003200003010030000200001204418566920681218233711400271400511400511295053129934801003020020000300006020020000500001400511400471150201100991004010010000100000100200002200000020000220321011613139788400001066200002000040100140052140048140052140052140052
802041400351049000000020000140036847751296862590103401003000320000301003000020000120441856691876121826931140027140051140051129501312993080100302002000030000602002000050000140051140035115020110099100401001000010000010020000220000002000020032101161313979640000666200002000040100140052140052140052140048140048
8020414005110490000000200011400328477112968625901034010030003200003010030000200001204383766920681218269311400271400351400521295053129934801003020020000300006020020000500001400511400471150201100991004010010000100000100200002200000020000220321011612139791400006610200002000040100140052140052140036140052140052
8020414005110490000000201011400368477512968625901034010030003200003010030000200001204383766920681218233711400271400511400511295053129918801003020020000300006020020000500001400471400471150201100991004010010000100000100200002200020020000220321011613139815400001000200002000040100140052140048140036140052140056
802041400531049000000000001140032847751296822590103401003000320000301003000020000120441856692068121823371140011140051140051129505271299498010030200200003000060200200005000014004714004711502011009910040100100001000001002000002000200200002203210116121397914000010610200002000040100140036140052140052140052140052
80204140047104900000002000114003684775129682259010340100300032000030100300002000012044605669206812181242114001114004714003512950531299348010030200200003000060200200005000014005114003511502011009910040100100001000001002000022000000200002203210116141397754000010610200002000040100140052140052140052140052140052
802041400471049000000020101140032847711296862590103401003000320000301003000020000120441856691290121826931140027140051140051129505312993480100302002000030000602002000050000140051140048115020110099100401001000010000010020000220000002000022032101161313978740000606200002000040100140052140052140048140052140052
80205140047104900000002000014003284771129682259010340100300032000030100300002000012044185669206812182337114002714003514005112950531299348010030200200003000060200200005000014005114003511502011009910040100100001000001002000022000000200002203210116131397924000010610200002000040100140052140052140052140052140052
80204140047104900000002000114003684775129686259010340100300032000030100300002000012044185669206812182337114002714005114005112950531299348010030200200003000060200200005000014005114004711502011009910040100100001000001002000022000000200002203210116141397874000010610200002000040100140052140052140036140052140052
80204140035104900011002000114003684775129686259010340100300032000030100300002000012043837669206812182337014001114005114003512950631299368010030200200003000060200200005000014005114004711502011009910040100100001000001002000022000003200002223906122547141868401840010200002000040100142214142471142397141843142354

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0051

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)0e0f1e22233a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)daddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002514005310490000210014003684775129670259001340010300032000030010300002000012043387669129012182517114001101400551400511295953130012800103002020000300006002020000500001400351400471150021109104001010000100000102000002200000000200002020000314031603313978740000606200002000040010140036140052140048140048140048
800241400511048000001001400228477912968625900134001030000200003001030000200001204373566922601218142211400110140047140047129591313000880010300202000030000600202000050000140051140035115002110910400101000010000010200000020002000020000202000031403160331397954000010610200002000040010140052140036140052140131140036
80024140051104900002000140033801301296822590013400103000320000300103000020000120437356692356121830511140011014005114003512957931300088001030020200003000060020200005000014005114004711500211091040010100001000001020000002000000002000000000003140316033139792400006610200002000040010140053140048140052140052140052
800241400511049000020001400208477712967625900164001030006200003001030000200001204425766923561218305101400370140041140057129601313003080010300202000030000600202000050000140035140047115002110910400101000010000010200000020004000020000202001131403160331397754000010010200002000040010140052140048140052140052140048
800241400511049000021001400328477512968225900134001030003200003001030000200001204232266912901218251711400230140051140035129595313002480010300202000030000600202000050000140035140047115002110910400101000010000010200000220000000020000202000031403160331397874000010100200002000040010140052140036140048140052140036
80024140047104900000001140020847751296822590013400103000320000300103000020000120437356691290121825171140027014005114005112959531300248001030020200003000060020200005000014005114004711500211091040010100001000001020000022000000002000020200003140316034139787400006106200002000040010140048140052140052140052140037
800241400471049000041011400368477112968625900264001030000200003001030000200001204373566920681218251711400270140051140051129595313002480010300202000030000600202000050000140057140053115002110910400101000010000010200022220002001020000202000031403160431397914000001010200002000040010140048140049140052140036140058
8002414005710490000800214003884775129670259001340010300032000030010300002000012043735669129012182517114002701400531400351295913130024800103002020000300006002020000500001400511400481150021109104001010000100000102000000200020102200002000000314031603313979140000101010200002000040010140048140036140052140052140052
80024140047104900002001140036847751296862590013400103000320000300103000020000120433486693460121818521140027014005114005112957931300088001030020200003000060020200005000014004714004711500211091040010100001000001020000022000000032000000200003140316033139775400006010200002000040010140052140052140048140052140059
80024140051104900102001140023847751296702590013400103000320000300103000020000120437356691290121825170140027014005114005112959131300268001030020200003000060020200005000014005114004711500211091040010100001000001020003222000300002000020200003140316034139775400001060200002000040010140036140052140052140052140048

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.8h, v1.8h }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0065

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f181e22233a3f43494d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802051400651049111111000600114005022847891297002590109401003000920000301003000020000120454036692740121839391140041014004914006512951931299428010030200200003000060200200005000014006514006511502011009910040100100001000011002000334200060242000224220032126167713980540000101010200002000040100140066140066140066140066140066
802041400651049110111000600114005022847891297002590109401003000920000301003000020000120483706692884121839391140041014007014006512951931299488010030200200003000060200200005000014006514006511502011009910040100100001000001002000324200040242000224221032127167713980540000101010200002000040100140066140066140066140050140066
802041400571049111010000610114005022847891297002590109401003000920000301003000020000120454036692740121839391140041014006514006512951931299488010030200200003000060200200005000014006514006511502011009910040100100001000001002000454200050142000224222032127167713980540000101010200002000040100140066140050140066140066140066
8020414004910491111100006102140050228478912970025901094010030009200003010030000200001204540366927401218393911400410140065140066129921121303658125230200201863055860386200005000014006514040581502011009910040100100001000001002000334200040042000224221032125167613980540008101010200002000040100140066140066140050140066140066
802041400651049111111000410114005022847891297002590109401003000920000301003000020000120454036692740121840281140041014004914006512951931299488010030200200003000060200200005000014006514006511502011009910040100100001000001002000224200060142000224222032128166713980540000101010200002000040100140066140066140066140066140066
80204140065104911111111061011400502284789129700259010940100300092000030100300002000012045403669274012183939114004101400651400651295193129948801003020020000300006020020000500001400681400651150201100991004010010000100000100200052420005014200022422103212716771398054000001010200002000040100140066140066140066140058140066
8020414006510501111110006101140050228478912970025901094010030009200003010030000200001204540366927401218393911400250140065140065129519211299488010030200200003000060200200005000014006514006511502011009910040100100001000001002000224200050042000224222032126167513980540000101010200002000040100140066140066140066140066140050
802041400651049110111000600114005022847891297012590109401003000920000301003000020000120454036692740121839391140043014006514006512951931299488010030200200003000060200200005000014006514006511502011009910040100100001000001002000324200050142000224220032127167713980540000101010200002000040100140066140069140066140066140050
802041400651049111010000610114005022847901297002590109401003000920000301003000020000120454036692740121839391140041314006714006512951931299488010030200200003000060200200005000014006514006511502011009910040100100001000001002000334200050142000224220032127167713980540000101010200002000040100140066140066140066140069140066
80204140108104911011000064810114005022847891296842590123401003000920000301003000020000120454036692740121839391140041014006514006512951931299498010030200200003000060200200005000014006514006511502011009910040100100001000011002000234200040142000224220032127177713978940005101010200002000040100140072140066140066140066140066

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0051

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f18191e2223243a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
800251400471049000000021000142127847711299194659022540268301352005232892327902135012172131676734412296385142448014284314310313056224013183686450330952210832790661602204655270143119142809341500211091040010100001000011020060002000010002000020200003851113457514309640345666200002000040010143880144461143779144640143986
800241424671049000002830160410011400329643913082483690474402583013520066328943261020000120423226691972121825171400330140051140051129595313004380010300202000030000602062000050000140051140051215002110910400101000010000010200000220000000320000200000031403164513979140000101010200002000040010140052140055140054140052140052
800241400511049000000060100140020847751296702590013400103000320000300103000020000120437356692068121828731400270140035140051129595313006480010300202000030000600202000050000140051140051115002110910400101000010000010200000220000000251320000202000031403162413979140000101010200002000040010140052140052140053140036140052
80024140051104900000002010014003684775129686259001340010300002000030010300002000012043735669206812182873140027014005114003512957931300738001030020200003000060020200005000014005114005111500211091040010100001000001020000022000000002000020200003140316451397754000010100200002000040010140052140052140036140052140052
8002414005110490000000830000140036847751296862590013400103000320000300103000020000120437356692068121828731400270140051140051129595313006880010300202000030000600202000050000140052140051115002110910400101000010000010200000220000000020000202020131404164413979140000101010200002000040010140052140052140052140036140052
80024140035104900000000000014003684775129686259001040010300002000030010300002000012043735669129012182873140011014005114003512959531300538001030020200003000060020200005000014005114005111500211091040010100001000001020000002000000062000020200003140316441397914000010100200002000040010140036140052140052140052140052
80024140035104900000002010014003684775129686259001040010300062000230010300002000012043735669206812182873140027014003514005112959531300168001030020200003000060020200005000014007914005111500211091040010100001000011020000022000000002000000200003140416441397974000010010200002000040010140052140136140063140061140052
800241400571049100000060100140036801301296862590013400103000020000300103000020000120442576692356121844871400110140057140057129595313003480010300202000030000600202000050000140035140051115002110910400101000010000010200034220000000020000002000031403163413979140000101010200002000040010140052140052140052140052140052
80024140051104900000002010014003684775129686259001340010300062000030100300002000012043735669206812182873140027014005114005212959531300438001030020200003000060020200625000014005714005111500211091040010100001000001020000002000000002000020200003140316441397914000010010200002000040010140052140052140052140052140052
8002414005110490000000209000014003684775129670259001340010300032000030010300002000012043735669129012182873140027014005114005112959531300328001030020200003000060020200005000014005714013411500211091040010100001000011020000002000000002000000000003140323441397914000010010200002000040010140137140036140036140036140052

Test 4: throughput

Count: 8

Code:

  ld2 { v0.8h, v1.8h }, [x6]
  ld2 { v0.8h, v1.8h }, [x6]
  ld2 { v0.8h, v1.8h }, [x6]
  ld2 { v0.8h, v1.8h }, [x6]
  ld2 { v0.8h, v1.8h }, [x6]
  ld2 { v0.8h, v1.8h }, [x6]
  ld2 { v0.8h, v1.8h }, [x6]
  ld2 { v0.8h, v1.8h }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f181e22233a3f43464951schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0e7eaeb? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
32020580068599000000016200280026016162532011410016005216000010016000016000050080004819219488002280041800410323320100200160000160000200160000320000800418004111802011009910010080000800000100160014154216005101511600386151421315109011711800380091600001600001008004280042800428004280042
320204800415991111110951018002601202532013810016000016000010016000016000050080000019210828002280041800410323320100200160000160000200160000320000800418004111802011009910010080000800000100160000001600320032160000012435005109011711800381661600001600001008004280042800428004280042
3202048004159900000009810180026200253201001001600381600001001600001600005008003761920670800228004180041032332010020016000016000020016000032000080041800411180201100991001008000080000010016000003516000000016003261240005130111711800381061600001600001008004280042800428004280042
3202048004159900000001280018002611202532013810016000016000010016000016000050080000019206568002280041801060323320100200160000160000200160000320000800418004111802011009910010080000800001100160000001600320001600326100005109011711800380001600001600001008004280042800428004280042
32020480041600000000038001800260121225320138100160000160000100160000160000500800377192065680022800418004103233201002001600761600002001600923200008004180041118020110099100100800008000001001600000271600321027160024002435005109011711800380661600001600001008004280042800428004280042
3202048004160000000009010180026212122532013810016003016000010016009016000050080037719200008002280041800411132332010020016000016000020016000032000080041800411180201100991001008000080000010016000002716003210241600006032270051090217118003811061600001600001008004280042800428004280042
320204800415990000000561018009221212253201301001600381600001001600001600005008003771921076800228004180041032332010020016000016000020016000032000080041800411180201100991001008000080000010016000002716003200421600320124350051090117118003811061600001600001008004280042800428004280042
320204800416000000000381008002621212253201381001600381600001001600001600005008000001920000800228004180041032332010020016000016000020016000032000080041800411180201100991001008000080000010016000002716000000321600326024000510901171180038010101600001600001008004280042800428004280042
320204800416000000000010080026212122532010010016003816000010016000016000050080000019206648002280041800410323320100200160000160000200160000320000800418004111802011009910010080000800001100160000001600320024160032602400051090117118003801001600001600001008004280042800428004280042
320204800416000000000980018002621212253201381001600001600001001600001600005008000001920000800228004180041032332010020016000016000020016000032000080041800411180201100991001008000080000010016000002716002400321600246024350051090117118003811061600001600001008004280042800428004280042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2223243a3f4346494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)a5ld unit uop (a6)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)c2branch cond mispred nonspec (c5)cdcfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0e7eaeb? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
320025800556001000100030010008002621212025320042101600321600001016000016000050800219192065610800228038680041032332001020160000160000201600003200008004180041118002110910108000080000110160000027016000000241600246124270005019533174480038166160000160000108004280042800428004280042
320024800416000000100030000008002621212025320040101600321600001016000016000050800000192000015800228004180041032332001020160000160000201600003200008004180041118002110910108000080000010160000027016002400271600246124420015019534174380038160160000160000108004280042800428004280042
32002480041600000000003001000800262121202532001010160030160000101600001600005080021919206701580022800418004103233200102016000016000020160000320000800418004111800211091010800008000001016000002701600000001600326124420005019535173480038006160000160000108004280042800428004280042
32002480041599000000003001001800262120025320010101600001600001016000016000050800222192105215800228004180041032332001020160000160000201600003200008004180041118002110910108000080000010160000027016002400241600246124420005019535173580038166160000160000108004280042800428004280042
32002480041599000000000010008002620120253200481016000016000010160000160000508003741920000158002280041800410323320010201600001600002016000032000080106800411180021109101080000800000101600000270160024002416002461000005019545175380038166160000160000108004280042800428004280042
32002480041599000011003800000800262121202532004210160038160000101600901600005080022219200001580022800418004103233200102016000016000020160000320000800418004111800211091010800008000001016000002701600240024160024612400005019544174480038166160000160000108004280042800428004280042
3200248004159900000000300100080026212002532004010160030160000101600001600005080022219206641580022800418004103233200102016000016000020160000320000800418004111800211091010800008000001016000002701600000024160024010001050195341733800381106160000160000108004280042800428004280042
32002480041600000000003801001800262121202532004010160030160000101600001600005080021919206641580022800418004103233200102016000016000020160000320000800418004111800211091010800008000001016000002701600240024160024612400005019533174480038166160000160000108004280042800428004280042
3200248004160000000000001000800260012025320042101600001600001016000016000050800219192064815800228004180041032332001020160000160000201600003200008004180041118002110910108000080000010160000027016002400241600240124420005019535175580038166160000160000108004280042800428004280042
3200248004159900000000001000800262121202532004010160000160000101600001600005080025419206641580022800418004103233200102016000016000020160000320000800418004111800211091010800008000011016000000016002400241600246124420005019534173480038160160000160000108004280042800428004280042