Firestorm: LD2 (multiple, post-index, 2S) measurements

Code:

  ld2 { v0.2s, v1.2s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.004

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5e	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
63005	28675	222	0	16	0	1	16	0	0	0	0	0	3	0	0	0	0	4957	28286	0	0	16477	4004	1000	2004	1000	1000	2000	1000	5000	5000	23847	0	7	22754	28443	28652	3	10	4000	1000	2000	2000	2000	28418	28595	1	1	61001	1000	1000	1000	0	2	1002	0	0	0	54	1001	2	1	2	0	13208	9809	7005	3285	8	39	20053	3186	3816	16	35	33	28107	1000	15246	12562	13609	1000	2000	1000	28694	28671	28758	28582	28649
63004	28481	222	0	12	0	0	9	0	0	0	0	0	2	0	0	0	0	4643	28559	0	0	16495	4004	1000	2006	1000	1000	2000	1000	5000	5000	23820	0	8	22658	28621	28688	3	10	4000	1000	2000	2000	2000	28462	28396	1	1	61001	1000	1000	1000	1	2	1000	0	1	0	0	1000	0	0	0	0	13280	9579	7007	3255	10	43	20033	3178	3823	9	39	37	28067	1000	15452	12467	13630	1000	2000	1000	28690	28621	28820	28634	28680
63004	28447	221	0	23	0	0	11	0	0	0	0	0	15	0	0	0	0	4792	28302	0	0	16631	4004	1000	2004	1000	1000	2000	1000	5000	5000	23860	0	4	22731	28401	28624	3	10	4000	1000	2000	2000	2000	28642	28556	1	1	61001	1000	1000	1000	0	2	1000	0	3	0	4	1000	0	0	0	0	13380	9680	7079	3161	10	40	19936	3180	3822	9	36	37	28070	1000	15341	12418	13567	1000	2000	1000	28666	28645	28712	28661	28581
63004	28625	221	0	12	0	0	17	0	0	0	0	0	2	0	0	0	0	4811	28284	0	0	16505	4004	1000	2006	1000	1000	2000	1000	5000	5000	23875	0	2	22718	28496	28693	3	10	4000	1001	2000	2000	2000	28519	28564	1	1	61001	1000	1000	1000	0	2	1000	0	1	0	0	1000	0	0	0	0	13126	9649	7031	3193	8	36	19870	3140	3821	12	37	41	28100	1000	15196	12537	13621	1000	2000	1000	28585	28761	28565	28622	28660
63004	28695	222	0	17	0	0	10	0	0	0	0	0	7	0	0	0	0	4769	28325	0	1	16547	4006	1000	2006	1000	1000	2000	1000	5000	5000	23854	0	1	22749	28510	28760	3	10	4000	1000	2000	2000	2000	28588	28582	1	1	61001	1000	1000	1000	0	2	1000	0	5	0	0	1000	2	0	0	0	13110	9544	7065	3181	6	35	19983	3281	3818	7	44	41	28079	1000	14966	12675	13622	1000	2000	1000	28685	28707	28724	28668	28733
63004	28746	223	0	17	0	0	17	0	0	0	0	0	0	0	0	0	0	4864	28373	0	0	16469	4004	1000	2004	1000	1000	2000	1000	5000	5000	23808	0	6	22706	28581	28746	3	10	4000	1000	2000	2000	2000	28483	28527	1	1	61001	1000	1000	1000	0	2	1000	0	1	0	3	1001	0	0	2	0	13413	9475	7009	3181	8	36	19980	3148	3820	15	40	34	28150	1000	15548	12399	13400	1000	2000	1000	28664	28693	28713	28663	28683
63004	28407	222	0	13	0	0	16	0	0	0	0	0	2	0	0	0	0	4854	28381	0	0	16698	4004	1000	2000	1000	1000	2000	1000	5000	5000	23806	0	1	22681	28525	28608	3	10	4000	1000	2000	2000	2000	28459	28604	1	1	61001	1000	1000	1000	0	2	1000	0	1	0	0	1000	2	0	2	0	13489	9652	7010	3221	7	32	20004	3079	3822	16	39	39	28145	1000	15158	12536	13552	1000	2000	1000	28672	28682	28694	28652	28641
63004	28736	221	0	12	0	0	17	0	0	0	0	0	14	0	0	0	0	4797	28358	0	0	16531	4006	1000	2004	1000	1000	2000	1000	5000	5000	23810	0	0	22691	28494	28642	3	10	4000	1000	2000	2000	2000	28591	28548	1	1	61001	1000	1000	1000	0	2	1000	0	1	0	3	1000	2	0	2	0	13201	9566	6979	3137	5	39	20066	3196	3820	13	35	35	28073	1000	15323	12048	13611	1000	2000	1000	28613	28717	28644	28682	28605
63004	28763	222	1	17	0	0	11	0	0	0	0	0	0	0	0	0	0	4945	28261	0	0	16508	4004	1000	2004	1000	1000	2000	1000	5000	5000	23854	0	5	22723	28538	28613	3	10	4000	1000	2000	2000	2000	28569	28614	1	1	61001	1000	1000	1000	0	2	1000	0	3	0	0	1000	0	0	2	0	13279	9592	7016	3184	11	33	19977	3247	3818	10	36	37	28066	1000	15430	12323	13900	1000	2000	1000	28606	28751	28647	28578	28659
63004	28709	220	0	10	0	0	13	0	0	0	0	0	0	0	1	0	0	4890	28277	0	0	16589	4004	1000	2006	1000	1000	2000	1000	5000	5000	23812	0	9	22678	28550	28538	3	10	4000	1000	2000	2000	2000	28478	28445	1	1	61001	1000	1000	1000	0	2	1000	0	2	0	0	1000	2	0	0	0	13369	9641	7096	3243	8	38	19973	3215	3821	11	37	35	28106	1000	15557	12156	13459	1000	2000	1000	28643	28641	28467	28611	28582

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.2s, v1.2s }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140047	1049	0	0	0	0	0	0	13	0	0	140032	139577	25	90103	50100	30004	10000	40100	30000	10000	1236903	5330042	16112739	140026	0	140048	140035	130726	0	3	131156	80100	30200	10000	30000	60200	20080	30000	140047	140047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	1	0	0	10000	1	1	0	0	0	0	3210	1	80	1	1	139722	50000	6	0	9	10000	20000	50100	140036	140036	140036	140051	140048
70204	140050	1086	0	0	1	1	0	0	1	0	1	140035	139552	25	90100	50100	30000	10000	40100	30000	10000	1236921	5330825	16112739	140011	0	140050	140050	130711	0	3	131141	80100	30200	10000	30000	60200	20000	30121	140050	140050	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	3183	10000	1	1	0	0	0	0	3210	1	121	1	1	139717	50000	26	9	9	10000	20000	50100	140036	140150	140051	140036	140048
70204	140050	1086	0	0	0	0	0	0	13	0	0	140035	139552	25	90103	50100	30003	10000	40100	30000	10000	1236903	5331203	16112739	140026	0	140050	140050	130787	0	3	131194	80100	30200	10040	30000	60200	20000	30000	140050	140037	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	1	0	0	10000	0	1	0	0	0	0	3210	2	121	1	1	139721	50000	20	0	0	10000	20000	50100	140051	140051	140051	140053	140036
70204	140135	1086	0	0	0	0	0	0	1	0	0	140035	139577	25	90103	50100	30003	10000	40100	30000	10000	1244786	5330042	16120324	140026	0	140050	140050	130723	0	3	131194	80404	30200	10000	30000	60200	20000	30000	140035	140047	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	0	10000	1	0	0	10000	1	1	0	0	0	0	3210	1	80	1	1	139722	50000	26	9	0	10000	20000	50100	140051	140051	140051	140051	140036
70204	140098	1086	0	0	1	0	1	0	22	0	0	140035	139552	25	90120	50100	30003	10000	40100	30232	10118	1244786	5331203	16114109	140026	0	140050	140150	130729	0	3	131194	80100	30200	10041	30000	60200	20000	30000	140050	140047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	1	4	0	10000	1	1	0	0	0	0	3210	1	80	1	1	139713	50000	26	6	0	10000	20000	50100	140038	140036	140048	140038	140051
70204	140050	1086	0	0	0	1	0	0	1	0	0	140036	139552	25	90103	50100	30003	10000	40100	30000	10000	1244786	5330042	16112739	140011	0	140050	140050	130726	0	3	131138	80100	30200	10000	30000	60200	20082	30000	140050	140050	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	0	3210	1	121	1	1	139722	50000	6	6	9	10000	20000	50100	140048	140051	140051	140037	140051
70204	140047	1085	0	0	0	0	0	0	145	0	0	140035	139552	25	90100	50100	30000	10000	40100	30000	10000	1244786	5330042	16110398	140097	0	140050	140050	130726	0	3	131194	80100	30200	10000	30000	60200	20000	30000	140050	140047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	1	0	0	10000	1	1	0	0	0	0	3210	1	80	1	1	139722	50000	115	6	6	10000	20000	50100	140051	140055	140036	140051	140051
70204	140047	1085	0	0	0	0	0	0	13	0	0	140035	139570	25	90100	50100	30000	10000	40100	30000	10000	1236903	5330746	16112739	140026	0	140147	140050	130726	0	3	131138	80100	30200	10000	30000	60200	20000	30000	140035	140050	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10001	0	0	0	10000	1	1	0	0	0	0	3210	1	80	1	1	139722	50000	26	6	0	10000	20000	50100	140055	140036	140052	140036	140036
70204	140035	1086	0	0	0	0	1	0	0	0	1	140035	139552	52	90103	50100	30003	10000	40100	30000	10000	1244786	5330042	16114691	140029	0	140035	140143	130726	0	3	131150	80100	30200	10041	30000	60200	20000	30000	140050	140035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	0	3210	1	80	1	1	139801	50000	26	6	6	10000	20000	50100	140048	140051	140051	140052	140036
70204	140041	1086	0	0	0	0	0	1	6	0	0	140037	139552	25	90129	50100	30003	10000	40100	30000	10039	1244786	5330042	16112739	140026	0	140050	140140	130723	0	3	131194	80100	30321	10000	30000	60200	20000	30000	140048	140035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	2	0	6455	10002	1	1	0	0	0	0	3302	1	118	1	1	139879	50226	190	6	9	10000	20000	50100	140242	140239	140126	140318	140230

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140047	1125	1	0	1	0	0	0	0	0	0	4	0	0	0	140035	139635	25	90013	50010	30000	10000	40010	30236	10160	1245916	5333285	16114779	1	0	140026	0	140052	140050	130750	3	131355	80010	30020	10000	30000	60020	20000	30000	140050	140047	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	0	204	10000	1	0	0	0	3140	0	0	3	87	3	3	139722	50000	46	6	9	10000	20000	50010	140051	140051	140052	140053	140051
70024	140050	1125	0	0	0	0	0	0	0	0	0	4	0	0	0	140035	139650	25	90013	50010	30003	10000	40010	30000	10000	1245916	5333285	16114896	1	0	140026	0	140051	140047	130749	3	131209	80010	30020	10000	30000	60020	20000	30000	140050	140047	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	0	3140	0	0	4	87	3	3	139722	50000	11	6	9	10000	20000	50010	140051	140051	140048	140051	140081
70024	140050	1125	0	0	0	0	0	0	0	0	0	1	0	0	0	140035	139650	25	90013	50010	30003	10000	40010	30000	10000	1245907	5333285	16115121	0	0	140028	0	140050	140050	130750	3	131209	80010	30020	10000	30000	60020	20000	30000	140050	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	3	10000	1	0	0	0	3140	0	0	4	87	4	3	139722	50000	6	9	9	10000	20000	50010	140052	140051	140051	140051	140051
70024	140050	1125	0	0	0	0	0	0	0	0	0	43	0	0	0	140035	139651	25	90013	50010	30003	10000	40010	30000	10000	1245847	5333285	16115176	1	0	140027	0	140053	140051	130749	3	131209	80010	30020	10000	30000	60020	20000	30000	140050	140047	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	0	0	10000	0	1	0	0	3140	0	0	3	87	3	3	139722	50000	6	0	9	10000	20000	50010	140048	140051	140051	140051	140048
70024	140050	1124	0	0	0	0	0	0	0	0	0	0	0	0	0	140035	139647	25	90013	50010	30003	10000	40010	30000	10000	1245907	5333285	16114779	1	0	140024	0	140047	140050	130749	3	131209	80010	30020	10000	30000	60020	20000	30000	140050	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	3	10000	1	1	0	0	3140	0	0	3	87	3	4	139733	50000	6	9	9	10000	20000	50010	140037	140051	140052	140052	140036
70024	140050	1125	0	0	0	0	0	0	0	0	0	4	0	0	0	140035	139650	25	90013	50010	30003	10000	40151	30000	10000	1245907	5333285	16114779	0	0	140026	0	140050	140050	130749	3	131194	80010	30020	10000	30000	60020	20000	30000	140050	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	0	3140	0	0	4	87	3	3	139722	50000	6	6	0	10000	20000	50010	140098	140036	140036	140036	140051
70024	140050	1125	0	0	0	0	0	0	0	0	0	1	0	1	0	140032	139650	25	90013	50010	30003	10000	40010	30000	10000	1245907	5332706	16114779	0	0	140034	0	140050	140050	130749	3	131209	80010	30020	10000	30000	60020	20000	30000	140050	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	0	3140	0	0	4	87	4	3	139724	50000	7	9	6	10000	20000	50010	140052	140051	140051	140048	140051
70024	140050	1125	0	0	0	0	0	1	0	0	0	4	0	0	0	140035	139647	25	90013	50010	30003	10000	40010	30000	10000	1245907	5333285	16115009	0	0	140029	0	140050	140050	130749	3	131209	80010	30020	10000	30000	60020	20000	30000	140050	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	24	10000	0	1	0	0	3140	0	0	3	87	3	3	139722	50000	9	10	9	10000	20000	50010	140146	140051	140139	140051	140051
70024	140141	1124	0	0	0	0	0	0	0	0	1	1	0	0	0	140129	139641	25	90025	50010	30007	10000	40010	30000	10048	1248080	5334739	16119914	1	0	140105	0	140050	140144	130777	15	131214	80010	30143	10000	30121	60020	20080	30000	140047	140215	2	1	50021	10	9	10	40010	10000	10000	0	10	10003	0	1	10000	0	0	0	3185	10002	1	1	0	0	3163	0	0	3	104	4	3	139722	50000	10	0	9	10000	20000	50010	140051	140144	140051	140141	140141
70024	140125	1126	0	0	1	0	1	0	0	0	1	265	0	0	0	140042	139599	25	90044	50020	30003	10004	40010	30236	10040	1248334	5333285	16114779	0	0	140175	0	140050	140235	130782	29	131206	80010	30140	10040	30238	60020	20080	30245	140047	140239	26	1	50021	10	9	10	40010	10000	10000	0	10	10004	2	1	10002	0	0	2	12810	10003	1	1	0	2	3210	0	0	3	110	3	6	140013	50020	9	9	11	10000	20000	50010	140222	140330	140242	140237	140316

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.2s, v1.2s }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0075

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch call (8e)	inst branch taken (90)	inst branch indir (93)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140057	1050	1	0	0	0	1	0	0	2	0	0	0	140060	139630	53	90106	50100	30006	10000	40100	30000	10000	1237160	5332259	16116480	1	140034	140075	140075	130751	3	131178	80100	30200	10000	30000	60200	20000	30141	140058	140068	1	1	50201	100	0	99	0	100	40100	10000	10000	1	100	10001	3	0	10001	0	7	0	1	10000	0	1	0	1	0	3210	1	121	1	1	139745	50000	10	6	9	10000	20000	50100	140076	140058	140076	140076	140076
70204	140075	1085	1	0	1	0	1	0	0	14	0	0	0	140060	139619	25	90106	50129	30013	10000	40100	30000	10000	1237232	5332259	16117505	1	140034	140075	140075	130714	3	131178	80100	30200	10000	30121	60200	20000	30000	140057	140068	1	1	50201	100	0	99	0	100	40100	10000	10000	1	100	10003	1	0	10002	0	1	0	3285	10000	1	1	1	1	1	3241	2	121	1	1	139738	50000	9	0	0	10000	20000	50100	140058	140058	140076	140076	140076
70204	140057	1086	1	0	1	0	0	0	0	11	0	1	1	140042	139617	25	90106	50100	30006	10000	40243	30000	10000	1237178	5332259	16117309	1	140051	140075	140075	130751	3	131178	80100	30200	10000	30000	60200	20000	30124	140075	140068	1	1	50201	100	0	99	0	100	40100	10000	10000	1	100	10002	1	1	10003	0	0	0	3231	10000	1	1	1	1	0	3210	1	121	1	1	139729	50000	9	9	9	10000	20000	50100	140076	140076	140077	140122	140058
70204	140075	1086	1	1	0	0	0	0	0	1	0	0	0	140060	139620	25	90106	50100	30006	10000	40100	30000	10000	1237178	5332062	16117309	0	140052	140075	140075	130751	3	131180	80100	30200	10000	30000	60200	20000	30000	140057	140075	2	1	50201	100	0	99	0	100	40100	10000	10000	1	100	10001	1	0	10001	0	0	0	1	10001	1	1	1	1	2	3210	2	80	2	1	139729	50000	9	6	9	10000	20000	50100	140076	140175	140122	140092	140078
70204	140075	1086	1	1	1	0	0	0	0	2	0	1	0	140062	139617	25	90106	50100	30006	10000	40100	30000	10000	1237178	5332979	16117440	0	140122	140080	140075	130751	3	131201	80100	30200	10000	30000	60200	20000	30142	140116	140078	1	1	50201	100	0	99	0	100	40100	10000	10000	1	100	10001	1	1	10002	0	0	1	1	10000	1	1	1	1	1	3210	1	121	1	1	139745	50000	9	9	9	10000	20000	50100	140058	140160	140069	140059	140076
70204	140075	1085	1	0	0	0	0	0	0	2	0	0	0	140060	139611	25	90103	50100	30003	10000	40100	30000	10000	1239213	5332297	16117309	0	140051	140076	140124	130751	34	131268	80100	30200	10000	30000	60200	20000	30000	140057	140070	2	1	50201	100	0	99	0	100	40100	10000	10000	1	100	10002	1	1	10002	0	1	2	4	10000	1	1	0	1	0	3210	1	121	1	1	139745	50000	0	9	9	10000	20000	50100	142768	144093	143558	140757	140076
70204	140078	1085	1	2	0	0	0	0	0	2	0	0	0	140109	139630	25	90103	50100	30006	10000	40100	30000	10000	1239968	5332376	16116480	0	140044	140075	140075	130751	3	131178	80100	30200	10000	30000	60200	20000	30000	140075	140068	1	1	50201	100	0	99	0	100	40100	10000	10000	1	100	10002	1	1	10002	0	2	1	7	10000	0	1	1	1	0	3210	1	121	1	1	139745	50000	9	6	9	10000	20000	50100	140076	140079	140076	140076	140167
70204	140075	1086	1	1	1	0	0	0	0	13	0	1	0	140042	139630	25	90121	50100	30006	10000	40100	30000	10000	1237108	5332259	16116480	1	140033	140075	140075	130751	3	131178	80100	30200	10040	30000	60200	20000	30000	140075	140068	1	1	50201	100	0	99	0	100	40100	10000	10000	0	100	10002	2	1	10001	0	0	1	1	10000	1	1	0	1	1	3210	1	121	1	1	139745	50000	9	7	9	10000	20000	50100	140058	140076	140076	140076	140076
70204	140075	1125	1	0	0	0	0	1	0	1	0	0	0	140062	139617	25	90106	50100	30006	10000	40100	30000	10000	1237178	5332298	16117537	0	140051	140078	140076	130751	3	131178	80100	30200	10000	30000	60200	20000	30000	140075	140076	1	1	50201	100	0	99	0	100	40100	10000	10000	1	100	10002	2	1	10001	0	3	1	22	10000	1	1	1	1	0	3210	1	121	1	1	139745	50000	9	6	10	10000	20000	50100	140077	140076	140058	140076	140076
70204	140075	1125	1	0	1	0	0	0	0	19	0	0	0	140053	139617	25	90106	50100	30006	10000	40100	30000	10000	1237223	5333359	16117544	1	140052	140166	140257	130796	32	131307	80398	33288	11090	30119	60696	20082	30245	140254	140175	2	1	50201	100	0	99	0	100	40100	10000	10000	0	100	10004	1	1	10002	2	2	3	9752	10002	1	1	1	1	0	3256	2	125	2	1	141792	50036	9	6	9	10000	20000	50100	140250	140361	140344	141205	140162

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0052

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140057	1049	0	0	0	0	0	0	0	13	0	0	140037	139652	25	90013	50010	30003	10000	40010	30000	10000	1245925	5333361	16113577	0	140028	0	140052	140052	130751	3	131218	80010	30020	10000	30000	60020	20000	30000	140052	140049	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	13	0	0	10000	1	1	3140	0	3	87	4	3	139724	50000	0	0	6	10000	20000	50010	140054	140053	140053	140053	140053
70024	140036	1085	0	0	0	0	0	0	0	1	0	0	140039	139649	25	90010	50010	30003	10000	40010	30000	10000	1245925	5333361	16115004	1	140028	0	140036	140036	130751	3	131195	80010	30020	10000	30000	60020	20000	30000	140052	140052	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	6	10000	0	1	3140	0	3	87	3	3	139724	50021	9	6	9	10000	20000	50010	140057	140054	140053	140037	140053
70024	140052	1086	0	0	0	0	0	0	0	1	0	0	140039	139589	25	90013	50010	30003	10000	40010	30000	10000	1245925	5332745	16120611	0	140028	0	140036	140052	130751	3	131211	80309	30020	10000	30000	60020	20000	30000	140052	140049	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	3	10000	1	1	3163	0	5	87	4	3	139724	50000	0	9	0	10000	20000	50010	140053	140040	140053	140053	140053
70024	140052	1085	0	0	1	0	0	0	0	12	0	0	140037	139652	25	90013	50010	30007	10000	40010	30000	10000	1245925	5333361	16115004	0	140028	0	140055	140049	130755	3	131211	80010	30020	10000	30000	60266	20000	30000	140052	140052	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	1	0	3	10000	1	1	3140	0	3	87	5	4	139724	50009	6	9	9	10000	20000	50010	140053	140053	140053	140059	140053
70024	140057	1085	0	0	0	0	0	0	0	1	88	0	140037	139652	25	90013	50010	30003	10000	40010	30000	10039	1245925	5333401	16115004	0	140028	0	140052	140052	130751	3	131211	80010	30020	10000	30000	60020	20000	30000	140036	140141	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	0	1	10000	0	0	3	10000	1	1	3140	0	3	87	4	4	139724	50000	0	6	9	10000	20000	50010	140151	140053	140037	140053	140055
70024	140052	1086	0	0	0	1	0	0	0	1	0	0	140021	139652	25	90013	50010	30003	10000	40010	30000	10000	1245934	5335073	16115004	0	140012	0	140052	140052	130751	3	131260	80010	30020	10000	30000	60020	20000	30000	140052	140050	2	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	1	0	0	10000	1	1	3140	0	3	91	4	4	139708	50010	9	6	0	10000	20000	50010	140053	140053	140146	140037	140041
70024	140052	1086	0	1	0	0	1	0	0	13	0	0	140039	139636	25	90030	50010	30003	10000	40010	30000	10000	1245925	5333361	16115004	0	140028	0	140052	140052	130751	3	131211	80010	30020	10000	30119	60020	20000	30000	140052	140052	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	0	10000	1	1	3140	0	3	87	4	3	139724	50000	0	6	9	10000	20000	50010	140053	140037	140053	140037	140053
70024	140053	1085	0	0	0	0	0	0	0	13	0	0	140037	139652	25	90013	50010	30003	10000	40151	30000	10000	1245925	5333361	16115004	0	140028	0	140052	140052	130735	3	131211	80010	30020	10000	30000	60020	20080	30000	140053	140052	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	2	0	3	10000	1	1	3140	0	4	109	4	4	139724	50000	6	6	0	10000	20000	50010	140053	140053	140053	140053	140053
70024	140144	1086	0	0	0	0	0	0	0	133	0	0	140037	139636	25	90013	50010	30003	10000	40010	30120	10000	1245856	5333361	16115004	0	140025	0	140052	140052	130751	3	131211	80010	30020	10000	30000	60020	20000	30122	140052	140049	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	1	0	3260	10000	1	0	3140	0	4	87	3	3	139726	50000	9	6	9	10000	20000	50010	140053	140058	140053	140053	140053
70024	140148	1086	0	0	0	0	0	0	0	0	88	0	140037	139636	25	90013	50010	30003	10000	40010	30118	10000	1245943	5333361	16115004	0	140028	0	140052	140052	130753	3	131211	80010	30020	10000	30000	60020	20000	30000	140052	140145	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	0	10004	0	0	9670	10004	0	1	3210	0	5	96	3	5	139934	50018	9	0	9	10000	20000	50010	140313	140233	140342	140335	140336

Test 4: throughput

Count: 8

Code:

  ld2 { v0.2s, v1.2s }, [x6], x8
  ld2 { v0.2s, v1.2s }, [x6], x8
  ld2 { v0.2s, v1.2s }, [x6], x8
  ld2 { v0.2s, v1.2s }, [x6], x8
  ld2 { v0.2s, v1.2s }, [x6], x8
  ld2 { v0.2s, v1.2s }, [x6], x8
  ld2 { v0.2s, v1.2s }, [x6], x8
  ld2 { v0.2s, v1.2s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5e	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240205	80041	620	2	1	2	0	0	0	1	1	147	88	0	0	0	80026	1	6	6	44	68	320466	80192	160216	80091	80238	160265	80268	4410451	3762093	9834880	0	0	80128	80181	80320	49948	24	57	50080	321157	202	80130	160260	200	160262	160000	80041	80180	2	1	80201	100	99	100	100	80000	80000	0	100	81058	2	14	81059	1	1	4	1169	80096	6	1	10	14	0	5153	1	33	1	2	80144	1	80185	6	6	80000	160000	80100	80183	80042	80182	80324	80182
240204	80181	621	0	1	1	1	0	0	2	1	16	0	0	0	0	80026	1	6	6	0	25	320140	80100	160032	80000	80100	160000	80000	4408215	3758374	9826026	0	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	14	80013	0	0	0	10	80009	6	0	9	18	0	5110	1	16	1	1	80038	1	80000	6	6	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	0	0	1	0	1	1	0	0	19	0	0	0	0	80026	1	6	6	0	25	320130	80100	160032	80000	80100	160000	80000	4408199	3758372	9826290	0	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	16	80012	0	0	0	16	80009	6	1	10	14	0	5110	1	16	1	1	80038	1	80000	7	7	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	0	0	0	0	0	0	0	0	34	0	1	0	0	80026	1	6	6	0	25	320140	80100	160032	80000	80100	160000	80000	4408215	3758303	9826026	0	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	14	80010	0	0	0	14	80009	6	0	0	14	0	5110	1	16	1	1	80038	1	80000	6	6	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	0	0	1	0	0	0	0	0	16	0	0	0	0	80026	1	6	6	0	25	320132	80100	160040	80000	80100	160000	80000	4408215	3758263	9826308	0	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	14	80010	0	2	0	10	80011	6	0	10	18	0	5110	1	16	1	1	80038	1	80000	6	6	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	0	0	1	0	1	0	0	0	27	0	0	0	0	80026	1	6	6	0	25	320130	80100	160040	80000	80100	160000	80000	4408215	3758370	9826519	0	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80000	0	0	0	14	80010	5	0	0	14	0	5110	1	16	1	1	80038	1	80000	6	6	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	0	0	1	0	1	1	0	0	27	0	0	0	0	80026	1	6	6	0	25	320132	80100	160040	80000	80100	160000	80000	4408215	3758346	9826135	0	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	14	80010	0	0	0	13	80010	6	0	12	0	0	5110	1	16	1	1	80038	1	80000	9	6	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	0	0	0	0	0	0	0	0	18	0	0	0	0	80026	1	6	6	0	25	320140	80100	160032	80000	80100	160000	80000	4408215	3758361	9825990	0	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	14	80000	0	0	0	13	80010	6	0	9	14	0	5110	1	16	1	1	80038	1	80000	0	9	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	0	0	1	0	0	0	0	0	15	0	0	0	0	80026	1	6	6	4	25	320138	80100	160032	80000	80100	160000	80000	4408215	3758368	9826154	0	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	14	80009	0	0	0	13	80010	0	0	9	14	0	5110	1	16	1	1	80163	1	80000	8	6	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	642	0	0	1	0	0	0	0	0	16	0	0	0	0	80026	1	6	6	0	25	320130	80100	160040	80000	80100	160000	80000	4408215	3758372	9826022	0	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	14	80010	0	0	0	10	80012	0	0	9	14	0	5110	1	16	1	1	80038	1	80000	9	6	80000	160000	80100	80042	80167	80042	80166	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	24	3f	43	46	49	4c	4f	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240025	80041	620	0	0	0	0	0	0	23	0	0	80026	1	0	6	0	0	0	25	320010	80010	160048	80000	80010	160000	80000	4407696	3758378	9825979	80022	0	80041	80041	49947	0	3	50021	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80022	10	9	10	10	80000	80000	0	10	80000	0	0	80018	0	0	17	80013	6	1	18	22	0	5020	4	15	4	5	80038	1	80000	13	0	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	620	0	0	1	0	0	0	24	0	0	80026	1	6	6	0	0	0	25	320058	80010	160048	80000	80010	160000	80000	4407696	3758377	9825741	80022	0	80041	80041	49947	0	3	50021	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80018	1	0	18	80018	6	1	14	22	0	5455	5	16	3	3	80038	1	80000	13	14	80000	160000	80010	80042	80042	80434	80042	80042
240024	80041	643	0	0	0	0	0	0	54	0	0	80026	1	6	6	155	3	0	25	320050	80010	160038	80000	80010	160000	80000	4407683	3758376	9825739	80022	0	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80018	0	0	14	80000	0	1	0	22	0	5020	4	15	5	7	80038	1	80000	0	10	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	621	0	0	0	0	0	0	24	0	0	80026	1	6	0	0	0	0	25	320010	80010	160000	80000	80010	160000	80000	4407696	3758378	9825741	80022	0	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80018	0	0	35	80014	6	1	18	22	0	5020	4	15	3	5	80038	1	80000	10	10	80000	160000	80010	80042	80042	81496	84421	80763
240024	80041	621	0	0	0	0	0	0	12	0	1	80026	1	6	6	0	3	0	25	320050	80010	160038	80000	80010	160000	80000	4407684	3762296	9834809	80131	0	80041	80480	49947	46	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	85710	0	18	84749	0	0	61493	85723	6	1	18	22	0	5020	5	15	3	3	80038	1	80000	13	10	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	599	0	0	0	0	0	0	24	0	0	80026	1	6	6	0	0	0	25	320058	80010	160046	80000	80010	160000	80000	4407696	3758376	9825741	80022	0	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80018	0	0	14	80013	6	0	0	22	0	5020	4	15	3	3	80038	1	80000	10	13	80000	160000	80010	80042	80042	80042	80042	80183
240024	80041	599	0	0	0	0	0	0	23	0	0	80026	1	0	6	0	13	0	53	320010	80010	160048	80000	80010	160000	80000	4407684	3758374	9825768	80022	0	80041	80041	49981	0	3	50022	320010	20	80000	160285	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80000	0	0	13	80014	6	1	13	0	0	5020	3	15	3	3	80038	1	80000	10	0	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	600	0	0	0	0	0	0	24	0	0	80026	0	6	0	0	0	0	25	320050	80010	160048	80000	80010	160000	80000	4407696	3758361	9825741	80022	0	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80017	0	0	18	80014	0	0	0	0	0	5020	3	15	3	5	80038	0	80000	0	13	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	600	0	0	0	0	0	0	0	0	0	80026	1	6	6	0	0	0	25	320056	80010	160048	80000	80010	160000	80000	4407696	3758382	9825751	80022	0	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80000	0	0	0	80014	6	1	18	22	0	5020	3	15	4	2	80038	1	80000	13	10	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	620	0	0	0	0	0	0	24	0	0	80026	1	0	6	0	0	0	25	320058	80010	160046	80000	80010	160000	80128	4407696	3758371	9825741	80022	0	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80018	0	0	0	80014	0	0	0	18	0	5020	3	15	4	4	80038	0	80000	10	10	80000	160000	80010	80042	80042	80042	80042	80042

LD2 (multiple, post-index, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations