Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2 (multiple, post-index, 4H)

Test 1: uops

Code:

  ld2 { v0.4h, v1.4h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.006

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.006

retire uop (01)cycle (02)03l1i tlb fill (04)l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f191e1f23243a3f43464951schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd load (98)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
63005289582241121111600001000480428469010165104012100020021000100020001000500050432389513002263728580287113104000100020002000200028601286941161001100010001100002100100251002113001354296216984315495220093321138041349542814610001531912485137851000200010002859828568286352862728664
630042867822201181018100025000485528364000165314012100020101000100020001000500050002383430022730284972853031040001000200020002000284972855011610011000100001000021000002510002241113409958369123207125819939320138101554592819110001539512291137291000200010002871328538285602872128690
630042878722200140022000040004785283980001653540001000200010001001200010005000501323864600227362852228654310400010002000200020002868828627116100110001000010000310010015810012241113491954969713226145120103314738011557552813710001508712425137461000200010002866728666287762865928605
6300428696222001600170000400047172823900116624400610002006100010002000100050005010239141500227412841528625310400010002000200020002846428543116100110001000010032410020014810010000013344952969843154124720026317138131655582811310001558712690136851000200010002871828685287152872628548
6300428800222012901201000500048362849500116582400810002012100010002000100050005000238481300227152857628690310400010002000200020002847228657116100110001000010000210011015710032121212933954869633131115319989317938101656512809410001516412604136171000200010002865928628286352864728749
630042852922200200024000040004792283070011657240061000200010001000200010005000500324066100022643284712863731040001000200020002000285862868811610011000100001001301005021910002000013263953969673153134920033328838081255572804310001524912569138111000200010002866228701285992862428600
630042875322300180019000010004831284980001660740021000200610001000200010005000501623814900226982838828679310400010002000200020002867628561116100110001000110022410050015110013241013278976469333222135720006321938062256612818710001538112548136371000200010002863428699286472871428599
630042867822201201120100050004856283390001653040061000200810001000200010005000500323892200022775284802836231040001000200020002000286322864111610011000100001000021001101371003224131325596597018316585120055327338051354522810410001549012289133321000200010002864728590286192873628672
6300428800224001800170000000047682851901116539400610002006100010002000100050005013238911000226962848328654310400010002000200020002858428571116100110001000010022310030013910012000013187972269533219115519974314238071453542803510001514012437132721000200010002876828611287682875928760
6300428593223011801211010600047992835400116433401010002012100010002000100050005013238071100227242850628691310400010002000200020002872628555116100110001000010000210010013910002231113052954269493128155819913321238091857522807810001470712412136941000200010002873928724286922869228583

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.4h, v1.4h }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0050

retire uop (01)cycle (02)0309l2 tlb miss data (0b)0e0f18191e1f23243a3f4d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)acafb5l1d cache miss ld nonspec (bf)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
70205140175108500110113200001400361395962590119501003000310001401003012010000124353853313571611495014007914015214003513076031311548010030200100413000060200200803000014014914005121502011009910040100100001000001001000001000213361000111032331911113972450000000100002000050100140056140156140036140136140151
7020414017210860001010000014013513961225901175010030004100004024130239101181237017533147116112739140031140144140054130730313124480394302001004030000604522000030118140035140052215020110099100401001000010000010010000110000043510000110321011211113983250000131013100002000050100140036140052140055140055140052
702041400541085001000101001400391395962590103501003000010000401003000010000123702653314711611467714001214005414005113071131311598010030200100003000060200200003000014003514005411502011009910040100100001000001001000111000004771000001032341971213972150000101310100002000050100140050140048140051140051140050
70204140035113100000016000014003613955525901035010030003100004010030000100001244813533074616114109140024140050140050130728313119480100302001000030000602002000030000140035140035115020110099100401001000010000010010000010000731000011032101801113972250000969100002000050100140051140051140051140052140051
70204140050112200000013000014003713955225901035013330003100004024335072106261244813533124316114109140012140051140141130727313119480400302001004030000602002000030000140117140245115020110099100401001000010000010010001110000161000001032332801113970550011900100002000050100140137140051140055140155140051
7020414005611340000001480010140035139553259014150100300071000040243300001000012447955331132161141091400261401431400521307293131197806923020010041300006068820000301211400511400351150201100991004010010000100000100100001100001643601000110032332801213979450000969100002000050100140051140149140051140247140231
7020414004911340000001000014013013957781901035010030008100004068430000100391244786533323516114226140104140141140051130729313119580398302001000030000606882000030122140050140047215020110099100401001000010000010010003010003132531000011032581951113981650019969100002000050100140051140051140142140051140255
70204140142112100000022176000140136139589259010350100300031000040100300001000012369255330042161141091400261400501400501307273131194801003020010000300006020020000300001400521400503150201100991004010010000100000100100001100000310000100321011211113970550000709100002000050100140051140051140055140051140048
7020414005311240000004000014003513955225901035010030003100004010030000100001244786533008116114109140322140050140050130726291311948010030200100003000060200200003000014005014004711502011009910040100100001000001001000011000026310000110321011211113972250000099100002000050100140048140051140036140051140048
7020414005211250000004000014003513957725901035010030003100004010030000100001236963533016216114109140026140050140053130726313119480100302001000030000602002000030000140050140048115020110099100401001000010000010010000110000147910000110321011211113972250000960100002000050100140051140051140051140048140150

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0054

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f233a3f4043494d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5e6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
7002514004810490000000130001400350001396592590013500103000310000400103000010000124587953331731611501000014002614005014004713074931312098001030020100003000060020200003012414004714003511500211091040010100001000001010000011001200031901000010000003140005874413970750000966100002000050010140048140051140051140050140054
700241400501086000000010001400350001396502590013500103000310001400103000010000124584753332851612017600014010114003514005013081131312068001030020100003000060020200803000014003514003611500211091040010100001000001010000011000301031000010100003140005875513970750000969100002000050010140092140051140051140036140139
70024140053108500000001300014003600013965254900105001030003100004001030000100401245907533328516114779000140011140138140051130734151312068001030020100003000060020200003000014004714012611500211091040010100001000001010000001000001001000010100003140003875513972550007969100002000050010140111140053140051140139140036
7002414005010860000011060001400350001396362590030500103000010000400103000010000124576153352701612422800014008714004714014313075231311948001030020100003000060020200003011914005014003511500211091040010100001000001010000021000100032211000111100003140005873413972750010006100002000050010140094140061140051140051140051
70024140051108500000112800014002000013965025900135001030007100004001030000100391245907533270616113346000140023140050140050130749171312098001030020100003000060020200003000014004814004721500211091040010100001000001010000011000003001000010000003187005874413972150000666100002000050010140051140053140054140053140154
7002414005010860000100130001400200001396472590013500213000310000400103012110000124587953331731611477900014002614003514003513075231312098001030142100003000060020200003000014013714005311500211091040010100001000011010000001000000031000010100003140003874313972250000909100002000050010140135140051140051140051140051
70024140047112600000001450001400350001396472590013500233000310000400103000010000124756453327061611477900014002314012914005313074958213324280310300201000030148600202000030000140048140047115002110910400101000010000110100062010013012165051000600000003140003873413971950010766100002000050010140051140142140102140036140036
7002414005011250000000138800140132000139794259001350010300071000040010300001000012458795333285161181660001400971400501400501307493131209800103014210000301486002020000300001400501400351150021109104001010000100000101000021100000001921000110100003140004875513971950000966100002000050010140056140157140056140062140056
700241400551125000000020001400280101396352590013500103000310000400103000010000124591653342151611477900014002614003714003513074631313078001030020100003000060020200003000014004714014521500211091040010100001000011010000211000000001000110100003140004874613972550000666100002000050010140048140139140052140051140051
70024140050112500000100000140132000139647259001350010300031000040010300001000012458795336281161147790001400941400351400471307491613121080010300201000030000600202000030000140130140047115002110910400101000010000010100002110000000310001101000031400048734139863501121009100002000050010140438140242140335140326140305

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.4h, v1.4h }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0075

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f18191e1f22243a3f4d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
70205140063105000111002000014006013961725901065010030003100004010030000100001244911533225916116480140042140057140057130733313121080100302001000030000602002000030000140075140066115020110099100401001000010000010010001311000111110000101100321011211113973850000969100002000050100140064140064140067140057140076
7020414007510860011000200001400861396172590106501003000310000401003000010000123721453322591611742614005114007514007613073331311788010030200100003000060200200003000014007514006811502011009910040100100001000001001000211100020011000011110032101801113974550000069100002000050100140056140064140064140056140058
702041400751086000000020000140060139617259010650100300061000040100300001000012449025330530161162361400331400751400751307513131201801003020010000300006020020000300001400751400751150201100991004010010000100000100100012110001004100001111103210712111139729500001090100002000050100140064140076140076140082140076
7020414007510861111000200001400621396172590106501003000610000401003000010000124500753305301611623614003914007514007513075131312268010030200100003000060200200003000014007514006811502011009910040100100001000001001000120100014141000010010032101801113974550000990100002000050100140076140064140064140064140058
70204140075108610110012000014005313960825901215010030006100004010030000100001237083533053016115220140039140063140075130775313117880100302001000030124602002000030000140075140068115020110099100401001000010000010010001311000100110000101110321021211113974550000999100002000050100140058140076140064140064140064
702041401611085101010008800014006013956525901065010030003100004010030000100001244902533544816107932140051140075140075130751313124180100302001000030000602002000030000140075140068115020110099100401001000010000010010001111000100410000111110321011211113973850000970100002000050100140058140076140076140159140060
70204140057108612000001000014004813956525901065010030003100014010030000100001244902533188216116236140031140063140055130751313117880100302001000030000602002008230000140075140075115020110099100401001000010000010010001211000112410000111100321011211113974550000999100002000050100140060140076140076140077140076
7020514016610861011000288000140042139630259010650100300061000040100300001003912371785330647161164801400331400641400661307391613117880100302001000030000602002000030000140075140075215020110099100401001000010000010010002211000111410001101110321011211113973550000999100002000050100140076140158140076140076140064
70204140075108611000001000014013413962425901065010030006100004010030000100001239968533225916119890140126140063140063130740313117880100302001000030000602002000030000140077140068115020110099100401001000010000010010001111000220110000101000321011211113972550000969100002000050100140076140076140077140076140064
70204140063108611000000000014004013956525901035010030006100004010030000100001237178533225916117309140051140063140072130732313117880100302001008030121604462008230119140063140252315020110099100401001000010000010010007411000503639110002111100323411351213989550041969100002000050100140354140234140801142615142557

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0052

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)0e0f18191e1f22233a3f4d5051schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)91inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5l1d cache miss ld nonspec (bf)branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
700251400561086000000100001400221397370259001350010300031000040010300001000012459255333361161150041140012014005214005213073531312118001030020100003000060020200003000014003614004911500211090104001010000100000101000001100000001000001031402874313972450010666100002000050010140051140050140199140082140053
7002414003610850010004601001401371397990259001350010300031000040010300001000012459255333361161202431140092014005214003613074831311958001030020100003000060020200003000014005214004911500211090104001010000100000101000001100000031000011031403873313972450000960100002000050010140037140037140211140451140053
700241400361086001000100001400421397050259001350010300001000040010300001000012458975332745161190321140096014003914005213075131312118001030020100003000060020200003000014005214003611500211090104001010000100001101000001100000001000001031403872213970850000969100002000050010140154140053140058140136140053
7002414005210860000001000014003713965802590010500103000010000400103000010040124585653327451611357611400280140054140052130738313121180010300201000030000600202000030000140151140049115002110901040010100001000011010000011000000319010000110314031222213972450000690100002000050010140415140053140126140103140053
7002414003610860000001000014003413965702590010500103000310000400103000010039124592553332491611462411400280140054140052130751313121180010300201000030000600202000030000140135140052115002110901040010100001000001010000011000000320510000010314021222213973150000900100002000050010140060140060140141140059140037
700241400541086000000100101400371396540259001050010300031000140010300001000012459255332865161150041140012014005214005213075131312118001030020100003000060262200003000014004914004911500211090104001010000100001101000000100000001000010031402872213979450000669100002000050010140037140038140130140054140053
7002414003610860000011300001400371397100539001350010300001000040010300001000012458565332745161134601140012014015114005213075131311958001030020100003000060020200003000014003614003611500211090104001010000100000101000001100000031000001031403872213972450000099100002000050010140037140053140098140337140053
70024140052108500000010000140037139713025900265001030005100004015130118100001248175533560616115004114010901401461401441308352813130580908303841008230246609902016030242140248140231215002110901040010100001000011010001211000410645010002110382221163213987350031069100002000050010140235140223140250140419140440
7002414042710862010001200001400371396490259001350010300001000040010300001000012458565332862161134601140017014005214003613075131312138001030020100003000060020200003014414005214005211500211090104001010000100000101000001100000031000011031402873313972450000990100002000050010140053140055140050140141140053
700241400361085001000100001400371397060259001350010300071000040010300001000012459255332745161134601140031014003614005213075131312118001030020100003000060020200003000014003614005211500211090104001010000100001101000001100000001000011031402872313972450000999100002000050010140053140053140156140057140053

Test 4: throughput

Count: 8

Code:

  ld2 { v0.4h, v1.4h }, [x6], x8
  ld2 { v0.4h, v1.4h }, [x6], x8
  ld2 { v0.4h, v1.4h }, [x6], x8
  ld2 { v0.4h, v1.4h }, [x6], x8
  ld2 { v0.4h, v1.4h }, [x6], x8
  ld2 { v0.4h, v1.4h }, [x6], x8
  ld2 { v0.4h, v1.4h }, [x6], x8
  ld2 { v0.4h, v1.4h }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2223243a3f4346494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
24020580041620000110000100080026166025320100801001602188000080100160000800004408215375836198262940800228004180041499240349999320100200800001600002001600001600008004180041218020110099100100800008000001008000001880015001980014611418051103161180038080000131080000160000801008004280042800428004280042
240204800416210000100001000800261600253201008010016004680000801001600008000044082153758361982541108002280041800414992403499993201002008000016000020016000016000080041800411180201100991001008000080000010080000018801051008000001022051102161180038180000131080000160000801008004280042800428004280042
240204800416210001000000000800261664425320100801001600388000080100160000800004408197375836198254110800228004180041499240349999320100200800001600002001600001600008004180041118020110099100100800008000001008000001880014003811630000051101161180038180000131380000160000801008004280042800428004280042
24020480041621000100024000008002616602532014880100160040800008010016000080000440821537583769826290080022800418004149924034999932010020080000160000200160000160000800418004111802011009910010080000800001100800000228001600080018611422051102161180038180000131080000160000801008004280042800428004280042
240204800416200000000240000080026160025320100801001600008000080100160000800004408215375836198262900800228004180041499240304999932010020080000160000200160000160000800418004111802011009910010080000800000100800000188000010188001761018051281161180038180000101080000160000801008004280042800428004280042
24020480041621000110024000018002616002532010080100160222800008010016000080000440821537583619825411080022800418004149924034999932010020080000160000200160266160000800418004111802011009910010080000800000100800000080017100800006117220511021611800380800000080000160000801008004280042800428004280042
24020480041621000000000000080026106025320100801001600008000080100160000800004408209375836198255330800228004180041499240350081320100200800001602652001600001600008004180041118020110099100100800008000001008000002280000201199800000102205110116118003818000013080000160000801008004280042800428004280042
2402048004162000000002000000800261064253201008019216004880090801001600008000044082153758381982541108002280041800414992403499993201002008000016000020016000016000080322800411180201100991001008000080000010080000018800180008010961172205110116118003818000001380000160000801008004280042800428004280042
2402048004162100010002400000800261660253201488010016004680000803791600008000044104643758376983546808012780183800414992403500793201002008000016053520016026616000080041801811180201100991001008000080000010080088208001800208001861142205128152128003818000013080000160000801008018380042800428004280042
2402048004162201000101568800008030610644703208848028716022480092803911602718040144105663761864985324808012680322801804998139315008032170520280271160272200160266160270804668018121802011009910010080000800000100801782080000000800006000051104161180038180000131380000160000801008004280042800428004280042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2223243a3f4346494e4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)dfe0e7? int output thing (e9)eaeb? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
2400258004162011001101350100080026106402532008280010160012800008001016000080000440761137583649826364180022800418004149947035002132001020801331600002016000016000080041800411180021109101080000800000108000782780030000308012061302772502031633080143180000131380000160000800108004280042800428018280042
24002480041621101100003700000800261664625320022800101600728000080010160000800004407617376190898262871800228004180041499470350021320010208000016000020160000160000800418004111800211091010800008000001080006727801180003180023611422005020315330800381800000080000160000800108004280042800428004280042
2400248004162100000000340000080026166002532005680010160048800008001016000080000440769637583639825745180022800418004149947035002232055320800001600002016026616000080041800411180021109101080000800000108000700801050000800186102270502031543080038180000101080000160000800108004280042800428004280042
2400248018362011000001120000080026000442532001080010160048800008001016000080000440769337619499825741180022800418004149947035002132001020800001600002016000016000080041800411180021109101080000800000108000001880018010188002360181800502041663080038080000131380000160000800108004280042800428004280042
2400248004162000000000360000080026000002532001080010160000800008001016000080000440768637583659825801180022800418004149947035002232001020800001600002016000016000080041800411180021109101080000800001108000702780018010218001761132260502031563080038180000131080000160000800108004280042800428004280042
2400248004162110000000240000080026066472532005880010160046800918001016000080000440769637583699825736180022800418004149947035002132001020800001600002016000016000080041800412180021109101080000800000108000002280018010178000061182200502031543080038180000131380000160000800108004280042800428004280042
24002480041620000000003600000800261660025320058800101600488000080010160000800004407689375836598346791800228004180041499470350022320010208000016000020160000160000800418004111800211091010800008000001080008027800180201880018611407050201331543080038180000131380000160000800108004280042800428004280042
2400248004162110000000240000180146166407032005680010160040800008001016000080000440769637583769825741180022800418004149947035002132001020800001600002016027216000080041800411180021109101080000800000108000001880018000148002361182200502031533080038180000131380000160000800108004280042800428018380042
24002480041620000000004600000800261660025320056800101600488000080010160000801354407696375836398251381800228004180041499470350022320010208000016000020160000160000800418004111800211091010800008000001080094008001400017800176114186250202154308003808000001380000160000800108004280042800428004280042
2400248004162111000000240000080026066472532005680010160048800008001016000080000440769637583769825989180022800418004149947035002232001020800001600002016000016000080183800411180021109101080000800004108000001880017000218010960142200502031533080038080000151380000160000800108004280042800428004280042