Firestorm: LD2 (multiple, post-index, 4S) measurements

Code:

  ld2 { v0.4s, v1.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.006

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
64005	29629	237	1	16	1	0	18	0	1	1	0	0	8	0	0	4700	29078	0	0	0	17296	5008	1000	2008	2000	1000	2000	2000	5000	10000	23916	5	22862	29270	29462	3	10	5000	2000	2000	3003	4000	29279	29437	2	1	61001	1000	1000	0	2010	2	0	2004	0	0	492	2004	4	4	0	2	0	0	13167	9371	6982	3074	6	38	20564	3316	3813	9	36	39	28848	1001	15829	13219	14464	2000	2000	1000	29618	29501	29491	29520	29488
64004	29566	236	1	9	2	2	14	1	1	0	1	10	392	0	0	4532	29071	0	0	0	17135	5006	1001	2006	2000	1000	2000	2000	5000	10000	23920	5	22939	29343	29587	9	49	5005	2002	2000	3000	4004	29443	29360	2	1	61001	1000	1000	0	2005	3	6	2006	0	6	404	2002	6	2	4	2	3	0	13227	9386	6941	3158	3	41	20650	3371	3820	14	40	37	28787	1000	16185	13215	14514	2000	2000	1000	29340	29286	29696	29457	29487
64004	29739	239	1	13	1	1	13	0	0	0	0	0	11	0	0	4620	29058	0	2	0	17442	5008	1000	2006	2000	1000	2000	2000	5000	10000	23871	1	22860	29201	29363	3	10	5000	2000	2000	3000	4000	29184	29254	1	1	61001	1000	1000	0	2003	270	0	2007	3	1	4	2000	2	4	4	2	1	1816	13418	9606	6929	3159	6	39	20507	3327	3815	3	37	40	28677	1000	16458	13114	14416	2000	2000	1000	29267	29313	29391	29412	29309
64004	29330	236	1	14	0	1	17	1	0	0	0	0	2	0	1	4737	28923	0	0	2	17149	5008	1000	2002	2000	1000	2000	2000	5000	10000	23872	3	22889	29225	29366	3	10	5000	2000	2000	3000	4000	29174	29275	1	1	61001	1000	1000	0	2004	3	4	2007	0	1	4	2000	6	2	4	2	1	0	13143	9530	6909	3130	7	35	20396	3298	3820	7	40	37	28595	1000	15975	13046	14421	2000	2000	1000	29405	29405	29357	29314	29463
64004	29357	237	1	14	1	0	8	1	0	0	0	0	8	0	0	4600	28945	2	0	0	17228	5002	1000	2002	2000	1000	2000	2000	5000	10000	23828	4	22863	29171	29312	3	10	5000	2000	2000	3000	4000	29309	29259	1	1	61001	1000	1000	0	2003	3	4	2003	0	1	4	2000	4	2	4	2	2	0	13193	9455	6885	3152	6	38	20321	3232	3819	10	35	34	28680	1000	16265	13030	14258	2000	2000	1000	29337	29339	29366	29315	29406
64004	29402	236	1	10	0	1	12	0	0	0	0	0	14	0	0	4777	28877	0	2	0	17081	5008	1000	2006	2000	1000	2000	2000	5000	10000	23902	2	22899	29343	29421	3	10	5000	2000	2000	3000	4000	29208	29221	1	1	61001	1000	1000	0	2003	3	0	2005	0	0	2	2000	4	2	4	2	1	0	13071	9495	6919	3130	7	34	20531	3274	3818	12	40	37	28625	1000	16254	13138	14498	2000	2000	1000	29391	29432	29504	29375	29404
64004	29361	236	1	12	0	0	10	1	0	0	0	0	9	0	0	4608	28977	0	0	0	17230	5002	1000	2002	2000	1000	2000	2000	5000	10000	23911	4	22868	29214	29287	3	10	5000	2000	2000	3000	4000	29396	29268	1	1	61001	1000	1000	0	2002	3	6	2003	2	1	2	2002	0	2	4	2	1	0	13328	9478	6972	3164	4	36	20432	3235	3820	7	33	31	28667	1000	16155	13131	14437	2000	2000	1000	29395	29428	29398	29423	29377
64004	29434	236	1	9	0	1	12	1	0	0	0	0	9	0	0	4684	28871	0	1	0	17292	5002	1000	2002	2000	1000	2000	2000	5000	10000	23914	0	22896	29229	29463	3	10	5000	2000	2000	3000	4000	29147	29266	1	1	61001	1000	1000	0	2002	2	4	2003	0	1	5	2000	4	2	4	2	1	0	13006	9517	6920	3163	4	33	20401	3299	3816	10	37	37	28610	1000	16081	13376	14490	2000	2000	1000	29468	29437	29389	29418	29374
64004	29489	236	1	11	1	1	13	1	1	1	0	0	14	0	0	4711	29082	0	0	0	17190	5006	1000	2008	2000	1000	2000	2000	5000	10000	23892	2	22857	29308	29319	3	10	5000	2000	2000	3000	4000	29387	29291	1	1	61001	1000	1000	0	2004	3	4	2003	1	1	2	2000	0	2	4	2	1	0	13141	9390	6912	3182	6	34	20469	3350	3819	10	34	37	28642	1000	16018	13118	14385	2000	2000	1000	29382	29398	29376	29405	29351
64004	29386	236	1	15	0	0	11	1	0	0	0	0	9	0	0	4638	29035	0	0	0	17136	5002	1000	2002	2000	1000	2000	2000	5000	10000	23816	4	22871	29261	29513	3	10	5000	2000	2000	3000	4000	29288	29270	1	1	61001	1000	1000	0	2003	3	4	2004	0	0	2	2000	4	2	4	2	1	0	13270	9469	6981	3114	9	34	20377	3328	3819	5	32	39	28634	1000	16168	13187	14115	2000	2000	1000	29399	29436	29345	29452	29425

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.4s, v1.4s }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80205	140057	1086	1	0	0	0	0	0	0	0	11	0	0	1	140036	127300	129686	25	100103	50100	30003	20000	40100	30000	20000	16078646	6692068	12182337	1	140027	140051	140052	129505	3	129934	90100	30200	20000	30000	60200	30000	50000	140051	140047	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	0	0	20000	2	0	2	0	0	0	3210	1	16	1	1	139791	50000	10	6	10	20000	20000	50100	140052	140052	140052	140052	140052
80204	140047	1086	0	0	0	0	0	0	0	0	2	0	0	1	140039	127300	129686	25	100106	50100	30006	20000	40100	30000	20000	16078534	6692068	12182337	0	140027	140051	140051	129506	3	129934	90100	30200	20000	30000	60200	30000	50000	140052	140047	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	0	3	20000	2	0	0	0	0	0	3210	1	16	1	1	139792	50000	10	6	0	20000	20000	50100	140052	140055	140048	140053	140052
80204	140047	1086	0	0	0	0	0	0	0	0	6	0	0	1	140036	127300	129686	25	100100	50110	30011	20000	40100	30000	20000	16078650	6692068	12182337	0	140011	140051	140051	129506	3	129936	90100	30200	22232	31672	60200	30000	50000	140054	140047	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	2	3	20000	2	0	0	0	0	0	3210	2	16	1	1	139795	50000	10	0	10	20000	20000	50100	140052	140036	140052	140052	140052
80204	140051	1086	0	0	0	0	0	0	0	0	146	0	0	1	140020	127300	129686	125	100106	50100	30006	20000	40100	30000	20050	16078534	6691290	12182337	0	140028	140051	140260	129548	3	129918	90100	30200	20000	30000	60200	30000	50000	140051	140121	1	1	50201	100	99	100	40100	10000	10000	0	100	20004	0	2	20000	0	0	0	0	20000	0	0	0	0	0	0	3210	1	16	1	1	139797	50009	6	6	12	20000	20000	50100	140036	140036	140131	140064	140052
80204	140037	1086	1	0	0	0	0	1	0	0	16	0	0	0	140032	127300	129670	25	100103	50100	30003	20000	40100	30090	20000	16076864	6692068	12182337	0	140027	140051	140051	129501	13	129934	90100	30200	20000	30000	60200	30000	50000	140035	140142	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20002	0	1	0	0	20000	2	0	2	2	0	0	3210	1	16	1	1	139791	50000	10	0	10	20000	20000	50100	140052	140053	140052	140147	140052
80204	140051	1085	0	0	0	0	0	0	0	0	2	0	0	1	140036	127300	129723	25	100106	50100	30006	20000	40100	30000	20000	16078534	6691434	12182337	0	140027	140035	140047	129501	3	129934	90100	30200	20000	30000	60200	30000	50000	140052	140052	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	0	20088	0	1	0	3	20000	2	0	0	0	0	0	3210	1	16	1	1	139791	50000	11	10	10	20000	20000	50100	140052	140052	140052	140052	140053
80204	140035	1086	0	0	0	0	0	0	0	0	38	0	0	1	140036	127300	129686	25	100103	50100	30000	20000	40100	30000	20000	16078534	6692164	12182337	1	140027	140051	140047	129501	3	129934	90100	30200	20000	30000	60200	30000	50000	140145	140035	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	0	20000	0	0	0	3	20000	0	0	2	0	0	0	3210	1	16	1	1	139775	50000	10	6	12	20000	20000	50100	140147	140052	140052	140052	140052
80204	140047	1085	0	0	0	0	0	0	0	0	0	0	0	1	140036	127300	129686	25	100106	50100	30003	20000	40100	30000	20000	16078070	6694518	12182337	0	140028	140051	140051	129505	3	129934	90100	30200	20000	30000	60200	30000	50000	140051	140035	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	0	0	20000	2	0	2	0	0	0	3210	1	16	1	1	139775	50010	10	6	0	20000	20000	50100	140048	140053	140090	140036	140036
80204	140051	1086	0	0	0	0	0	0	0	0	6	0	0	1	140036	127300	129727	75	100103	50100	30003	20000	40100	30000	20000	16078534	6691290	12182693	0	140023	140051	140051	129509	3	129934	90100	30200	20000	30000	60200	30000	50000	140051	140047	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	0	3	20000	2	0	2	0	0	0	3210	1	16	1	1	139791	50000	6	6	10	20000	20000	50100	140036	140052	140053	140052	140052
80204	140035	1086	0	0	0	1	0	1	0	0	2	176	0	1	140321	126287	129799	102	100138	50131	30014	20002	40460	30360	20100	16223980	6765336	12307101	0	140186	140137	140242	129593	24	130084	90624	30481	20248	30093	60946	30279	50310	140319	140219	4	1	50201	100	99	100	40100	10000	10000	0	100	20058	0	2	20004	0	0	7	7660	20008	2	0	0	0	2	0	3293	1	32	3	1	139850	50000	10	10	0	20000	20000	50100	140036	140048	140052	140052	140036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80025	140061	1125	1	1	1	0	0	0	0	0	0	34	0	0	0	1	140132	127306	129696	25	100013	50010	30003	20000	40010	30000	20000	16078712	6692356	12183407	1	140034	140058	140058	129601	3	130031	90010	30020	20000	30000	60020	30000	50000	140057	140057	1	1	50021	10	9	10	40010	10000	10000	0	10	20003	3	2	20000	0	1	2	3	20000	2	2	2	2	1	0	3140	12	16	12	12	139801	50000	14	10	10	20000	20000	50010	140063	140058	140058	140062	140052
80024	140055	1125	0	0	0	0	0	1	0	1	0	2	0	0	0	0	140036	127300	129732	25	100013	50010	30003	20000	40010	30000	20000	16078252	6692260	12182873	0	140027	140056	140055	129599	14	130008	90010	30020	20000	30000	60020	30000	50000	140051	140052	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	2550	20000	2	0	2	0	0	0	3140	11	16	12	10	139791	50000	10	10	10	20000	20000	50010	140053	140151	140052	140052	140052
80024	140055	1125	0	0	1	0	0	0	0	0	0	5	0	0	0	0	140036	127300	129686	25	100016	50020	30006	20000	40010	30000	20000	16078600	6692356	12181974	0	140033	140057	140057	129601	3	130030	90010	30020	20000	30000	60020	30000	50000	140061	140057	1	1	50021	10	9	10	40010	10000	10000	0	10	20002	3	2	20000	0	0	0	0	20000	2	0	2	0	12	0	3140	11	16	11	12	139792	50000	10	13	10	20000	20000	50010	140056	140052	140052	140052	140052
80024	140051	1124	0	0	0	0	0	0	0	0	0	17	88	0	0	0	140040	127301	129686	25	100010	50010	30003	20000	40010	30090	20000	16077904	6692260	12182873	0	140107	140055	140055	129595	3	130029	90010	30020	20000	30000	60020	30000	50000	140058	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	20004	0	2	20000	0	1	0	0	20000	2	0	2	0	0	0	3140	13	16	13	10	139791	50010	10	10	10	20000	20000	50010	140052	140052	140052	140053	140052
80024	140055	1125	0	0	0	0	0	0	0	0	0	2	0	0	0	0	140036	127301	129687	126	100013	50010	30003	20000	40010	30000	20050	16077904	6692068	12182873	0	140031	140051	140055	129599	3	130024	90010	30020	20062	30000	60020	30000	50000	140057	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	3	20000	2	0	2	0	0	0	3140	12	16	12	13	139791	50000	10	10	10	20000	20000	50010	140053	140053	140052	140052	140139
80024	140057	1124	0	0	0	0	0	1	1	0	0	8	0	0	0	0	140036	127300	129686	25	100013	50010	30003	20000	40010	30000	20000	16078352	6694422	12182873	0	140031	140056	140051	129595	3	130024	90010	30020	20000	30093	60020	30000	50000	140052	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	0	20000	2	0	2	0	0	0	3140	12	16	9	13	139775	50000	10	10	10	20000	20000	50010	140052	140053	140052	140052	140052
80024	140051	1124	0	0	0	0	0	0	0	0	0	11	0	0	0	0	140036	127300	129691	25	100013	50010	30003	20000	40010	30000	20000	16077904	6692068	12186708	0	140029	141974	143929	129877	3	130024	90010	30020	20000	30000	60020	30000	50000	140036	140144	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	3	0	6	20002	2	0	2	0	0	0	3140	11	16	9	13	139791	50000	10	10	10	20000	20000	50010	140052	140058	140053	140052	140057
80024	140051	1125	0	0	0	0	0	0	0	0	0	2	0	0	0	1	140036	127300	129686	25	100013	50010	30003	20000	40010	30000	20000	16077904	6692068	12182873	0	140027	140051	140098	129599	3	130028	90010	30020	20000	30000	60020	30000	50000	140052	140055	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	9	20000	2	0	2	0	0	0	3161	8	16	11	11	139795	50000	10	10	10	20000	20000	50010	140052	140056	140052	140052	140052
80024	140051	1125	0	0	0	0	0	0	0	0	1	5	0	0	0	0	140040	127305	129689	25	100013	50010	30003	20000	40010	30000	20000	16077904	6692068	12182873	0	140031	140051	140051	129598	3	130024	90010	30020	20000	30000	60020	30000	50000	140051	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	1	0	0	20000	2	0	2	0	0	0	3163	13	16	12	11	139791	50000	12	14	10	20000	20000	50010	140054	140052	140052	140052	140052
80024	140051	1125	0	0	0	0	0	0	0	0	1	2	0	0	0	0	140124	127093	129690	25	100093	50020	30003	20000	40010	30090	20000	16084038	6692260	12182962	0	140031	140051	140051	129599	3	130069	90270	30020	20124	30000	60206	30000	50000	140142	140054	2	1	50021	10	9	10	40010	10000	10000	0	10	20004	0	2	20002	0	0	0	2	20000	2	2	2	2	3	0	3170	13	16	12	12	139865	50010	10	10	14	20000	20000	50010	140062	140043	140150	140059	140137

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.4s, v1.4s }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80205	140047	1049	0	0	0	0	0	0	6	0	0	0	1	140020	127297	129670	25	100103	50100	30003	20000	40100	30000	20000	16078534	6692116	12182337	0	140027	140051	140052	129505	3	129935	90100	30200	20000	30000	60200	30000	50000	140051	140035	1	1	50201	100	99	100	40100	10000	10000	0	100	20002	0	0	2	0	20000	1	3	20000	2	0	0	0	3210	2	16	1	1	139791	50000	10	6	10	20000	20000	50100	140052	140054	140052	140052	140052
80204	140047	1085	0	0	0	0	0	0	2	88	0	0	0	140020	127301	129686	25	100103	50100	30003	20000	40100	30000	20000	16076640	6692212	12182337	0	140027	140051	140051	129505	3	129918	90100	30200	20000	30000	60200	30000	50000	140056	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	0	2	0	20000	1	0	20000	2	2	0	0	3210	1	16	1	1	139791	50000	10	0	10	20000	20000	50100	140036	140048	140036	140052	140052
80204	140035	1125	0	0	0	0	0	0	2	0	0	0	0	140036	127297	129686	25	100103	50100	30003	20000	40100	30000	20000	16076640	6692068	12181242	0	140027	140035	140035	129505	3	129934	90100	30200	20000	30000	60200	30000	50000	140137	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	0	2	0	20000	0	0	20000	2	2	0	0	3210	1	16	1	1	139791	50000	6	0	0	20000	20000	50100	140052	140038	140141	140048	140052
80204	140051	1125	0	0	0	1	0	0	6	0	0	0	1	140020	127297	129686	25	100103	50100	30003	20000	40100	30000	20000	16078534	6692068	12181242	0	140028	140037	140143	129489	3	129918	90100	30293	20000	30000	60200	30000	50000	140054	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	0	2	0	20000	4	3	20000	2	2	0	0	3210	1	16	1	1	139775	50000	10	6	6	20000	20000	50100	140054	140052	140065	140052	140052
80204	140051	1124	0	0	0	1	0	0	0	0	0	0	0	140036	127300	129682	25	100103	50100	30003	20000	40220	30000	20000	16076640	6692068	12182337	0	140027	140035	140055	129505	3	129935	90100	30200	20000	30000	60200	30000	50000	140140	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	0	2	0	20000	0	2513	20000	2	2	0	0	3210	1	48	1	1	139775	50000	10	6	10	20000	20000	50100	140128	140052	140052	140052	140141
80204	140038	1125	0	0	0	0	0	0	2	0	0	0	0	140036	127302	129686	25	100100	50100	30000	20000	40100	30000	20000	16076752	6692068	12182337	0	140027	140053	140051	129505	3	129938	90100	30200	20000	30098	60200	30000	50000	140058	140052	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	0	0	0	20000	0	0	20000	0	0	0	0	3210	1	16	1	1	139791	50000	6	6	10	20000	20000	50100	140052	140048	140055	140052	140052
80204	140053	1125	0	0	0	0	9	1	2	0	1	0	1	140036	127302	129670	50	100103	50100	30003	20000	40100	30000	20000	16076640	6692068	12181242	0	140027	140051	140056	129489	3	130038	90100	30200	20000	30000	60200	30000	50000	140144	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	0	2	0	20000	0	0	20000	2	2	0	0	3210	2	16	1	1	139775	50000	13	6	10	20000	20000	50100	140053	140052	140052	140053	140036
80204	140037	1125	0	0	0	0	0	0	14	0	1	0	1	140036	127300	129686	25	100103	50100	30007	20000	40220	30000	20000	16076976	6691290	12182337	0	140027	140052	140051	129505	3	129949	90100	30293	20000	30000	60200	30093	50000	140051	140047	1	1	50201	100	99	100	40100	10000	10000	0	100	20012	0	0	2	0	20013	1	12703	20010	2	2	0	0	3230	1	56	1	2	140287	50072	10	0	10	20000	20000	50100	140676	140578	140447	140650	140134
80204	140733	1130	0	0	0	0	0	3	914	712	1	0	1	140036	127307	129727	25	100119	50100	30003	20000	40100	30000	20000	16078650	6692068	12182337	0	140028	140054	140051	129506	3	129940	90100	30293	20000	30000	60200	30000	50000	140041	140052	2	1	50201	100	99	100	40100	10000	10000	1	100	20000	0	0	2	0	20000	0	0	20000	0	2	0	0	3210	1	16	2	1	139791	50000	10	0	10	20000	20000	50100	140048	140054	140036	140139	140054
80204	140053	1124	0	0	0	0	1	0	14	0	0	0	1	140123	126159	129687	25	100119	50100	30003	20000	40100	30000	20000	16078070	6692068	12186377	0	140027	140051	140037	129541	3	129966	90360	30293	20682	30093	60762	30186	52325	140236	140326	4	1	50201	100	99	100	40100	10000	10000	0	100	20011	0	0	2	0	20000	7	2550	20002	2	2	0	0	3229	1	24	2	0	139907	50000	0	8	10	20000	20000	50100	140230	140052	140055	140054	140052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0055

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	18	19	1e	1f	22	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80025	140051	1085	0	0	1	0	0	0	0	17	0	0	0	1	140020	127300	129686	25	100013	50010	30003	20000	40010	30000	20000	16077904	6692260	12182873	0	140031	0	140057	140055	129601	3	130028	90010	30020	20000	30000	60020	30186	50000	140055	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	0	20000	0	0	0	20000	2	0	2	0	0	0	3142	5	0	3	16	2	2	139795	50000	14	10	10	20000	20000	50010	140056	140036	140053	140052	140056
80024	140148	1085	0	0	0	0	0	0	0	134	0	0	0	0	140040	127303	129692	25	100013	50010	30003	20000	40010	30090	20000	16078368	6692260	12182873	0	140031	0	140055	140055	129595	3	130028	90010	30392	20124	30000	60020	30000	50000	140055	140055	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	1	0	0	20000	2	0	2	0	0	0	3144	5	0	3	16	3	2	139791	50000	14	10	14	20000	20000	50010	140056	140056	140052	140052	140052
80024	140055	1085	0	0	0	0	0	0	0	2	0	0	0	1	140036	127302	129690	25	100013	50010	30003	20000	40010	30000	20000	16076010	6692404	12182873	0	140037	0	140061	140061	129606	3	130034	90010	30020	20000	30000	60020	30000	50000	140064	140064	1	1	50021	10	9	10	40010	10000	10000	0	10	20002	2	2	20003	1	0	5	20000	2	2	0	2	0	0	3142	5	0	3	16	3	3	139802	50000	14	14	14	20000	20000	50010	140062	140042	140062	140062	140062
80024	140061	1085	1	0	0	0	0	0	0	16	0	0	0	0	140046	127310	129696	25	100016	50010	30006	20000	40010	30000	20000	16079064	6692356	12183407	0	140039	0	140041	140061	129601	3	130034	90010	30020	20000	30000	60020	30000	50000	140061	140057	1	1	50021	10	9	10	40010	10000	10000	0	10	20002	2	2	20002	0	1	2	20000	2	0	2	0	0	0	3140	5	0	3	16	3	3	139791	50000	14	10	14	20000	20000	50010	140056	140056	140056	140036	140056
80024	140056	1086	0	0	0	0	0	0	0	2	0	0	0	1	140036	127304	129692	25	100013	50010	30003	20000	40010	30000	20000	16078368	6692260	12182873	0	140034	0	140055	140055	129599	3	130028	90010	30020	20000	30000	60020	30000	50000	140056	140056	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	20000	0	0	2	0	0	0	3140	5	0	3	16	3	3	139795	50000	14	0	14	20000	20000	50010	140056	140056	140058	140057	140056
80024	140055	1086	0	0	0	0	0	0	0	2	0	0	0	1	140036	127305	129691	25	100013	50010	30003	20000	40010	30000	20000	16078368	6692260	12182873	0	140032	0	140055	140055	129599	3	130031	90010	30020	20000	30000	60020	31023	56045	143905	141449	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	2530	20000	2	0	2	0	0	0	3140	5	0	2	24	3	2	139795	50000	14	10	12	20000	20000	50010	140056	140056	140036	140056	140056
80024	140058	1085	0	0	0	0	0	0	0	5	0	0	0	1	140040	127300	129691	25	100013	50010	30004	20000	40010	30000	20000	16078368	6691290	12182873	0	140031	0	140055	140058	129599	3	130028	90010	30392	20062	30000	60020	30000	50000	140055	140055	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	20000	0	0	2	0	0	0	3140	5	0	3	16	2	3	139795	50000	0	14	14	20000	20000	50010	140052	140053	140052	140056	140036
80024	140051	1086	0	0	0	0	0	0	0	14	0	0	0	1	140040	127304	129728	25	100010	50010	30003	20000	40010	30000	20000	16078368	6691290	12183229	0	140031	0	140055	140055	129599	3	130028	90270	30020	20000	30000	60020	30000	50000	140055	140036	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	0	20000	2	0	0	20000	2	0	2	0	0	0	3140	5	0	3	16	3	3	139795	50000	0	10	14	20000	20000	50010	140134	140036	140056	140056	140052
80024	140055	1086	0	0	0	0	1	0	0	2	0	0	0	1	140040	127308	129686	25	100013	50010	30003	20000	40010	30090	20000	16076010	6692260	12183988	0	140027	0	140035	140055	129599	3	130028	90010	30020	20000	30000	60020	30000	50155	140059	140052	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	1	0	3	20000	2	0	2	0	0	0	3142	5	0	3	24	3	2	139847	50020	0	10	14	20000	20000	50010	140150	140148	140056	140134	140142
80024	140128	1086	0	1	1	1	0	19	1	398	88	0	0	0	140324	124911	129788	128	100042	50050	30011	20038	43252	32610	21350	16238894	6766192	12301058	0	140215	0	140317	140328	129635	34	130080	91052	30299	20124	30279	60206	30372	50465	140249	140327	4	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	6	20000	2	0	2	0	0	0	3140	5	0	2	16	4	3	139791	50000	14	10	10	20000	20000	50010	140036	140058	140056	140036	140052

Test 4: throughput

Count: 8

Code:

  ld2 { v0.4s, v1.4s }, [x6], x8
  ld2 { v0.4s, v1.4s }, [x6], x8
  ld2 { v0.4s, v1.4s }, [x6], x8
  ld2 { v0.4s, v1.4s }, [x6], x8
  ld2 { v0.4s, v1.4s }, [x6], x8
  ld2 { v0.4s, v1.4s }, [x6], x8
  ld2 { v0.4s, v1.4s }, [x6], x8
  ld2 { v0.4s, v1.4s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst simd alu (9a)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320205	80070	643	0	0	0	0	0	0	36	0	0	0	0	81794	2	12	12	27	79	400432	80160	160146	160116	80216	160130	160124	481182	1003721	2155316	0	80023	80262	80153	48	27	60	400410	200	160124	160124	200	240186	320248	80265	80155	3	1	80201	100	99	100	100	80000	0	80000	100	160104	33	160136	0	0	1099	160141	6	1	37	41	0	1	1	1	5144	0	25	0	0	80135	1	80060	10	10	160000	160000	80100	80268	80160	80244	80155	82116
320204	82022	659	0	1	1	0	1	1	168	176	0	0	0	80140	2	12	12	54	51	400688	80223	160254	160116	80108	160124	160016	480860	960415	2085208	0	80115	80371	80154	69	27	60	400410	200	160016	160016	200	240024	320032	80043	80043	1	1	80201	100	99	100	100	80000	0	80000	100	160002	41	160031	1	0	37	160038	6	0	29	41	0	1	1	1	5116	0	16	0	0	80135	1	80006	10	10	160000	160000	80100	80045	80045	80045	80638	80044
320204	80044	643	0	0	0	0	0	0	35	0	1	0	0	80028	2	12	12	0	26	400154	80106	160046	160008	80108	160016	160016	480538	960734	2080136	0	80023	80043	80044	0	6	14	400140	200	160016	160016	200	240024	320032	80044	80043	1	1	80201	100	99	100	100	80000	0	80000	100	160002	33	160039	0	0	35	160039	6	1	30	41	0	1	1	1	5117	0	16	0	0	80040	0	80006	10	10	160000	160000	80100	80044	80044	80044	80044	80045
320204	80043	642	0	0	0	0	0	0	55	0	0	0	0	80029	2	12	12	0	26	400154	80106	160040	160008	80108	160016	160016	480538	960736	2081146	0	80023	80044	80043	69	7	14	400140	200	160016	160016	200	240024	320032	80043	80044	1	1	80201	100	99	100	100	80000	0	80000	100	160002	33	160039	0	0	30	160031	6	1	30	33	0	1	1	1	5117	0	16	0	0	80041	0	80006	14	10	160000	160000	80100	80044	80044	80045	80045	80044
320204	80043	643	0	0	0	0	0	0	42	0	0	0	2	80029	2	12	12	0	25	400156	80106	160042	160000	80100	160000	160000	480499	960331	2080976	0	80023	80042	80042	0	3	24	400100	200	160000	160000	200	240000	320000	80042	80042	1	1	80201	100	99	100	100	80000	0	80000	100	160000	33	160037	0	0	30	160030	6	1	30	33	0	0	0	0	5109	1	17	1	1	80039	0	80000	10	14	160000	160000	80100	80043	80043	80043	80043	80043
320204	80042	643	0	0	0	1	0	0	35	0	0	0	2	80027	2	12	12	0	25	400136	80100	160042	160000	80100	160000	160000	480499	960328	2080960	0	80023	80042	80042	0	3	24	400100	200	160000	160000	200	240000	320000	80042	80042	1	1	80201	100	99	100	100	80000	0	80000	100	160000	41	160029	1	0	0	160029	6	1	30	33	0	0	0	0	5109	1	17	1	1	80039	1	80000	14	10	160000	160000	80100	80043	80043	80043	80043	80043
320204	80042	643	0	0	0	0	0	0	35	0	0	0	2	80027	2	12	12	0	25	400138	80100	160044	160000	80100	160000	160000	480499	960361	2080976	0	80023	80042	80056	0	3	24	400100	200	160000	160000	200	240000	320000	80042	80042	1	1	80201	100	99	100	100	80000	0	80000	100	160000	33	160037	1	0	37	160029	6	1	37	41	0	0	0	0	5109	1	17	1	1	80039	1	80000	0	10	160000	160000	80100	80043	80043	80043	80043	80043
320204	80042	643	0	0	0	0	0	0	36	0	0	0	0	80027	2	12	12	0	25	400136	80100	160044	160000	80100	160000	160000	480499	960852	2080972	0	80023	80042	80042	0	3	24	400100	200	160000	160000	200	240000	320000	80042	80042	1	1	80201	100	99	100	100	80000	0	80000	100	160000	33	160030	0	0	30	160000	6	1	30	41	0	0	0	0	5109	1	17	1	1	80039	0	80000	10	10	160000	160000	80100	80043	80043	80043	80043	80043
320204	80042	643	0	0	0	0	0	0	35	0	0	1	0	80027	2	12	0	0	25	400142	80100	160036	160000	80100	160000	160000	480499	960660	2080960	0	80023	80042	80042	0	3	24	400100	200	160000	160000	200	240000	320000	80042	80042	1	1	80201	100	99	100	100	80000	0	80000	100	160000	33	160030	0	0	37	160029	6	0	30	33	0	0	0	0	5109	1	17	1	1	80039	0	80000	14	10	160000	160000	80100	80043	80043	80043	80043	80043
320204	80042	643	0	0	0	0	0	0	0	0	0	0	2	80027	2	12	0	0	25	400142	80100	160042	160000	80100	160000	160000	480499	960330	2080982	0	80023	80042	80042	9	3	24	400100	200	160000	160000	200	240000	320000	80042	80042	1	1	80201	100	99	100	100	80000	0	80000	100	160000	33	160037	0	0	37	160037	6	1	30	42	0	0	0	0	5109	1	17	1	1	80039	0	80000	10	10	160000	160000	80100	80043	80043	80043	80043	80043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	80056	642	0	0	0	0	0	0	0	0	0	0	57	0	0	0	0	2	80027	2	0	15	0	25	400056	80010	160028	160000	80010	160000	160000	480049	964177	2080512	0	80023	80042	80042	0	3	24	400010	20	160000	160000	20	240000	320000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160011	10	40	160047	0	0	0	46	160022	6	1	47	25	10	0	0	5019	2	17	2	2	80039	0	80000	9	9	160000	160000	80010	80043	80043	80043	80043	80043
320024	80042	643	1	0	0	0	0	1	1	1	0	0	11	0	0	0	0	0	80027	3	0	14	0	25	400022	80010	160010	160000	80010	160000	160000	480047	960922	2081810	0	80023	80042	80042	0	3	24	400010	20	160000	160000	20	240000	320000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160011	10	0	160047	0	0	1	10	160036	6	1	11	40	10	1	0	5019	2	17	2	2	80039	0	80000	9	9	160000	160000	80010	80043	80043	80043	80043	80043
320024	80042	643	1	0	0	1	0	0	0	0	0	0	54	0	0	0	0	0	80027	2	13	15	0	25	400062	80010	160046	160000	80010	160000	160000	480042	960931	2082146	0	80023	80042	80042	0	3	24	400010	20	160000	160000	20	240000	320000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160010	11	40	160012	0	0	0	50	160037	6	1	46	40	11	0	0	5019	2	17	2	2	80039	0	80000	9	12	160000	160000	80010	80043	80043	80043	80043	80043
320024	80042	643	1	0	0	0	0	0	0	0	0	0	52	0	1	0	0	0	80027	0	14	0	0	25	400062	80010	160048	160000	80010	160000	160000	480049	961026	2081872	0	80023	80042	80042	0	3	24	400010	20	160000	160000	20	240000	320000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160012	11	40	160046	0	0	0	46	160036	6	1	49	40	10	1	0	5019	2	17	2	2	80039	0	80000	9	9	160000	160000	80010	80043	80043	80043	80043	80043
320024	80042	643	1	0	1	1	0	0	0	0	0	0	10	0	0	0	1	2	80027	0	0	0	0	25	400062	80010	160048	160000	80010	160000	160000	480049	972999	2081834	0	80023	80042	80042	0	3	24	400010	20	160000	160000	20	240324	320000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160011	12	40	160011	0	1	0	47	160036	6	1	10	0	10	1	0	5019	2	17	2	2	80039	0	80000	0	0	160000	160000	80010	80043	80043	80043	80043	80043
320024	80042	644	1	0	0	1	0	1	0	0	0	0	11	0	0	0	0	0	80027	3	14	14	0	25	400058	80010	160052	160000	80010	160000	160000	480049	965904	2081986	0	80023	80042	80042	0	3	24	400010	20	160000	160108	20	240000	320000	80042	80042	1	1	80021	10	9	10	10	80000	80000	1	10	160013	11	40	160046	0	1	1	47	160037	6	0	10	40	11	0	0	5019	2	17	2	2	80039	0	80000	9	0	160000	160000	80010	80043	80043	80043	80043	80043
320024	80042	643	1	0	0	1	0	0	0	0	0	0	59	0	0	0	0	2	80027	2	14	14	0	25	400058	80010	160052	160000	80010	160000	160000	480371	960945	2081968	0	80023	80042	80042	0	3	24	400280	20	160000	160000	20	240000	320000	80042	80042	1	1	80021	10	9	10	10	80000	80000	1	10	160011	10	40	160046	0	0	1	48	160036	0	1	47	0	10	1	0	5019	2	17	2	2	80039	0	80000	9	0	160000	160000	80010	80043	80043	80043	80043	80043
320024	80042	643	1	0	0	1	0	1	1	0	0	0	56	0	0	0	0	2	80027	3	14	14	0	51	400062	80010	160048	160000	80010	160000	160000	480049	968352	2082000	0	80023	80042	80042	23	3	24	400010	20	160000	160000	20	240000	320000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160012	10	42	160047	0	0	0	49	160138	6	1	47	0	10	0	0	5019	2	17	2	2	80039	0	80000	9	9	160000	160000	80010	80043	80043	80043	80043	80043
320024	80042	643	1	0	0	0	0	1	1	0	0	0	58	0	0	0	0	2	80027	3	14	14	0	25	400058	80010	160052	160000	80010	160000	160000	480049	967300	2081892	0	80115	80042	80042	0	3	24	400010	20	160000	160000	20	240000	320000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160011	10	40	160011	0	2	0	14	160037	6	1	47	43	11	1	0	5019	2	17	2	2	80039	0	80000	11	9	160000	160000	80010	80043	80043	80043	80043	80043
320024	80042	643	1	0	0	1	0	1	0	0	0	0	16	0	0	0	0	2	80027	2	14	0	0	25	400058	80010	160044	160000	80010	160000	160000	480049	965637	2086142	0	80023	80042	80042	0	3	24	400010	20	160000	160000	20	240162	320000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160012	10	40	160049	0	0	0	47	160036	6	1	47	40	10	1	0	5019	2	17	2	2	80039	0	80000	9	9	160000	160000	80010	80043	80043	80043	80043	80043

LD2 (multiple, post-index, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations