Firestorm: LD2 (multiple, post-index, 8B) measurements

Code:

  ld2 { v0.8b, v1.8b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.004

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
63005	28848	224	4	1	0	1	4	1	0	0	2	0	1	0	4680	28322	0	1	1	16637	4004	1000	2004	1000	1000	2000	1000	5000	5000	23856	12	1	0	22681	28523	28711	3	10	4000	1000	2000	2000	2000	28677	28533	1	1	61001	1000	1000	0	1000	0	2	1001	0	1	1001	1	1	3	0	0	13173	9296	6985	3147	1	58	20030	3233	3808	13	62	60	28097	1000	15358	12657	13476	1000	2000	1000	28691	28771	28631	28739	28690
63004	28793	223	2	1	0	2	1	1	0	0	4	0	0	0	4603	28342	0	1	1	16478	4004	1000	2006	1000	1000	2000	1000	5000	5000	23854	12	1	0	22738	28662	28746	3	10	4000	1000	2000	2000	2000	28670	28546	1	1	61001	1000	1000	0	1000	0	0	1001	0	1	1001	1	1	0	0	0	13195	9452	7062	3199	1	60	20056	3217	3804	14	70	58	28099	1000	15497	12738	13664	1000	2000	1000	28659	28655	28761	28620	28670
63004	28795	223	1	1	0	1	0	0	0	0	2	0	0	0	4670	28301	0	1	1	16512	4004	1000	2004	1000	1000	2000	1000	5000	5001	23842	12	1	0	22755	28570	28713	3	10	4000	1000	2000	2000	2000	28559	28684	1	1	61001	1000	1000	0	1000	0	0	1001	0	1	1001	1	1	3	0	0	13347	9301	6917	3144	2	70	20039	3143	3806	18	62	68	28171	1000	15451	12533	13564	1000	2000	1000	28729	28611	28760	28672	28697
63004	28788	223	2	1	0	0	0	0	0	0	0	0	0	0	4714	28332	0	0	1	16613	4004	1000	2004	1000	1000	2000	1000	5000	5000	23840	12	1	0	22683	28508	28631	3	10	4000	1000	2000	2000	2000	28540	28575	1	1	61001	1000	1000	0	1000	0	2	1001	0	0	1001	1	1	0	0	0	13480	9595	6974	3172	1	62	19944	3223	3812	13	67	63	28137	1000	15336	12422	13551	1000	2000	1000	28828	28750	28829	28718	28765
63004	28738	222	1	1	0	1	0	0	0	0	0	0	0	0	4787	28343	0	0	1	16660	4004	1000	2004	1000	1000	2000	1000	5000	5000	23844	7	1	0	22694	28662	28697	3	10	4000	1000	2000	2000	2000	28605	28572	1	1	61001	1000	1000	0	1000	0	2	1001	0	1	1001	2	0	2	0	0	13297	9694	7002	3169	1	59	20012	3145	3819	20	61	59	28192	1000	15191	12659	13895	1000	2000	1000	28695	28727	28858	28782	28640
63004	28816	222	2	0	0	1	0	0	0	0	0	0	0	0	4770	28365	0	1	0	16584	4004	1000	2000	1000	1000	2000	1000	5000	5000	23834	12	0	0	22661	28429	28779	3	10	4000	1000	2000	2000	2000	28631	28582	1	1	61001	1000	1000	0	1000	0	2	1001	0	1	1000	1	1	2	0	0	13003	9547	6932	3230	0	60	20027	3145	3810	21	65	61	28202	1000	15370	12656	13450	1000	2000	1000	28702	28631	28613	28652	28819
63004	28809	222	1	1	0	0	0	0	0	0	7	0	0	0	4712	28418	0	0	0	16629	4004	1000	2004	1000	1000	2000	1000	5000	5000	23842	7	1	0	22773	28473	28688	3	10	4000	1000	2000	2000	2000	28655	28534	1	1	61001	1000	1000	0	1000	0	0	1001	0	0	1000	1	2	2	0	0	13362	9361	6952	3205	0	60	20089	3182	3807	15	59	61	28120	1000	15227	12485	13674	1000	2000	1000	28704	28689	28749	28801	28647
63004	28672	222	1	0	0	1	0	0	0	0	2	0	0	0	4853	28350	0	1	1	16641	4004	1000	2000	1000	1000	2000	1000	5000	5000	23849	5	1	0	22683	28530	28740	3	10	4000	1000	2000	2000	2000	28575	28485	1	1	61001	1000	1000	0	1000	0	2	1001	0	1	1002	1	1	2	0	0	13228	9408	6904	3208	2	58	19915	3213	3809	21	61	65	28122	1000	15196	12445	13744	1000	2000	1000	28668	28662	28620	28721	28697
63004	28699	223	1	0	0	0	0	0	0	0	2	0	0	0	4780	28355	1	0	1	16583	4004	1000	2004	1000	1000	2000	1000	5000	5000	23852	7	0	7	22761	28569	28775	3	10	4000	1000	2000	2000	2000	28665	28599	1	1	61001	1000	1000	0	1000	0	2	1001	0	4	1001	0	0	2	0	0	13260	9397	6925	3170	0	62	20006	3226	3814	11	60	65	28128	1000	15350	12633	14060	1000	2000	1000	28692	28779	28703	28652	28741
63004	28663	222	0	0	0	0	0	0	0	0	2	0	0	0	4671	28301	0	1	1	16595	4004	1000	2004	1000	1000	2000	1000	5000	5000	23810	6	0	0	22730	28581	28713	3	10	4000	1000	2000	2000	2000	28653	28638	1	1	61001	1000	1000	0	1000	0	2	1001	0	1	1000	1	1	0	0	0	13346	9409	7013	3181	0	62	19931	3223	3820	20	63	67	28112	1000	15361	12575	13869	1000	2000	1000	28742	28731	28599	28685	28657

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.8b, v1.8b }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140057	1125	1	0	1	1	0	0	0	0	2	0	0	0	140045	139659	81	90156	50110	30010	10002	40243	30000	10000	1237044	5331699	16115305	140036	140065	140060	130733	3	131161	80100	30200	10000	30000	60200	20000	30000	140060	140041	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10002	0	0	1	1	10000	0	1	1	1	0	0	3210	1	121	1	1	139787	50000	14	0	13	10000	20000	50100	140062	140064	140061	140043	140061
70204	140235	1126	1	2	0	0	0	0	0	0	2	0	0	0	140046	139599	25	90106	50100	30006	10000	40100	30000	10000	1237035	5331775	16115305	140036	140061	140060	130736	3	131163	80100	30200	10000	30000	60200	20000	30000	140060	140041	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	2	1	10001	0	0	0	4	10002	1	1	1	1	0	0	3210	1	121	1	1	139740	50000	0	13	14	10000	20000	50100	140062	140061	140042	140061	140061
70204	140060	1125	1	0	0	0	0	0	0	0	2	0	0	0	140045	139602	25	90106	50100	30006	10000	40100	30000	10000	1237017	5331699	16115539	140036	140060	140063	130736	3	131160	80100	30200	10000	30000	60200	20000	30000	140060	140057	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10001	0	0	0	10	10000	1	1	1	1	0	0	3210	1	121	1	1	139733	50000	13	10	16	10000	20000	50100	140061	140061	140175	140377	140061
70204	140060	1125	1	0	1	1	0	0	0	0	2	0	0	0	140146	139602	643	90685	50523	30113	10000	40406	30000	10078	1258170	5339086	16130257	140619	140904	140713	130929	112	131611	81897	31181	10321	30975	62625	20484	30853	140804	140613	7	1	50201	100	99	100	40100	10000	10000	0	100	10008	1	0	10009	0	0	0	19286	10010	1	1	1	1	0	0	3398	1	167	1	1	139924	50000	13	11	13	10000	20000	50100	140061	140156	140153	140158	140158
70204	140155	1124	1	2	0	0	0	0	0	1	134	0	0	0	140218	139683	53	90145	50100	30010	10000	40241	30000	10040	1237044	5331387	16110604	140036	140145	140041	130736	17	131219	80400	30200	10040	30000	60446	20000	30121	140060	140147	2	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10001	0	2	1	4	10000	1	1	0	1	0	0	3210	1	106	1	1	139727	50000	0	10	13	10000	20000	50100	140061	140148	140061	140061	140061
70204	140057	1125	1	0	1	2	0	0	0	1	134	0	0	0	140026	139602	25	90103	50110	30006	10000	40100	30000	10039	1237044	5331699	16115726	140036	140060	140060	130769	3	131165	80100	30200	10000	30120	60200	20000	30000	140060	140060	1	1	50201	100	99	100	40100	10000	10000	0	100	10005	2	1	10001	0	0	0	1	10001	1	1	1	1	2	0	3233	1	110	0	1	140115	50000	9	148	6	10000	20000	50100	140057	140058	140133	140060	140051
70204	140150	1124	1	0	0	0	0	0	0	0	13	0	0	1	140042	139702	53	90103	50100	30006	10000	40100	30121	10000	1237008	5331587	16109316	140034	140154	140056	130732	3	131159	80100	30200	10000	30000	60200	20000	30000	140057	140143	1	1	50201	100	99	100	40100	10000	10000	0	100	10004	1	1	10001	0	1	1	4	10001	0	1	1	1	0	0	3210	1	121	1	1	139713	50010	9	6	9	10000	20000	50100	140057	140059	140058	140057	140042
70204	140059	1126	1	1	0	1	0	0	1	0	14	0	0	1	140141	139598	44	90106	50100	30010	10001	40100	30000	10000	1237053	5333631	16116432	140108	140148	140148	130732	16	131160	80100	30200	10000	30122	60450	20000	30000	140149	140055	2	1	50201	100	99	100	40100	10000	10000	0	100	10005	1	1	10002	0	1	3	3257	10001	0	1	1	1	1	0	3210	1	101	1	1	139841	50021	10	0	9	10000	20000	50100	140138	140151	140036	140036	140053
70204	140150	1125	0	1	0	1	0	0	0	0	145	0	0	0	140038	139731	79	90103	50100	30009	10000	40382	30118	10000	1236934	5335354	16121707	140543	140733	140855	131052	90	131695	82514	31432	11941	36199	70460	20080	30245	140050	140035	1	1	50201	100	99	100	40100	10000	10000	0	100	10006	0	0	10003	0	2	0	3268	10001	0	0	1	0	0	0	3233	2	80	1	1	139789	50000	9	6	9	10000	20000	50100	140052	140049	140226	140229	140244
70205	140149	1125	0	1	0	1	0	0	2	1	145	0	0	0	140213	139631	82	90124	50110	30004	10001	40100	30120	10039	1249079	5333285	16113483	140013	140093	140050	130784	16	131272	80411	30443	10000	30000	60442	20000	30242	140222	140050	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	0	1	10000	0	1	0	6388	10000	1	0	1	0	4	0	3257	1	95	1	2	139717	50011	0	0	9	10000	20000	50100	140146	140051	140138	140052	140145

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140053	1086	1	0	0	0	0	0	0	0	6	0	0	0	0	140032	139656	0	25	90013	50010	30006	10000	40010	30000	10000	1245961	5333517	16109908	0	140032	140056	140056	130756	3	131212	80010	30020	10000	30000	60020	20000	30000	140056	140056	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	3	10000	0	0	1	0	0	3140	5	87	5	4	139722	50000	9	6	9	10000	20000	50010	140042	140042	140057	140042	140042
70024	140053	1085	1	1	0	1	0	0	0	0	2	0	0	0	0	140041	139650	0	25	90010	50010	30003	10000	40010	30000	10000	1245907	5333285	16114779	0	140023	140035	140035	130734	3	131194	80010	30020	10000	30000	60020	20000	30000	140050	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	1	10002	0	0	4	10000	1	1	1	1	0	3140	6	87	5	7	139728	50000	9	6	0	10000	20000	50010	140051	140048	140048	140036	140051
70024	140047	1085	0	0	0	0	0	0	0	0	1	0	0	0	0	140035	139641	0	25	90016	50010	30006	10000	40010	30000	10000	1245961	5333517	16115415	0	140017	140056	140056	130755	3	131212	80010	30020	10000	30000	60020	20000	30000	140056	140056	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	1	0	0	10000	1	0	1	0	0	3140	6	87	5	5	139722	50000	0	9	9	10000	20000	50010	140057	140054	140042	140057	140054
70024	140053	1086	1	0	0	0	0	0	0	0	7	0	1	0	0	140026	139651	0	25	90013	50010	30003	10000	40010	30000	10000	1245907	5333285	16114779	0	140026	140036	140035	130746	3	131209	80010	30020	10000	30000	60020	20000	30000	140050	140050	1	1	50021	10	9	10	40010	10000	10000	1	10	10002	1	1	10001	0	1	1	10000	0	1	1	1	0	3140	6	87	4	4	139729	50000	6	6	9	10000	20000	50010	140053	140048	140048	140036	140051
70024	140050	1085	0	0	0	0	0	0	0	0	16	0	0	0	0	140036	139656	0	25	90013	50010	30006	10000	40010	30000	10000	1245961	5333517	16109908	0	140032	140067	140056	130755	3	131215	80010	30020	10000	30000	60020	20000	30000	140056	140053	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3140	5	87	5	5	139722	50000	9	9	0	10000	20000	50010	140054	140057	140057	140057	140057
70024	140056	1086	1	1	0	0	0	0	0	0	827	528	0	0	0	140041	139656	4	25	90013	50010	30003	20772	40010	30000	10000	1245856	5332706	16114896	1	140026	140057	140041	130756	3	131213	80010	30020	10000	30000	60020	20000	30000	140051	140051	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	6	10000	1	0	1	0	0	3140	5	87	4	5	139726	50000	13	10	18	10000	20000	50010	140055	140058	140058	140055	140055
70024	140057	1125	0	0	0	0	0	0	0	0	16	0	0	0	1	140039	139635	0	25	90013	50010	30003	10000	40010	30000	10000	1245943	5332706	16113346	0	140014	140054	140054	130778	3	132404	80010	30143	10000	30000	60260	20000	30000	140396	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	2	0	3	10000	1	0	1	0	0	4890	8	743	15	15	145373	50740	10	0	31	10000	20000	50010	140058	140058	140037	140055	140036
70024	140054	1125	0	0	0	0	0	0	0	0	12	0	0	0	0	140039	139654	0	25	90013	50010	30003	10000	40010	30000	10000	1245943	5332706	16113346	0	140027	140054	140054	130734	3	131213	80010	30020	10000	30000	60020	20000	30000	140054	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	0	10000	0	0	1	0	0	3140	4	87	5	4	139726	50000	0	0	8	10000	20000	50010	140055	140052	140055	140055	140059
70024	140054	1049	0	0	0	0	1	0	0	0	22	0	0	0	0	140039	139654	0	25	90013	50010	30003	10000	40010	30000	10000	1245943	5333441	16115181	0	140030	140054	140054	130753	3	131213	80010	30020	10000	30000	60020	20000	30000	140054	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3140	5	87	5	5	139726	50000	13	13	18	10000	20000	50010	140056	140057	140055	140052	140055
70024	140054	1049	0	0	0	0	0	0	0	0	1	0	0	0	0	140039	139651	0	25	90013	50010	30003	10000	40010	30000	10000	1245847	5333441	16115181	0	140030	140054	140054	130756	3	131213	80010	30020	10000	30000	60020	20000	30000	140054	140052	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10001	0	0	0	10000	1	0	1	0	0	3140	4	87	5	4	139728	50000	13	13	18	10000	20000	50010	140055	140055	140055	140036	140052

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.8b, v1.8b }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0075

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140058	1086	0	0	0	0	0	1	0	14	0	0	0	0	140065	139621	25	90106	50100	30006	10000	40100	30000	10000	1239968	5332449	16116858	1	140113	0	140065	140078	130751	0	3	131168	80100	30200	10000	30000	60200	20000	30000	140075	140075	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	8	1	10001	0	1	0	1	10001	1	0	1	0	0	0	3210	6	121	3	6	139745	50000	13	10	10	10000	20000	50100	140076	140076	140076	140076	140066
70204	140055	1085	0	0	0	0	0	0	0	2	0	0	0	1	140064	139618	53	90103	50100	30006	10000	40100	30000	10000	1237214	5332455	16117426	1	140031	0	140065	140065	130751	0	3	131158	80405	30200	10000	30000	60200	20000	30000	140075	140065	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	0	1	10000	0	0	0	0	10000	1	1	1	1	0	0	3233	5	121	6	6	139746	50000	13	13	13	10000	20000	50100	140080	140080	140080	140080	140080
70204	140079	1086	1	0	0	0	1	0	0	1	0	0	0	0	140040	139617	25	90103	50100	30000	10000	40242	30000	10000	1237195	5332342	16116123	1	140055	0	140057	140079	130749	0	3	131183	80100	30200	10000	30000	60200	20000	30000	140079	140081	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10002	0	1	1	4	10000	1	0	1	0	0	0	3234	6	121	4	6	139745	50029	13	13	13	10000	20000	50100	140056	140076	140076	140349	140163
70204	140160	1087	0	0	0	1	0	2	22	134	176	0	0	1	140146	139800	82	90137	50152	30010	10003	40384	30120	10118	1238606	5335034	16114413	1	140185	0	140156	140248	130760	0	42	131279	80708	33379	11132	33390	66656	22104	30367	140757	140159	4	1	50201	100	99	100	40100	10000	10000	0	100	10007	0	1	10004	0	0	0	9635	10003	1	1	0	1	3	0	3210	6	121	3	6	139752	50000	13	10	13	10000	20000	50100	140080	140080	140080	140081	140081
70204	140079	1086	1	0	0	1	1	0	0	1	0	0	0	0	140060	139621	25	90100	50100	30003	10000	40100	30000	10000	1237179	5332262	16116123	1	140052	0	140080	140076	130752	0	3	131190	80100	30200	10000	30000	60200	20000	30000	140079	140076	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10001	0	1	0	1	10000	1	0	1	0	0	0	3210	6	121	3	6	139745	50000	13	10	13	10000	20000	50100	140076	140076	140066	140076	140066
70204	140075	1086	0	0	0	1	0	0	0	14	0	0	0	0	140064	139621	25	90106	50100	30006	10000	40100	30000	10000	1237187	5332297	16117426	1	140051	0	140075	140075	130752	0	3	131178	80100	30200	10000	30142	60200	20000	30000	140075	140075	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	0	1	0	0	3210	6	121	3	6	139749	50000	10	13	13	10000	20000	50100	140080	140080	140077	140080	140080
70204	140079	1086	1	0	0	1	1	0	0	1	0	0	0	0	140060	139617	42	90103	50100	30003	10000	40100	30000	10000	1237083	5332262	16116123	1	140055	0	140079	140079	130755	0	3	131179	80100	30200	10000	30000	60200	20000	30000	140079	140076	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10002	0	1	0	1	10000	1	0	0	0	0	0	3210	6	121	3	6	139745	50000	13	0	13	10000	20000	50100	140076	140079	140076	140076	140076
70204	140075	1086	0	0	0	1	0	0	0	14	0	0	0	0	140064	139622	25	90106	50100	30006	10000	40100	30000	10000	1237214	5332411	16117426	0	140041	0	140075	140055	130741	0	3	131178	80100	30200	10000	30000	60200	20000	30000	140075	140065	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	1	0	0	10000	1	1	1	1	0	0	3210	6	121	6	6	139752	50000	13	13	13	10000	20000	50100	140108	140077	140080	140077	140080
70204	140079	1085	1	0	0	0	0	0	0	1	0	0	0	0	140060	139616	25	90103	50100	30003	10000	40100	30000	10000	1237179	5332262	16116123	1	140052	0	140079	140079	130755	0	3	131179	80100	30200	10000	30000	60200	20000	30000	140077	140076	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10002	0	0	0	1	10000	1	0	0	0	0	0	3210	6	121	3	6	139745	50000	13	10	13	10000	20000	50100	140066	140076	140076	140056	140076
70204	140075	1085	0	0	2	1	1	0	0	2	0	0	0	0	140064	139619	25	90106	50100	30006	10000	40100	30000	10000	1237214	5332489	16117426	0	140041	0	140075	140076	130751	0	3	131168	80100	30200	10000	30000	60200	20000	30000	140065	140078	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	0	3	10000	0	1	1	1	0	0	3210	6	121	6	6	139729	50000	13	10	0	10000	20000	50100	140080	140080	140058	140077	140080

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140049	1049	0	0	0	0	0	0	0	37	0	1	0	0	140039	139652	25	90013	50010	30003	10000	40010	30000	10000	1245897	5333249	16115004	0	140015	0	140051	140052	130748	3	131216	80010	30020	10000	30000	60020	20000	30000	140036	140049	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	0	1	0	3140	5	87	2	2	139711	50000	9	6	9	10000	20000	50010	140050	140053	140053	140056	140056
70024	140052	1086	0	0	0	0	0	0	0	1	0	0	0	0	140123	139652	25	90013	50010	30003	10000	40010	30000	10000	1245925	5333249	16115004	0	140029	0	140147	140052	130748	3	131214	80010	30020	10000	30139	60020	20000	30000	140036	140036	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	3	10000	1	1	0	3140	2	98	2	2	139724	50000	6	6	0	10000	20000	50010	140053	140050	140053	140050	140053
70024	140036	1086	0	0	0	0	1	0	0	0	88	0	0	0	140037	139649	25	90013	50010	30003	10000	40010	30000	10000	1245897	5333361	16115004	0	140025	0	140049	140052	130751	3	131208	80010	30020	10000	30000	60020	20000	30000	140052	140049	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	0	0	10000	1	1	0	3164	2	87	3	3	139721	50000	9	0	9	10000	20000	50010	140050	140053	140053	140053	140053
70024	140049	1085	0	0	0	1	0	0	0	13	0	0	0	1	140042	139636	25	90013	50010	30003	10000	40151	30000	10000	1245925	5333400	16115004	0	140028	0	140053	140052	130751	3	131211	80010	30020	10000	30000	60020	20000	30000	140145	140049	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	3245	10000	1	0	0	3140	2	87	2	2	139724	50000	9	6	9	10000	20000	50010	140102	140142	140037	140050	140053
70024	140054	1085	0	0	0	0	0	0	0	1	0	0	0	0	140130	139673	25	90013	50010	30000	10000	40010	30000	10000	1245865	5332745	16113460	0	140028	0	140052	140036	130751	3	131195	80308	30020	10000	30000	60020	20000	30000	140052	140049	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10005	0	4	0	3	10000	0	1	0	3163	2	87	3	3	139724	50000	9	9	9	10000	20000	50010	140053	140050	140050	140050	140050
70024	140036	1085	0	0	0	0	0	0	1	1	0	0	0	0	140021	139652	25	90013	50010	30003	10000	40010	30000	10000	1245925	5332745	16115004	0	140028	0	140052	140052	130778	3	131211	80010	30020	10000	30123	60020	20000	30000	140052	140052	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	3140	2	87	3	3	139724	50000	9	10	6	10000	20000	50010	140050	140053	140053	140053	140050
70024	140052	1086	0	0	0	0	0	0	0	25	88	0	0	0	140128	139652	25	90013	50010	30003	10000	40010	30000	10000	1245934	5333361	16115004	0	140029	0	140097	140050	130751	3	131211	80010	30020	10000	30000	60020	20000	30000	140052	140036	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	1	0	0	10000	1	1	0	3140	2	87	2	2	139810	50000	9	6	6	10000	20000	50010	140050	140053	140050	140050	140140
70024	140036	1086	0	0	0	0	0	0	0	6	0	0	0	0	140037	139652	25	90013	50010	30003	10002	40010	30000	10000	1245897	5332745	16115004	0	140025	0	140049	140036	130748	3	131208	80010	30020	10000	30000	60020	20080	30000	140036	140049	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	3	10000	1	0	0	3140	2	87	3	3	139724	50000	9	6	9	10000	20000	50010	140053	140053	140053	140053	140050
70024	140036	1086	0	0	0	0	0	0	0	13	88	0	0	0	140038	139649	25	90010	50010	30003	10000	40010	30000	10039	1245952	5333440	16115004	0	140031	0	140052	140054	130735	16	131195	80010	30020	10000	30000	60020	20000	30000	140052	140050	2	1	50021	10	9	10	40010	10000	10000	0	10	10001	0	1	10000	0	0	0	3	10001	1	1	0	3140	2	87	3	3	139724	50000	9	0	0	10000	20000	50010	140053	140053	140137	140037	140050
70024	140049	1086	0	0	0	0	1	0	0	1	0	0	0	1	140037	139652	25	90013	50010	30003	10000	40010	30000	10000	1245856	5333591	16115004	0	140028	0	140052	140036	130751	3	131195	80010	30020	10000	30000	60020	20000	30000	140036	140036	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10008	0	1	0	9605	10001	1	1	2	3186	2	103	2	4	139954	50020	0	0	9	10000	20000	50010	140211	140256	140331	140242	140353

Test 4: throughput

Count: 8

Code:

  ld2 { v0.8b, v1.8b }, [x6], x8
  ld2 { v0.8b, v1.8b }, [x6], x8
  ld2 { v0.8b, v1.8b }, [x6], x8
  ld2 { v0.8b, v1.8b }, [x6], x8
  ld2 { v0.8b, v1.8b }, [x6], x8
  ld2 { v0.8b, v1.8b }, [x6], x8
  ld2 { v0.8b, v1.8b }, [x6], x8
  ld2 { v0.8b, v1.8b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240205	80041	620	1	1	0	0	1	1	0	0	32	0	0	0	80026	1	6	6	1	6	25	320164	80100	160062	80000	80100	160000	80000	4408211	3758374	9826361	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	100	80008	6	23	80026	0	0	0	29	80018	6	1	6	23	7	0	5110	1	16	1	1	80038	1	80000	9	9	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	620	1	1	0	1	0	0	0	0	44	0	0	0	80026	1	6	6	1	2	25	320164	80100	160062	80000	80100	160000	80000	4408211	3758371	9825507	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	100	80007	6	24	80027	0	0	0	25	80018	6	1	26	23	6	0	5110	1	16	1	1	80038	0	80000	9	9	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	621	1	0	0	0	0	0	0	0	31	0	0	0	80026	1	6	6	1	2	25	320164	80100	160062	80000	80100	160000	80000	4408211	3758373	9826361	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	100	80007	7	23	80025	0	0	1	25	80019	6	1	24	23	7	1	5110	1	16	1	1	80038	1	80000	10	9	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	620	1	0	1	1	0	0	0	0	31	0	0	0	80026	1	6	6	1	0	25	320114	80100	160062	80000	80100	160000	80000	4408200	3758373	9825507	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	100	80006	8	23	80026	0	0	0	29	80019	6	0	26	23	7	1	5110	1	16	1	1	80038	1	80000	9	0	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	620	1	1	0	0	1	0	0	0	31	0	0	0	80026	1	0	6	1	2	25	320164	80100	160014	80000	80100	160000	80000	4408201	3758373	9826363	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	100	80006	7	23	80025	0	0	1	25	80019	6	1	25	23	7	0	5110	1	16	1	1	80038	0	80000	9	9	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	621	1	1	1	0	1	0	0	0	31	0	0	0	80026	1	0	6	1	1	25	320162	80100	160064	80000	80100	160000	80000	4408215	3758374	9826377	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	100	80008	7	23	80025	0	0	0	25	80019	6	1	7	23	6	1	5110	1	16	1	1	80038	0	80000	9	9	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	621	1	0	1	0	0	0	0	0	6	0	0	0	80026	0	6	6	1	6	25	320114	80100	160012	80000	80100	160000	80000	4408211	3758377	9826363	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	100	80007	6	26	80027	0	1	0	9	80019	6	0	26	23	6	1	5110	1	16	1	1	80038	0	80000	9	9	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	621	1	0	1	1	0	0	0	0	7	0	0	0	80026	1	0	6	1	4	25	320164	80100	160062	80000	80242	160000	80000	4408211	3758361	9826371	80022	80041	80041	49924	0	3	49999	320100	200	80131	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	100	80006	8	24	80029	0	0	0	6	80000	0	1	25	24	7	1	5110	1	16	1	1	80038	0	80000	9	0	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	621	1	1	1	1	0	0	0	0	31	0	0	0	80026	0	6	6	1	6	25	320164	80100	160014	80000	80100	160000	80000	4408211	3758373	9826361	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	100	80007	7	23	80025	0	0	0	7	80019	6	1	7	23	7	0	5110	1	16	1	1	80038	0	80000	0	9	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	620	1	1	0	1	0	0	0	0	31	0	0	1	80026	1	0	6	1	9	25	320114	80100	160014	80000	80100	160000	80000	4408206	3758373	9826925	80022	80041	80041	49924	22	3	49999	320100	200	80000	160000	200	160266	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	100	80008	7	0	80006	0	1	0	28	80000	6	1	7	23	7	0	5110	1	16	1	1	80038	1	80000	9	0	80000	160000	80100	80042	80042	80042	80042	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	24	3a	3f	43	46	49	4c	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240025	80041	621	0	0	0	0	0	0	1	0	0	20	0	0	0	0	80026	1	0	0	0	0	4	25	320050	80010	160032	80000	80010	160000	80000	4407696	3758361	9825519	1	80022	0	80041	80041	49947	0	0	3	50022	320530	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	14	0	80013	0	0	0	13	80011	6	1	10	18	0	0	0	5020	8	16	9	8	80038	0	80000	9	6	80000	160000	80010	80042	80042	80181	80042	80042
240024	80041	620	0	0	0	0	0	1	0	0	0	19	0	0	0	0	80026	1	6	6	0	0	0	25	320042	80010	160000	80000	80010	160000	80000	4407696	3761905	9826742	1	80022	0	80041	80041	49947	0	21	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	0	80014	0	0	0	14	80013	0	1	10	14	0	0	0	5020	7	15	8	6	80038	0	80000	12	6	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	644	0	0	0	0	0	0	0	0	0	19	0	0	0	0	80026	1	6	6	0	0	4	67	320050	80010	160040	80000	80010	160000	80000	4407689	3758376	9825493	1	80128	0	80041	80041	49947	0	0	3	50104	320010	20	80000	160000	20	160000	160260	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	16	0	80010	0	0	0	16	80013	0	0	10	0	0	0	0	5020	8	15	7	8	80038	1	80094	9	6	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	643	0	0	0	0	0	0	0	1	0	19	0	0	0	0	80026	1	6	6	0	0	0	25	320048	80010	160040	80000	80010	160000	80000	4407696	3758372	9825697	1	80346	0	80041	80041	49947	0	0	3	50022	320010	20	80000	160261	20	160782	160797	80355	80347	3	1	80021	10	9	10	10	80000	80000	0	10	80270	0	0	0	80286	2	0	0	1502	80000	6	0	10	0	0	0	0	5020	7	35	7	9	80366	1	80188	9	9	80000	160000	80010	80491	80478	80372	80717	80489
240024	80482	646	0	0	1	1	0	0	1	0	0	28	0	0	0	0	80026	1	6	6	0	0	0	25	320050	80010	160040	80000	80010	160000	80000	4407690	3758361	9825125	1	80022	0	80041	80041	49947	0	0	3	50022	320010	20	80000	160000	20	160266	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	14	0	80000	0	0	0	14	80014	6	1	12	18	0	0	0	5047	8	15	7	8	80038	1	80000	10	6	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	643	0	0	0	0	0	0	0	0	0	132	0	0	0	0	80026	1	6	6	0	0	0	25	320042	80010	160040	80000	80010	160000	80000	4407696	3758376	9825695	1	80022	0	80041	80190	49947	0	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	14	0	80013	0	0	0	0	80013	6	1	0	14	0	0	0	5020	8	15	8	6	80038	1	80000	9	6	80000	160000	80010	80042	80042	80042	80042	80042
240024	80181	643	0	0	0	0	0	0	0	1	0	0	0	0	0	0	80026	1	6	6	0	0	0	25	320050	80010	160040	80000	80010	160000	80000	4407696	3758374	9825509	1	80022	0	80041	80041	49947	0	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80087	0	14	0	80014	0	1	0	14	80014	0	1	10	22	0	0	0	5020	8	15	7	8	80038	1	80000	9	9	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	643	0	0	0	0	0	1	1	0	0	32	0	0	0	0	80026	1	6	6	0	0	2	25	320074	80105	160062	80000	80010	160000	80000	4407696	3758374	9827214	1	80022	0	80041	80041	49947	0	0	3	50022	320010	20	80146	160000	20	160256	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	14	0	80014	0	1	0	14	80009	0	1	10	18	0	0	0	5020	5	15	8	7	80038	0	80000	6	6	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	643	0	0	0	0	0	0	0	0	0	31	0	0	1	0	80026	1	6	0	0	0	0	25	320048	80010	160000	80000	80010	160000	80000	4409857	3758361	9825511	1	80452	0	80041	80041	49947	0	0	3	50022	320010	20	80000	160270	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	0	80014	0	0	0	14	80013	6	1	10	14	0	9	0	5020	5	15	8	7	80038	1	80093	9	7	80000	160000	80010	80042	80042	80042	80042	80042
240024	80182	643	0	0	0	0	0	0	1	0	0	20	0	0	0	0	80026	1	0	6	0	0	10	25	320040	80010	160000	80000	80010	160000	80000	4407689	3758376	9825139	1	80022	0	80041	80041	49947	0	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	0	80009	0	0	0	14	80014	6	0	10	18	0	0	0	5040	8	15	8	8	80038	1	80000	9	0	80000	160000	80010	80042	80042	80042	80042	80182

LD2 (multiple, post-index, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations