Firestorm: LD2 (multiple, post-index, 8H) measurements

Code:

  ld2 { v0.8h, v1.8h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.004

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
64005	28951	232	0	23	0	1	20	0	0	1	0	0	6	0	1	0	4764	28626	0	0	2	16805	5004	1000	2004	2000	1000	2000	2000	5000	10000	23814	0	22801	0	28791	28870	3	10	5000	2000	2000	3000	4000	28709	28882	1	1	61001	1000	1000	1	2000	0	6	2002	0	0	2	2004	4	2	4	0	0	0	13050	9413	6929	3161	9	58	19824	3248	3823	31	58	55	28360	1000	15849	12803	14012	2000	2000	1000	28862	28854	28856	28922	28892
64004	28948	231	0	19	0	0	22	0	0	0	0	0	4	0	0	0	4777	28442	0	2	0	16632	5004	1000	2004	2000	1000	2000	2000	5000	10000	23808	3	22847	0	28778	28963	3	10	5000	2000	2000	3000	4000	28747	28805	1	1	61001	1000	1000	0	2000	0	4	2002	0	0	2	2004	2	0	4	0	0	0	13201	9435	6904	3165	10	54	19876	3299	3822	26	58	50	28350	1000	15639	12708	13808	2000	2000	1000	28787	28918	28812	28870	28808
64004	28953	231	0	17	0	0	16	0	0	0	0	0	4	0	1	0	4698	28512	0	0	0	16734	5006	1000	2004	2000	1000	2000	2000	5000	10000	23807	5	22846	0	28733	28747	3	10	5000	2000	2000	3000	4000	28622	28717	1	1	61001	1000	1000	0	2000	0	4	2000	0	0	0	2000	0	0	4	0	0	0	13137	9251	6927	3097	7	51	19881	3260	3803	25	54	48	28208	1000	15602	12748	14015	2000	2000	1000	28782	28782	28939	28800	28833
64004	28816	231	0	18	0	0	19	0	0	0	0	0	0	0	0	0	4837	28566	0	2	0	16686	5006	1000	2006	2000	1000	2000	2000	5000	10000	23850	15	22853	0	28691	28817	3	10	5000	2000	2000	3000	4000	28785	28928	1	1	61001	1000	1000	0	2000	0	4	2002	0	0	0	2000	4	2	6	0	0	0	13298	9611	6970	3121	7	57	19979	3304	3824	23	65	56	28343	1000	15849	12682	13961	2000	2000	1000	28827	28904	29008	28989	28968
64004	28811	232	0	23	0	0	18	0	0	0	0	0	4	0	0	0	4820	28604	0	2	0	16761	5006	1000	2000	2000	1000	2000	2000	5000	10000	23888	2	22925	0	28677	28952	3	10	5000	2000	2000	3000	4000	28774	28730	1	1	61001	1000	1000	0	2000	0	4	2002	0	0	2	2002	4	2	4	0	0	0	13266	9526	6937	3210	9	60	19883	3238	3822	22	55	56	28356	1000	15850	12704	13755	2000	2000	1000	28816	28916	28918	28888	28861
64004	28793	232	0	17	0	0	18	0	0	0	0	0	4	0	0	0	4658	28564	0	0	0	16738	5006	1000	2004	2000	1000	2000	2000	5000	10000	23812	14	22898	0	28686	28925	3	10	5000	2000	2000	3000	4000	28849	28752	1	1	61001	1000	1000	1	2000	0	4	2002	0	0	4	2000	4	2	4	0	0	0	13183	9486	6992	3205	6	61	19707	3232	3813	16	46	52	28309	1000	15791	12803	13929	2000	2000	1000	28949	28858	28948	28965	28735
64004	28822	232	0	24	0	0	20	0	0	0	0	0	5	0	0	0	4612	28522	0	2	0	16723	5006	1000	2000	2000	1000	2000	2000	5000	10000	23884	4	22819	0	28656	28921	3	10	5000	2000	2000	3000	4000	28815	28863	1	1	61001	1000	1000	1	2000	0	4	2002	0	0	2	2000	2	0	0	0	0	0	13232	9511	6937	3143	5	58	19841	3275	3819	17	52	57	28403	1000	15620	12795	14018	2000	2000	1000	28958	28880	28873	28875	28980
64004	28934	232	0	16	0	0	16	0	0	0	0	0	0	0	0	0	4851	28467	0	0	0	16713	5000	1000	2006	2000	1000	2000	2000	5000	10000	23806	0	22870	0	28665	28873	3	10	5000	2000	2000	3000	4000	28750	28687	1	1	61001	1000	1000	0	2000	0	0	2000	0	0	0	2000	4	0	0	0	0	0	13188	9501	7005	3152	13	53	19833	3277	3821	16	53	51	28235	1000	15827	12737	13691	2000	2000	1000	28889	28914	28859	28881	28910
64004	28756	231	0	12	0	0	22	0	0	0	0	0	4	0	0	0	4750	28580	2	0	2	16727	5006	1000	2006	2000	1000	2000	2000	5000	10000	23870	0	22877	0	28725	28869	3	10	5000	2000	2000	3000	4000	28902	28757	1	1	61001	1000	1000	0	2000	0	4	2000	0	0	2	2000	3	6	4	0	0	0	13151	9430	6964	3135	7	63	19992	3168	3819	9	53	51	28298	1000	15738	12825	13784	2000	2000	1000	28849	28992	28859	28905	28964
64004	29009	232	0	16	0	0	16	0	0	0	0	0	0	0	0	0	4670	28632	0	2	2	16700	5006	1000	2004	2000	1000	2000	2000	5000	10000	23844	0	22790	0	28731	28850	3	10	5000	2000	2000	3000	4000	28756	28811	1	1	61001	1000	1000	0	2000	0	4	2000	0	0	4	2002	0	0	0	0	0	0	13171	9568	6938	3143	6	59	19904	3166	3817	28	54	53	28300	1000	15522	12501	13854	2000	2000	1000	28877	28829	28937	28878	28874

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.8h, v1.8h }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0055

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5e	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	7a	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80205	140057	1125	1	1	2	1	0	0	0	0	4	0	0	0	0	140037	127260	129671	25	100103	50100	30003	20002	40100	30000	20000	16086070	6692356	12182693	0	1	140031	140035	140055	129509	3	129940	90100	0	30293	20000	30093	60200	30000	50000	140035	140052	2	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	0	20002	2	0	2	0	0	0	3210	0	1	16	1	1	139775	50000	0	10	14	20000	20000	50100	140036	140036	140036	140058	140058
80204	140147	1125	0	0	0	0	0	0	0	0	17	0	0	0	0	140040	127304	129692	25	100103	50100	30003	20000	40100	30000	20000	16078534	6692260	12182871	0	0	140011	140057	140055	129509	3	129938	90100	0	30200	20000	30000	60200	30000	50000	140055	140087	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20006	0	2	17708	20010	2	0	2	0	0	0	3373	0	1	24	1	2	139855	50074	14	10	14	20000	20000	50100	140879	140886	140794	141051	140899
80204	140783	1132	0	0	0	1	0	0	1	0	2	352	0	0	1	140045	124980	129728	50	100103	50100	30007	20002	40220	30000	20000	16084460	6692260	12182693	0	0	140031	140153	140135	129514	3	129938	90360	0	30293	20000	30000	60386	30000	50000	140151	140114	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	0	20000	0	0	0	20000	2	0	2	0	0	0	3210	0	1	16	1	2	139796	50010	10	10	10	20000	20000	50100	140056	140056	140159	140058	140057
80204	140140	1086	0	1	0	0	0	0	0	0	0	88	0	0	1	140040	127297	129691	52	100103	50110	30003	20000	40220	30000	20050	16078998	6694806	12182693	0	0	140107	140142	140055	129538	3	129940	90100	0	30200	20000	30093	60200	30093	50000	140139	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	2	20000	0	0	2445	20002	2	0	2	0	0	0	3210	0	1	16	1	1	139875	50000	16	10	14	20000	20000	50100	140056	140056	140056	140056	140056
80204	140055	1085	0	0	0	0	0	0	0	0	14	0	0	0	1	140036	127304	129690	25	100103	50100	30003	20000	40100	30000	20000	16079114	6692260	12182693	0	0	140031	140055	140058	129509	3	129938	90100	0	30200	20000	30000	60200	30000	50000	140055	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	0	20000	2	0	2	0	0	0	3210	0	1	16	2	1	139795	50011	14	10	14	20000	20000	50100	140152	140056	140056	140114	140052
80204	140506	1127	0	1	0	0	0	0	1	0	2	88	0	0	1	140041	127297	129690	51	100103	50110	30003	20002	40100	30000	20050	16076640	6694126	12181242	0	0	140029	140140	140057	129509	3	129994	90362	0	30200	20062	30000	60386	30000	50000	140131	140051	2	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20002	0	0	0	20000	0	0	0	0	0	0	3210	0	1	16	1	1	139862	50010	14	10	14	20000	20000	50100	140153	140056	140146	140056	140056
80204	140056	1086	0	1	0	0	0	0	1	0	2	88	0	0	2	140136	127297	129737	50	100103	50112	30000	20000	40220	30000	20050	16078998	6694614	12182693	0	0	140031	140055	140055	129512	3	129965	90360	0	30200	20000	30000	60386	30000	50155	140055	140142	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	0	20000	2	0	2	0	0	0	3210	0	1	16	1	1	139791	50000	14	10	14	20000	20000	50100	140057	140052	140056	140056	140056
80204	140051	1086	0	0	0	0	0	0	0	0	2	0	0	0	1	140036	127297	129690	25	100103	50100	30003	20000	40100	30000	20000	16079222	6692260	12182693	0	0	140031	140058	140055	129509	3	129934	90100	0	30200	20000	30000	60200	30000	50000	140055	140152	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	6	20000	2	0	2	0	0	0	3210	25	1	16	1	1	139793	50000	10	6	10	20000	20000	50100	140058	140059	140058	140058	140060
80204	140042	1131	1	0	0	0	0	0	0	1	23	0	0	0	1	140024	127300	129686	50	100103	50112	30003	20002	40100	30000	20000	16084126	6692068	12186860	0	0	140027	140051	140051	129545	3	129989	90100	0	30200	20000	30000	60200	33162	50000	140051	140226	1	1	50201	100	99	100	40100	10000	10000	1	100	20004	2	2	20004	1	0	5	20000	2	2	2	2	0	0	3210	0	1	24	1	1	139798	50000	14	10	10	20000	20000	50100	140062	140044	140157	140159	140058
80204	140057	1135	1	1	0	1	0	0	0	0	148	0	0	0	1	140040	127305	129690	25	100103	50111	30007	20000	40100	30000	20050	16078998	6695046	12182693	0	0	140109	140051	140150	129533	3	129934	90100	0	30200	20000	30000	60386	30000	50155	140422	140057	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	1	0	6	20000	2	0	2	0	0	0	3210	0	2	32	1	1	139791	50000	10	6	10	20000	20000	50100	140048	140052	140036	140040	140138

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80025	140048	1125	0	0	0	0	0	0	0	0	0	2	0	0	1	140036	127297	129686	25	100013	50010	30003	20000	40010	30000	20000	16077904	6691290	12182517	0	140027	0	140054	140051	129580	3	130020	90010	30020	20000	30000	60578	30000	50000	140051	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	20000	0	2	0	0	3140	0	2	10	16	8	13	139791	50000	10	6	10	20000	20000	50010	140052	140056	140052	140052	140048
80024	140035	1125	0	0	0	0	0	0	0	0	0	5	0	0	1	140036	127302	129686	25	100013	50010	30003	20000	40010	30090	20000	16076010	6692068	12182517	0	140011	0	140051	140051	129595	3	130008	90010	30020	20062	30000	60020	30000	50000	140035	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	20000	2	2	0	0	3168	0	5	12	16	12	13	139791	50000	0	6	0	20000	20000	50010	140052	140048	140052	140055	140055
80024	140054	1124	0	0	0	0	0	0	0	0	0	5	0	0	1	140036	127300	129690	25	100010	50010	30003	20000	40010	30000	20000	16078016	6692068	12187126	0	140013	0	140131	140047	129595	3	130024	90010	30020	20000	30000	60020	30000	50000	140035	140035	1	1	50021	10	9	10	40010	10000	10000	1	10	20000	0	2	20000	0	0	3	20000	2	2	0	0	3140	0	0	11	16	12	12	139793	50000	10	6	10	20000	20000	50010	140052	140052	140036	140053	140052
80024	140144	1125	0	0	0	0	0	0	0	0	0	3	0	0	1	140036	127306	129686	25	100013	50010	30003	20000	40010	30000	20000	16077904	6692212	12182517	0	140046	0	140051	140054	129595	3	130024	90010	30020	20000	30000	60020	30000	50000	140051	140146	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	20000	0	2	0	0	3140	0	0	14	16	11	12	139792	50000	10	6	11	20000	20000	50010	140052	140052	140054	140048	140052
80024	140051	1124	0	0	0	0	0	0	0	0	0	2	0	0	1	140036	127300	129686	25	100013	50010	30003	20000	40010	30000	20000	16077904	6692116	12182517	0	140030	0	140047	140035	129579	3	130026	90010	30020	20000	30000	60020	30000	50000	140051	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	20000	2	2	0	0	3140	0	0	14	16	9	12	139791	50000	6	10	0	20000	20000	50010	140052	140053	140052	140052	140036
80024	140035	1125	0	0	0	0	0	0	0	0	0	3	0	0	0	140036	127297	129687	25	100013	50010	30003	20000	40010	30000	20000	16076010	6692068	12182689	0	140027	0	140051	140052	129595	3	130027	90010	30020	20000	30000	60392	30093	50000	140047	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	0	20000	0	0	0	20000	2	2	0	0	3140	0	0	12	16	14	15	139792	50000	10	10	10	20000	20000	50010	140036	140052	140052	140052	140052
80024	140051	1125	0	0	0	0	0	0	0	0	0	8	0	0	1	140036	128672	129670	25	100013	50010	30003	20000	40010	30000	20000	16077904	6692068	12182517	0	140023	0	140051	140051	129595	3	130020	90010	30020	20000	30000	60020	30000	50000	140047	140050	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	20000	2	2	0	0	3140	0	0	10	24	10	13	139791	50000	10	10	11	20000	20000	50010	140048	140048	140052	140052	140052
80024	140047	1124	0	0	0	0	0	0	0	0	0	5	0	0	1	140039	127300	129687	25	100013	50010	30003	20000	40010	30000	20000	16077904	6691290	12182517	0	140012	0	140035	140051	129595	3	130027	90010	30020	20000	30000	60020	30000	50000	140051	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	1	0	2550	20000	2	0	0	0	3140	0	0	13	16	10	13	139791	50000	10	6	13	20000	20000	50010	140048	140052	140052	140053	140054
80024	140051	1125	0	0	0	0	0	0	0	0	0	5	0	0	1	140036	127300	129686	25	100013	50010	30003	20000	40010	30000	20000	16077904	6692068	12181422	0	140027	0	140051	140051	129579	3	130024	90010	30020	20000	30000	60020	30000	50000	140051	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	1	0	0	20000	2	2	0	0	3140	0	0	13	24	10	13	139863	50000	15	10	11	20000	20000	50010	140052	140185	140048	140141	140155
80024	140049	1126	0	0	0	0	1	1	0	1	0	134	176	0	1	140020	125112	129800	129	100045	50040	30016	20006	40250	30270	20100	16091950	6698592	12194541	3	140245	0	140232	140421	129727	43	130178	90790	30392	20186	30186	60206	30279	50465	140238	140499	3	1	50021	10	9	10	40010	10000	10000	0	10	20006	2	2	20010	0	2	7568	20008	2	2	0	0	3225	32	0	11	38	13	14	139873	50010	14	10	14	20000	20000	50010	140153	140057	140056	140146	140063

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.8h, v1.8h }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0f	18	19	1e	1f	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80205	140057	1085	1	1	0	0	0	0	4	0	2	140059	127306	129692	25	100106	50100	30006	20000	40100	30000	20050	16079230	6692500	12182871	0	140033	140058	140057	129511	3	129989	90100	30200	20000	30000	60200	30000	50000	140057	140053	2	1	50201	100	99	100	40100	10000	10000	0	100	20004	2	2	20002	0	0	2	20000	2	2	2	2	1	0	0	0	3210	1	16	1	1	139781	50000	9	0	10	20000	20000	50100	140042	140058	140061	140058	140042
80204	140057	1086	1	0	0	0	0	0	4	0	2	140061	127308	129692	25	100106	50100	30006	20000	40100	30000	20000	16079454	6691588	12182871	0	140033	140041	140057	129519	3	129940	90100	30200	20000	30000	60200	30000	50000	140041	140053	1	1	50201	100	99	100	40100	10000	10000	0	100	20002	3	2	20002	0	0	5	20000	2	2	0	2	1	0	0	0	3210	1	16	1	1	139800	50000	10	10	10	20000	20000	50100	140058	140042	140058	140058	140058
80204	140057	1086	1	0	0	0	0	0	4	0	2	140043	127306	129695	25	100103	50100	30006	20000	40100	30000	20000	16079230	6691588	12182960	0	140037	140057	140057	129513	3	129940	90100	30200	20000	30000	60200	30000	50000	140057	140054	1	1	50201	100	99	100	40100	10000	10000	0	100	20002	4	2	20002	0	1	2	20000	2	2	2	2	0	0	0	0	3210	1	24	1	1	139797	50000	11	6	10	20000	20000	50100	140058	140059	140042	140058	140042
80204	140128	1086	1	1	0	1	0	0	4	0	0	140058	127302	129692	25	100106	50100	30006	20006	40342	30090	20000	16085175	6692356	12182960	0	140033	140057	140057	129511	14	129924	90100	30200	20000	30000	60200	30000	50000	140057	140057	1	1	50201	100	99	100	40100	10000	10000	0	100	20002	2	2	20002	0	0	2	20002	2	2	2	2	0	0	0	0	3210	1	16	1	1	139797	50011	10	0	10	20000	20000	50100	140061	140058	140236	140058	140058
80204	140057	1086	1	0	0	0	0	0	4	0	0	140136	127302	129729	25	100106	50100	30006	20000	40220	30000	20000	16079230	6692356	12182871	0	140033	140058	140058	129511	3	129940	90100	30200	20000	30093	60200	30000	50000	140057	140053	1	1	50201	100	99	100	40100	10000	10000	0	100	20003	3	2	20003	1	0	2	20000	2	2	2	2	0	0	0	0	3210	1	16	1	2	139800	50000	10	6	10	20000	20000	50100	140139	140058	140058	140058	140042
80204	140057	1086	1	1	0	0	0	0	4	88	2	140047	127306	129692	51	100106	50100	30010	20000	40100	30000	20000	16079230	6692356	12182871	0	140035	140053	140145	129511	3	129940	90100	30200	20062	30000	60200	30000	50000	140061	140057	1	1	50201	100	99	100	40100	10000	10000	0	100	20003	2	2	20004	0	0	17	20000	2	2	2	2	1	0	0	0	3230	1	16	1	1	139797	50000	10	0	10	20000	20000	50100	140058	140043	140058	140058	140058
80204	140141	1086	1	0	1	1	0	0	134	0	2	140043	127306	129692	25	100106	50100	30006	20000	40100	30092	20050	16085164	6692356	12182871	0	140033	140058	140057	129511	23	129940	90100	30200	20000	30000	60200	30000	50000	140156	140053	2	1	50201	100	99	100	40100	10000	10000	0	100	20002	2	2	20003	0	1	2	20002	0	2	0	2	0	0	0	0	3210	1	16	1	1	139781	50000	15	6	10	20000	20000	50100	140059	140147	140042	140059	140058
80204	140057	1085	1	1	0	0	1	0	4	0	2	140141	127125	129692	25	100106	50100	30006	20000	40100	30000	20000	16079346	6691588	12187122	0	140033	140057	140057	129511	3	129999	90100	30200	20000	30000	60200	30000	50000	140057	140143	1	1	50201	100	99	100	40100	10000	10000	0	100	20003	3	2	20003	0	0	5	20000	2	2	0	2	1	0	0	0	3210	1	16	1	1	139797	50000	10	0	10	20000	20000	50100	140061	140061	140058	140138	140058
80204	140053	1085	1	2	2	0	1	0	10	0	2	140055	127306	129716	25	100103	50100	30010	20000	40100	30000	20000	16079230	6691588	12186059	0	140098	140057	140057	129495	3	129940	90100	30200	20000	30000	60200	30000	50000	140057	140139	1	1	50201	100	99	100	40100	10000	10000	0	100	20002	2	2	20003	0	0	2502	20000	2	2	0	2	1	0	0	0	3239	1	16	1	1	139797	50000	10	0	0	20000	20000	50100	140058	140060	140058	140058	140058
80204	140057	1085	1	1	0	0	1	0	2	0	1	140043	127308	129692	25	100122	50100	30006	20002	40100	30000	20000	16079230	6692356	12182871	0	140033	140057	140148	129511	13	129940	90360	30200	20062	30186	60200	31581	55115	140234	140237	3	1	50201	100	99	100	40100	10000	10000	0	100	20046	5	2	20014	0	3	10192	20008	2	2	2	2	0	0	0	0	3269	2	24	3	4	139869	50070	10	0	10	20000	20000	50100	140313	140338	140236	140338	140200

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0055

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cf	d2	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	df	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80025	140047	1125	0	0	0	0	0	0	0	0	17	0	0	0	1	140036	127300	129687	25	100013	50010	30003	20000	40010	30000	20000	16077904	6692068	12182517	1	140027	140035	140048	129595	3	130024	90010	30020	20000	30000	60020	30000	50000	140051	140035	1	1	50021	10	9	10	40010	10000	10000	1	10	20000	0	0	20000	0	0	3	20000	2	0	2	0	0	3140	0	5	16	0	4	4	0	139787	50000	10	0	6	20000	20000	50010	140052	140036	140036	140048	140532
80024	140580	1128	0	0	0	0	0	0	4	4	687	368	0	0	1	140473	127297	130112	154	100093	50070	30027	20010	40730	30540	20300	16109358	6696142	12187986	1	140072	140488	140052	129596	3	130008	90010	30020	20000	30000	60020	30000	50000	140144	140035	1	1	50021	10	9	10	40010	10000	10000	0	10	20008	1	2	20000	0	0	3	20000	0	0	0	0	0	3140	0	4	16	0	5	5	0	139791	50000	6	6	10	20000	20000	50010	140052	140052	140052	140052	140052
80024	140051	1125	0	0	0	0	0	0	0	0	2	0	0	0	1	140036	128671	129682	25	100013	50010	30003	20000	40010	30000	20000	16078016	6692068	12182517	1	140027	140051	140051	129596	3	130020	90010	30020	20000	30093	60020	30000	50000	140051	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	20000	0	0	2	0	0	3140	0	5	16	0	4	3	0	139791	50000	10	10	10	20000	20000	50010	140055	140052	140052	140052	140053
80024	140051	1124	0	0	0	0	0	0	0	0	5	0	0	0	1	140036	127300	129670	25	100013	50010	30003	20000	40010	30000	20000	16077904	6692068	12182517	0	140011	140035	140035	129598	3	130024	90010	30020	20000	30000	60020	30000	50000	140047	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	3	20000	2	0	2	0	1	3160	0	5	16	0	5	5	0	139791	50000	10	6	0	20000	20000	50010	140149	140054	140053	140054	140052
80024	140051	1124	0	0	0	0	1	0	0	0	2	0	0	0	1	140036	127301	129687	25	100013	50010	30007	20000	40010	30000	20000	16077904	6691924	12194659	0	140027	140035	140051	129595	3	130013	90010	30020	20000	30000	60020	30000	50000	140035	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	1	0	0	20000	2	0	0	0	0	3140	0	4	16	0	5	4	0	139791	50000	10	10	10	20000	20000	50010	140053	140052	140036	140053	140053
80024	140047	1125	0	0	0	0	0	0	0	0	17	0	0	0	1	140039	127300	129687	25	100013	50010	30003	20000	40010	30000	20000	16077904	6692068	12181422	0	140028	140053	140051	129595	3	130024	90010	30020	20000	30000	60020	30000	50000	140149	140051	1	1	50021	10	9	10	40010	10000	10000	1	10	20000	0	2	20000	0	0	0	20000	2	0	2	0	0	3140	0	5	16	0	5	4	0	139791	50000	10	6	10	20000	20000	50010	140036	140052	140052	140052	140052
80024	140051	1125	0	0	0	0	0	0	1	0	17	0	0	0	1	140020	127300	129687	25	100013	50010	30003	20000	40010	30000	20000	16078016	6692068	12182603	0	140027	140035	140051	129595	3	130021	90010	30020	20000	30000	60020	30000	50000	140054	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	1	0	0	20000	0	0	2	0	0	3140	0	5	16	0	5	4	0	139791	50000	0	10	10	20000	20000	50010	140052	140052	140052	140098	140054
80024	140051	1125	0	0	0	0	0	0	0	0	0	0	0	0	0	140020	127297	129686	25	100013	50010	30003	20000	40010	30000	20000	16078020	6692068	12182517	1	140027	140052	140051	129579	3	130024	90010	30020	20000	30000	60020	30000	50000	140047	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	6	20000	2	0	2	0	0	3140	0	5	16	0	5	5	0	139791	50000	6	6	10	20000	20000	50010	140052	140052	140048	140036	140052
80024	140051	1125	0	0	0	0	0	0	0	0	5	0	0	0	1	140036	127301	129686	25	100013	50010	30003	20000	40010	30000	20000	16077904	6692164	12182606	0	140028	140051	140051	129579	3	130024	90010	30020	20000	30000	60020	30000	50000	140052	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	0	20000	1	0	0	20000	2	0	0	0	0	3140	0	4	16	0	4	4	0	139778	50000	10	0	10	20000	20000	50010	140055	140052	140052	140052	140053
80024	140035	1124	0	0	0	0	0	0	0	0	5	0	0	0	1	140036	127302	129687	51	100013	50010	30003	20000	40010	30000	20000	16077904	6692742	12182517	0	140011	140047	140051	129598	3	130024	90010	30020	20000	30000	60020	30000	50000	140051	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	20004	0	2	20000	0	0	0	20000	2	0	2	0	0	3140	0	5	16	0	4	5	0	139791	50000	6	12	11	20000	20000	50010	140052	140053	140053	140052	140053

Test 4: throughput

Count: 8

Code:

  ld2 { v0.8h, v1.8h }, [x6], x8
  ld2 { v0.8h, v1.8h }, [x6], x8
  ld2 { v0.8h, v1.8h }, [x6], x8
  ld2 { v0.8h, v1.8h }, [x6], x8
  ld2 { v0.8h, v1.8h }, [x6], x8
  ld2 { v0.8h, v1.8h }, [x6], x8
  ld2 { v0.8h, v1.8h }, [x6], x8
  ld2 { v0.8h, v1.8h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	67	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320205	80071	599	1	0	0	0	0	0	0	0	64	0	0	0	2	80027	0	0	14	0	25	400154	80100	160000	160000	80100	160000	160000	480499	960920	2081816	0	0	80023	0	80042	80042	0	3	24	400100	200	160000	160000	200	240000	320000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160011	10	40	160032	0	0	0	53	160036	6	1	46	40	10	1	0	0	0	5109	1	17	1	1	80039	0	80000	9	6	160000	160000	80100	80043	80128	80043	80043	80043
320204	80042	620	1	0	0	0	1	0	0	0	10	0	0	0	2	80027	2	14	15	0	25	400152	80100	160048	160000	80100	160000	160108	480499	960917	2081832	0	0	80023	0	80042	80042	0	3	24	400100	200	160000	160000	200	240000	320000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160012	12	40	160021	1	1	0	47	160036	6	1	48	40	0	1	0	0	0	5109	2	17	1	1	80039	0	80000	0	10	160000	160000	80100	80043	80043	80043	80043	80043
320204	80042	620	0	0	0	0	0	0	0	0	54	0	0	0	2	80027	3	0	14	0	25	400148	80154	160010	160000	80100	160000	160000	480499	960030	2081922	0	0	80023	0	80042	80042	0	3	24	400100	200	160000	160000	200	240000	320000	80042	80042	2	1	80201	100	99	100	100	80000	80000	0	100	160011	11	0	160048	0	0	1	10	160037	6	1	22	40	11	0	0	0	0	5125	1	17	1	1	80039	0	80000	9	9	160000	160000	80100	80043	80043	80043	80043	80043
320204	80042	620	0	0	0	0	0	0	0	1	51	0	0	0	1	80027	3	0	14	0	25	400152	80100	160046	160000	80100	160000	160000	480499	960887	2080114	0	0	80023	0	80042	80042	0	3	24	400100	200	160108	160000	200	240000	320000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160012	11	40	160046	0	0	0	11	160036	6	1	30	40	11	1	0	0	0	5109	1	17	1	2	80039	0	80000	9	0	160000	160000	80100	80043	80043	80154	80043	80043
320204	80042	620	1	0	0	0	0	0	0	0	34	0	0	0	2	80027	3	14	14	0	25	400146	80100	160048	160000	80100	160000	160000	480821	960905	2081758	0	0	80023	0	80042	80042	23	3	24	400100	200	160000	160000	200	240000	320000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160010	12	40	160048	0	0	0	48	160037	6	1	46	40	11	1	0	0	0	5223	1	17	1	1	80039	0	80000	9	9	160000	160000	80100	80043	80043	80043	80043	80043
320204	80042	621	1	0	0	1	0	0	0	0	65	0	0	0	2	80027	2	0	0	0	25	400148	80100	160012	160000	80100	160000	160000	480499	960884	2081772	0	0	80023	0	80042	80042	0	3	24	400100	200	160108	160000	200	240000	320000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160011	11	40	160012	0	1	1	47	160036	6	1	10	0	11	1	0	0	0	5109	1	17	2	1	80039	0	80000	0	10	160000	160000	80100	80152	80043	80043	80043	80043
320204	80042	620	1	0	0	0	0	0	0	0	53	0	1	0	2	80137	2	14	14	0	25	400150	80100	160010	160000	80100	160108	160000	480499	960887	2081760	0	0	80023	0	80042	80042	0	3	24	400100	200	160000	160000	200	240000	320000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160116	11	40	160012	1	0	0	47	160000	6	1	47	40	11	0	0	0	0	5109	1	17	1	1	80039	1	80054	10	0	160000	160000	80100	80043	80043	80043	80043	80043
320204	80152	621	1	0	0	0	0	0	0	0	52	0	0	0	2	80027	2	14	15	0	25	400148	80100	160048	160000	80100	160000	160000	480499	960882	2080624	0	0	80023	0	80042	80042	0	3	24	400100	200	160000	160000	200	240000	320000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160011	0	42	160046	0	0	0	29	160029	6	1	48	42	11	0	0	0	0	5109	1	17	1	1	80039	1	80000	9	9	160000	160000	80100	80043	80043	80043	80043	80043
320204	80042	621	1	0	0	1	0	0	0	0	54	0	0	0	2	80027	0	0	14	2	25	400146	80100	160052	160000	80100	160000	160000	480499	960962	2081808	0	0	80023	0	80152	80042	0	3	24	400100	200	160000	160000	200	240000	320000	80042	80042	2	1	80201	100	99	100	100	80000	80000	0	100	160011	11	0	160048	0	0	0	47	160036	6	1	48	40	11	0	0	0	0	5109	1	17	1	1	80039	0	80000	0	9	160000	160000	80100	80043	80043	80043	80043	80153
320204	80042	620	1	0	0	1	0	0	0	0	10	0	0	0	2	80027	2	14	14	0	25	400136	80100	160046	160000	80100	160000	160000	480499	960878	2081772	0	0	80023	0	80042	80042	0	3	24	400100	200	160000	160000	200	240000	320000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160011	12	40	160104	0	0	0	46	160036	6	1	47	40	10	0	0	0	0	5109	2	17	1	1	80039	0	80000	0	9	160000	160000	80100	80043	80043	80043	80043	80043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	67	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	80057	643	1	0	0	0	0	1	1	0	0	79	0	0	2	80027	2	14	14	0	25	400020	80010	160048	160000	80010	160000	160000	480049	960884	2081772	0	0	80023	0	80042	80042	0	3	24	400010	20	160000	160000	20	240000	320000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160010	11	40	160048	0	1	0	48	160036	6	1	47	40	10	3	5019	2	17	2	3	80039	80000	9	9	160000	160000	80010	80043	80043	80043	80043	80043
320024	80042	643	1	0	1	0	1	0	1	0	0	71	0	0	2	80027	2	15	14	0	25	400056	80010	160048	160000	80010	160000	160000	480049	960874	2080126	0	0	80023	0	80042	80042	0	3	24	400010	20	160000	160000	20	240000	320000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160011	12	40	160048	0	1	1	54	160036	6	1	46	40	11	0	5021	1	17	2	1	80039	80000	10	9	160000	160000	80010	80043	80043	80043	80043	80043
320024	80042	643	1	0	0	1	1	0	1	0	0	552	0	0	2	80027	2	15	14	0	25	400056	80010	160048	160000	80010	160000	160000	480049	960874	2081796	0	0	80023	0	80042	80042	0	3	24	400010	20	160000	160000	20	240000	320000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160010	11	40	160046	0	0	0	48	160036	6	1	46	40	10	0	5019	1	17	1	1	80039	80000	9	9	160000	160000	80010	80043	80043	80043	80043	80043
320024	80042	642	1	0	1	0	0	0	1	0	0	55	0	0	3	80027	2	0	14	0	25	400062	80010	160048	160000	80010	160000	160000	480049	960882	2081944	0	0	80023	0	80042	80042	0	3	24	400010	20	160000	160000	20	240000	320000	80042	80042	1	1	80021	10	9	10	10	80000	80000	1	10	160011	11	40	160049	1	3	0	46	160036	6	1	47	40	11	0	5019	2	17	2	1	80039	80000	9	9	160000	160000	80010	80043	80043	80043	80043	80043
320024	80042	642	1	0	1	1	0	0	1	26	4	52	0	0	3	80027	3	13	14	0	25	400062	80010	160046	160000	80010	160108	160000	480049	960887	2081770	0	0	80023	0	80042	80042	0	13	24	400010	20	160000	160000	20	240000	320000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160011	13	40	160048	0	0	2	47	160036	6	1	48	40	10	0	5021	2	17	1	2	80039	80000	9	10	160000	160000	80010	80043	80043	80043	80043	80043
320024	80042	642	1	0	0	1	0	0	1	0	0	93	0	0	3	80027	2	14	14	0	51	400056	80010	160050	160000	80010	160000	160000	480049	960874	2081772	0	0	80023	0	80042	80042	0	3	24	400010	20	160000	160324	20	240000	320000	80042	80153	1	1	80021	10	9	10	10	80000	80000	0	10	160011	11	40	160046	0	0	1	51	160037	6	1	49	40	10	0	5021	1	17	2	2	80039	80000	9	9	160000	160000	80010	80043	80043	80043	80043	80153
320024	80042	643	1	0	1	1	0	0	1	0	0	53	0	0	2	80027	2	14	14	0	25	400054	80010	160052	160000	80010	160000	160000	480049	960874	2081786	0	0	80023	0	80042	80042	0	3	24	400010	20	160108	160000	20	240000	320000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160113	11	40	160047	0	0	1	48	160036	6	1	48	0	11	1	5019	2	17	1	1	80039	80000	9	17	160000	160000	80010	80043	80043	80043	80043	80043
320024	80042	643	1	0	0	0	1	0	1	0	0	64	0	0	3	80027	3	14	14	0	25	400058	80010	160052	160000	80010	160000	160000	480049	960884	2081972	0	0	80023	0	80042	80042	0	3	24	400010	20	160000	160000	20	240000	320000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160011	11	40	160047	0	0	1	47	160036	6	1	47	40	11	1	5019	1	17	1	2	80039	80000	9	9	160000	160000	80010	80043	80043	80043	80043	80043
320024	80042	643	1	0	0	0	1	1	1	0	0	71	0	1	2	80027	1	14	11	0	25	400056	80010	160048	160000	80010	160000	160000	480049	960914	2081934	0	0	80023	0	80162	80042	0	3	24	400010	20	160000	160000	20	240000	320000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160011	11	40	160048	0	0	0	47	160037	6	1	48	40	11	0	5021	2	17	2	1	80039	80000	9	9	160000	160000	80010	80043	80043	80043	80043	80043
320024	80042	643	1	0	0	1	0	0	1	0	1	59	0	0	3	80027	2	14	14	3	25	400058	80010	160052	160000	80010	160000	160000	480049	960888	2081778	0	0	80023	0	80042	80042	0	3	24	400010	20	160000	160000	20	240000	320000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160013	10	40	160047	0	0	0	48	160037	6	1	49	40	11	0	5021	2	17	1	2	80039	80000	9	9	160000	160000	80010	80043	80043	80043	80043	80043

LD2 (multiple, post-index, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations