Firestorm: LD2 (single, B) measurements

Code:

  ld2 { v0.b, v1.b }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.002

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.002

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	0e	0f	1e	22	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	df	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
63005	28482	214	16	14	0	0	2	1	4989	27931	1	1	1	16300	3004	2004	1000	2000	1000	5000	23881	3	22801	28059	28444	3	10	3000	1000	2000	1000	4000	28221	27997	1	1	61001	1000	1000	0	1000	0	3	1003	0	0	1	1001	2	1	3	13812	10288	7083	3385	13	47	19778	3421	3812	16	44	44	2	27988	14879	12574	12982	1000	2000	28537	28406	28219	28521	28292
63004	28362	214	16	13	0	0	3	1	4958	28162	0	1	1	16294	3004	2002	1000	2000	1000	5000	23854	4	22783	28320	28408	3	10	3000	1000	2000	1001	4000	28313	28382	1	1	61001	1000	1000	0	1000	0	2	1000	0	0	3	1000	0	0	3	13600	10227	7223	3368	6	39	19604	3328	3822	14	43	43	2	27978	14710	12975	13493	1000	2000	28173	28113	28176	28218	28341
63004	28297	211	15	12	0	0	2	0	5174	28125	0	0	0	16280	3002	2002	1000	2000	1000	5000	23816	0	22783	28356	28293	3	10	3000	1000	2000	1000	4000	28314	28109	1	1	61001	1000	1000	0	1000	0	2	1000	1	0	0	1001	1	1	0	13576	10111	7053	3387	7	35	19763	3373	3820	17	42	37	2	27944	15191	13025	13312	1000	2000	28396	28360	28372	28401	28554
63004	28503	213	10	12	0	0	2	1	4947	28133	0	1	0	16357	3000	2000	1000	2000	1000	5000	23858	2	22751	28388	28406	3	10	3000	1000	2000	1000	4000	28299	28385	1	1	61001	1000	1000	0	1000	0	2	1001	0	0	1	1000	1	1	3	13947	10256	7227	3410	9	41	19663	3349	3816	12	38	42	3	27988	14326	12634	13086	1000	2000	28251	28278	28218	28229	28228
63004	28472	211	15	11	0	0	4	1	5053	28128	0	0	1	16311	3004	2002	1000	2000	1000	5000	23798	8	22757	28420	28295	3	10	3000	1000	2000	1000	4000	28367	28286	1	1	61001	1000	1000	0	1000	0	2	1006	1	2	3	1003	1	1	2	13600	9999	7106	3393	5	37	19479	3359	3806	9	44	42	2	28001	14273	12658	13565	1000	2000	28456	28351	28344	28517	28339
63004	28277	212	15	14	0	0	7	0	4945	28106	1	1	1	16265	3002	2002	1000	2000	1000	5000	23893	2	22768	28415	28396	3	10	3000	1000	2000	1000	4000	28243	28196	1	1	61001	1000	1000	1	1000	0	2	1003	1	0	0	1000	1	1	3	13573	10353	7065	3400	9	39	19553	3337	3818	12	41	42	2	28062	14502	12973	13422	1000	2000	28193	28154	28255	28376	28244
63004	28352	211	11	12	0	0	4	1	5018	28161	0	1	1	16277	3004	2000	1000	2000	1000	5000	23813	6	22766	28227	28169	3	10	3000	1000	2000	1000	4000	28236	28423	1	1	61001	1000	1000	0	1000	0	0	1000	0	0	6	1000	1	1	3	13917	10164	7169	3408	5	37	19602	3385	3815	11	40	46	3	27980	14314	12668	13511	1000	2000	28291	28520	28411	28462	28381
63004	28318	211	13	16	0	0	4	1	4932	28134	1	0	1	16144	3002	2000	1000	2000	1000	5000	23889	5	22762	28124	28291	3	10	3000	1000	2000	1000	4000	28383	28314	1	1	61001	1000	1000	0	1000	0	2	1001	0	0	1	1003	1	1	3	13795	9939	7243	3379	8	40	19492	3394	3817	20	41	38	2	28051	13982	12569	13635	1000	2000	28182	28449	28593	28307	28195
63004	28296	213	13	15	0	0	4	1	5007	28087	0	0	1	16211	3004	2004	1000	2000	1000	5000	23890	8	22753	28313	28298	3	10	3000	1000	2000	1000	4000	28200	28248	1	1	61001	1000	1000	0	1000	0	0	1001	1	0	3	1003	0	3	0	14055	9997	7085	3398	5	36	19551	3401	3813	12	43	39	3	27892	15043	12688	14001	1000	2000	28242	28258	28264	28320	28429
63004	28530	212	16	12	0	0	0	1	4996	28013	1	1	1	16113	3002	2004	1000	2000	1000	5000	23897	5	22768	28385	28550	3	10	3000	1000	2000	1000	4000	28482	28048	1	1	61001	1000	1000	0	1000	0	2	1000	0	0	1	1000	2	1	2	13688	10227	7202	3422	7	46	19487	3397	3817	11	40	43	2	27977	14807	12319	13655	1000	2000	28223	28347	28293	28233	28327

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.b, v1.b }[1], [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140047	1049	0	0	0	0	0	0	1	0	0	1	0	1	0	0	140698	139707	139338	129353	25	80119	40132	30041	10002	30100	30000	10000	1264328	6707298	20081263	0	140023	0	140048	140047	130545	3	131205	70100	30200	10000	30160	62440	10157	51865	140249	140047	2	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	2	0	10000	1	1	0	0	3402	3	153	2	2	139899	40000	6	6	6	10000	20000	40100	140048	140080	140658	140611	140048
70204	140047	1050	0	1	0	0	0	0	0	0	0	82	0	1	0	0	140032	139431	139338	129353	25	80103	40100	30003	10000	30249	30000	10000	1264328	6693388	20081263	0	140023	0	140047	140047	130544	3	131118	70100	30200	10000	30000	60200	10000	50000	140048	140035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	3210	2	153	2	2	139559	40028	6	6	6	10000	20000	40100	140048	140049	140049	140150	140048
70204	140047	1049	0	0	0	0	0	0	0	0	0	208	0	0	0	0	140020	139433	139338	129341	25	80103	40100	30003	10000	30100	30000	10000	1264328	6693388	20081263	0	140095	0	140047	140047	130543	3	131126	70100	30200	10000	30000	60200	10000	50000	140047	140047	1	1	50201	100	99	100	40100	10000	10000	0	100	10006	0	1	10000	0	0	0	10000	1	1	0	0	3210	2	153	2	2	139559	40000	6	6	6	10000	20000	40100	140048	140036	140048	140048	140048
70204	140047	1049	0	0	0	0	0	0	0	1	0	1	0	1	0	0	140032	139431	139338	129353	25	80103	40100	30003	10000	30100	30000	10049	1264382	6693388	20081263	0	140023	3	140049	140047	130543	3	131126	70100	30200	10000	30158	60200	10000	50000	140047	140047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10001	0	0	0	10000	1	1	0	0	3210	2	153	2	2	139559	40000	6	6	6	10000	20000	40100	140048	140048	140050	140149	140048
70204	140047	1049	0	0	0	0	0	0	0	0	0	1	0	1	0	0	140032	139431	139338	129353	25	80103	40100	30003	10000	30249	30000	10000	1264328	6693388	20081263	0	140023	0	140040	140047	130543	3	131118	70100	30200	10000	30000	60574	10000	50000	140047	140047	2	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	3	0	0	10000	1	1	0	0	3210	2	133	2	2	139680	40000	6	6	6	10000	20000	40100	140048	140048	140048	140048	140048
70204	140047	1049	0	0	0	0	0	0	0	1	0	1	0	1	0	1	140033	139470	139338	129353	25	80103	40100	30007	10000	30100	30000	10049	1265635	6693388	20081263	0	140023	0	140048	140047	130575	3	131118	70100	30200	10000	30000	60200	10000	50266	140048	140036	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	3210	2	133	2	2	139544	40024	0	6	6	10000	20000	40100	140048	140048	140048	140048	140048
70204	140047	1049	0	0	0	0	0	0	0	0	0	1	0	1	0	0	140032	139431	139338	129353	25	80103	40100	30003	10000	30100	30000	10000	1264328	6693388	20081263	0	140031	0	140047	140047	130543	3	131126	70100	30360	10000	30000	60200	10000	50000	140047	140047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	0	0	3210	2	153	2	2	139559	40000	6	6	6	10000	20000	40100	140080	140080	140051	140048	140048
70204	140047	1049	0	0	0	0	0	0	0	0	0	1	0	0	0	0	140032	139431	139338	129353	25	80103	40100	30003	10000	30100	30000	10000	1264328	6693388	20081263	0	140023	0	140047	140047	130572	3	131118	70100	30200	10000	30000	60200	10000	50000	140047	140050	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	4	1	183	10000	1	1	0	0	3210	2	153	2	2	139559	40000	6	0	6	10000	20000	40100	140048	140051	140048	140036	140048
70204	140035	1049	0	0	0	0	0	0	1	0	0	52	88	1	0	0	140032	139431	139325	129353	25	80103	40109	30003	10000	30100	30000	10000	1264328	6693388	20081263	1	140023	0	140047	140047	130543	3	131120	70441	30200	10000	30000	60200	10000	50000	140047	140049	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	0	1	10000	0	0	0	10000	1	1	2	0	3210	2	153	2	2	139559	40000	6	6	6	10000	20000	40100	140048	140052	140048	140144	140048
70204	140035	1049	0	0	0	0	0	1	1	0	0	13	0	1	0	0	140032	139431	139338	129353	25	80103	40100	30003	10000	30100	30000	10000	1264328	6693388	20081263	0	140023	0	140047	140047	130543	3	131126	70100	30200	10000	30000	60200	10000	50000	140047	140047	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	3210	2	153	2	2	139559	40000	6	6	6	10000	20000	40100	140054	140050	140048	140048	140048

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0049

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140053	1049	0	0	1	1	0	0	1	0	1	0	0	140035	139491	139343	129356	25	80013	40010	30003	10000	30010	30000	10000	1264771	6693388	20081263	0	0	140026	140050	140050	130568	3	131175	70010	30020	10000	30000	60020	10000	50000	140050	140096	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	4	3	10000	1	0	1	0	0	3190	0	0	0	5	121	0	0	0	2	4	139862	40000	9	6	9	10000	20000	40010	140051	140051	140151	140051	140036
70024	140047	1049	0	0	0	0	0	0	1	0	0	0	0	140035	139491	139325	129356	25	80010	40010	30000	10000	30010	30000	10000	1264771	6693869	20079451	0	0	140011	140035	140050	130553	3	131175	70010	30020	10000	30000	60020	10000	50000	140050	140035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	0	0	1	0	0	3140	0	0	0	2	121	0	0	0	2	4	139574	40000	0	6	9	10000	20000	40010	140036	140051	140036	140051	140048
70024	140047	1049	0	0	0	0	0	0	0	0	0	0	0	140035	139446	139343	129341	25	80013	40010	30003	10000	30010	30000	10000	1264771	6693535	20081263	0	0	140011	140050	140035	130565	3	131161	70010	30020	10000	30000	60020	10000	50000	140050	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	0	1	0	0	3140	0	0	0	2	121	0	0	0	2	4	139572	40000	9	6	0	10000	20000	40010	140048	140048	140036	140051	140051
70024	140035	1048	0	0	0	1	0	0	1	0	1	0	0	140035	139448	139373	129342	25	80010	40010	30003	10000	30010	30000	10000	1264771	6692791	20079451	1	0	140026	140035	140050	130568	3	131161	70010	30020	10000	30000	60020	10000	50000	140050	140035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	1	0	10000	0	0	0	0	0	3140	0	0	0	2	121	0	0	0	2	2	139569	40000	0	0	6	10000	20000	40010	140086	140051	140048	140110	140083
70024	140050	1049	0	0	0	0	0	0	0	0	0	0	0	140035	139492	139325	129356	25	80010	40010	30003	10000	30010	30000	10000	1264771	6693535	20079451	0	0	140023	140035	140047	130568	3	131175	70010	30020	10000	30000	60388	10000	50000	140047	140058	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	3	10000	1	0	1	0	0	3140	0	0	0	2	120	0	0	0	3	2	139572	40000	9	0	9	10000	20000	40010	140036	140036	140051	140051	140051
70024	140047	1049	0	0	0	0	0	0	1	0	0	0	0	140020	139491	139344	129356	25	80013	40010	30000	10002	30010	30000	10000	1265122	6692887	20081263	0	0	140026	140035	140047	130568	3	131175	70010	30020	10000	30000	60020	10000	50000	140050	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	5385	10000	1	0	1	0	0	3168	0	0	0	2	121	0	0	0	3	5	139864	40000	9	6	9	10000	20000	40010	140051	140037	140051	140154	140051
70024	140035	1049	0	0	0	0	0	0	0	0	1	0	0	140035	139446	139343	129356	25	80010	40010	30003	10000	30010	30000	10000	1264719	6693535	20081697	0	0	140026	140050	140047	130568	3	131175	70010	30020	10000	30000	60388	10000	50000	140050	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	0	1	0	0	3140	0	0	0	2	121	0	0	0	4	3	139557	40000	9	9	0	10000	20000	40010	140051	140051	140051	140051	140036
70024	140035	1080	0	0	0	0	0	0	1	0	1	0	0	140020	139491	139325	129356	25	80013	40010	30003	10000	30010	30000	10000	1264748	6692791	20081697	0	0	140011	140050	140035	130568	3	131175	70010	30020	10000	30000	60020	10000	50000	140050	140035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	1	0	10000	1	0	0	0	0	3140	0	0	0	2	121	0	0	0	2	2	139557	40000	9	9	9	10000	20000	40010	140051	140051	140036	140051	140036
70024	140035	1049	0	0	0	0	0	0	1	0	0	0	0	140035	139487	139325	129356	25	80010	40010	30000	10000	30010	30000	10000	1264771	6693535	20081263	0	0	140011	140047	140047	130565	3	131173	70010	30020	10000	30000	60020	10000	50000	140050	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	0	0	0	0	3140	0	0	0	2	120	0	0	0	3	2	139570	40000	0	9	9	10000	20000	40010	140036	140051	140051	140051	140081
70024	140035	1048	0	0	1	0	0	0	0	0	0	0	0	140035	139446	139338	129353	58	80010	40010	30003	10000	30010	30000	10000	1264719	6693583	20081263	0	0	140023	140050	140050	130553	3	131175	70010	30020	10000	30000	60020	10000	50000	140047	140035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	0	0	0	0	3140	0	0	0	2	17	0	0	0	3	2	139572	40000	9	0	9	10000	20000	40010	140036	140048	140051	140048	140051

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.b, v1.b }[1], [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0458

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	22	23	24	3a	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140887	1054	1	0	0	1	0	0	0	7	1	0	0	1	140670	139866	139974	129987	25	80106	40100	30006	10000	30100	30000	10000	1269962	6713069	20172574	0	140434	0	140682	140685	130964	39	131777	70100	30200	10000	30000	60200	10000	50000	140458	140458	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10001	0	1	1	10000	1	1	1	1	0	0	0	3210	3	129	1	1	140192	40000	13	10	13	10000	20000	40100	140459	140686	140686	140459	140683
70204	140682	1052	1	1	0	0	0	1	0	1	1	0	0	0	140443	139866	139974	129762	25	80106	40100	30003	10000	30100	30000	10000	1268087	6723821	20172574	0	140661	0	140685	140685	131190	3	131777	70100	30200	10064	30000	60200	10000	50000	140458	140458	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10002	0	2	1	10000	0	1	0	1	1	0	0	3210	1	129	1	1	140195	40000	13	13	0	10000	20000	40100	140459	140683	140683	140686	140683
70204	140685	1088	1	2	0	1	0	0	0	2	0	0	0	0	140670	140331	139975	129775	25	80106	40100	30012	10000	30100	30000	10000	1268087	6723821	20172574	0	140434	0	140458	140682	130964	3	131553	70100	30200	10000	30000	60200	10000	50000	140682	140746	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10001	2	1	1	10000	1	1	1	1	1	0	0	3210	1	129	1	1	140195	40000	10	10	10	10000	20000	40100	140683	140686	140459	140459	140686
70204	140458	1053	1	1	0	0	0	0	0	2	0	0	0	0	140670	140279	139974	129987	25	80106	40100	30006	10000	30100	30000	10000	1268105	6723965	20173015	1	140658	0	140458	140685	131190	3	131780	70100	30200	10000	30000	60200	10000	50000	140458	140682	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	2	1	10002	1	1	1	10000	1	1	1	1	0	0	0	3210	1	129	1	1	140195	40000	13	0	13	10000	20000	40100	140683	140459	140683	140683	140686
70204	140458	1051	1	1	0	0	1	1	0	2	1	0	0	1	140670	140279	139974	129987	25	80106	40100	30003	10000	30100	30000	10000	1268087	6723965	20172574	1	140434	0	140458	140458	131187	3	131777	70100	30200	10000	30000	60200	10000	50000	140458	140711	1	1	50201	100	99	100	40100	10000	10000	1	100	10003	1	1	10002	0	0	4	10000	1	1	1	1	0	0	0	3210	1	17	1	1	140194	40000	13	13	13	10000	20000	40100	140686	140686	140459	140686	140686
70204	140458	1054	1	1	0	1	0	0	0	2	0	0	0	0	140675	140276	139972	129987	25	80106	40100	30006	10000	30100	30000	10000	1269962	6723965	20172574	1	140661	0	140685	140685	130964	3	131780	70100	30200	10000	30000	60200	10000	50000	140685	140682	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	0	10002	0	1	4	10000	0	1	1	1	0	0	0	3210	1	129	1	1	140195	40000	0	10	13	10000	20000	40100	140459	140686	140686	140459	140686
70204	140682	1052	1	1	0	1	0	0	0	1	0	0	0	0	140443	140276	139974	129985	25	80103	40100	30006	10000	30100	30000	10000	1269946	6723821	20172574	1	140661	0	140682	140685	130964	3	131553	70100	30200	10000	30000	60200	10000	50000	140682	140682	1	1	50202	100	99	100	40100	10000	10000	1	100	10002	3	0	10001	0	1	1	10000	1	1	1	1	1	0	0	3210	1	129	1	1	139969	40000	13	13	0	10000	20000	40100	140686	140686	140459	140686	140683
70204	140682	1054	1	1	0	1	0	0	0	7	0	0	0	0	140443	140279	139974	129763	25	80106	40100	30003	10000	30100	30000	10000	1269962	6713069	20172574	0	140661	0	140458	140685	131190	3	131777	70100	30389	10000	30000	60200	10000	50000	140685	140682	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	2	0	10001	58	1	1	10000	1	1	1	1	1	0	0	3210	1	129	1	1	139969	40000	0	0	13	10000	20000	40100	140459	140686	140459	140683	140459
70204	140685	1053	1	1	0	0	0	1	0	2	1	0	0	0	140675	140279	139972	129985	25	80106	40100	30006	10000	30100	30000	10000	1269962	6723965	20140295	0	140658	0	140685	140458	131190	3	131780	70100	30200	10000	30000	60200	10000	50000	140458	140682	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10001	0	1	1	10000	1	1	1	1	0	0	0	3210	1	129	1	1	140195	40000	13	0	13	10000	20000	40100	140686	140686	140687	140459	140692
70204	140458	1052	1	0	0	1	1	0	0	2	1	0	0	0	140443	140279	139974	129987	25	80103	40100	30006	10000	30100	30000	10000	1269962	6723965	20140295	1	140434	0	140458	140685	131190	3	131780	70100	30200	10000	30000	60200	10000	50000	140458	140682	1	1	50201	100	99	100	40100	10000	10000	1	100	10001	2	0	10002	0	2	1	10000	1	1	1	1	0	0	0	3210	1	129	1	1	140195	40000	13	13	13	10000	20000	40100	140459	140459	140686	140459	140459

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0301

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	18	19	1e	1f	22	23	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140594	1052	0	0	0	0	0	0	0	0	0	0	1	0	140244	139862	139753	129564	25	80010	40010	30003	10000	30010	30000	10000	1266650	6703564	20141197	1	1	140440	0	140259	140259	130776	3	131162	70010	30020	10000	30000	60394	10000	50000	140464	140069	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3140	0	0	5	121	5	4	139780	40000	9	6	9	10000	20000	40010	140260	140465	140037	140260	140260
70024	140259	1052	0	0	0	0	0	0	0	0	1	0	0	0	140244	139488	139753	129564	25	80010	40010	30000	10000	30010	30000	10000	1264728	6692839	20111784	0	0	140235	0	140259	140036	130554	3	131383	70010	30020	10000	30000	60020	10000	50000	140464	140036	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3140	3	0	4	121	5	4	139984	40000	9	0	6	10000	20000	40010	140037	140260	140037	140465	140260
70024	140096	1052	0	0	0	0	0	0	0	0	1	0	1	0	140449	139488	139551	129564	25	80013	40010	30003	10000	30010	30000	10000	1268532	6713366	20079595	0	0	140235	0	140464	140036	130554	3	131162	70010	30020	10000	30000	60020	10000	50000	140464	140036	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3140	0	0	4	120	4	5	139558	40000	9	9	9	10000	20000	40010	140260	140260	140465	140260	140465
70024	140259	1052	0	0	0	0	0	0	0	0	1	0	1	0	140244	139488	139753	129564	25	80010	40015	30003	10000	30010	30000	10000	1266650	6713366	20111784	0	1	140012	0	140036	140464	130554	3	131162	70010	30020	10000	30000	60020	10000	50000	140464	140464	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	0	10000	0	0	1	0	0	3140	0	0	6	122	4	4	139780	40000	0	0	9	10000	20000	40010	140465	140037	140465	140465	140465
70024	140036	1053	0	0	0	0	0	1	0	0	0	0	1	0	140021	139700	139551	129342	25	80013	40010	30003	10000	30010	30000	10000	1266650	6703564	20111784	0	1	140235	0	140259	140036	130980	3	131162	70010	30020	10000	30000	60020	10000	50000	140259	140259	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3140	0	0	4	122	4	4	139558	40000	9	9	6	10000	20000	40010	140260	140037	140260	140037	140260
70024	140259	1052	0	0	0	0	0	0	0	0	0	0	1	0	140021	139700	139551	129983	25	80013	40010	30000	10000	30010	30000	10000	1264728	6703564	20079595	0	1	140235	0	140036	140259	130776	3	131589	70010	30020	10000	30000	60020	10000	50000	140036	140259	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3140	0	0	6	122	5	4	139780	40000	0	0	9	10000	20000	40010	140260	140037	140037	140465	140260
70024	140259	1049	0	0	0	0	0	1	0	0	6	0	1	0	140021	139700	139551	129768	25	80010	40010	30003	10000	30010	30000	10000	1264728	6703564	20111784	0	1	140235	0	140263	140259	130554	3	131162	70010	30020	10000	30000	60020	10000	50000	140259	140464	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3140	0	0	4	122	5	4	139558	40000	0	0	0	10000	20000	40010	140465	140260	140260	140465	140465
70024	140036	1049	0	0	0	0	0	0	0	0	1	0	1	0	140244	139700	139753	129768	25	80013	40010	30000	10000	30010	30000	10000	1268532	6713366	20141197	0	0	140235	0	140259	140259	131195	3	131162	70010	30020	10000	30000	60020	10000	50000	140036	140036	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	3140	3	0	6	122	4	4	139780	40000	0	6	9	10000	20000	40010	140037	140260	140465	140260	140037
70024	140464	1052	0	0	0	0	0	0	0	0	1	0	0	0	140244	139700	139326	129564	25	80013	40010	30003	10000	30010	30000	10000	1264728	6703564	20111784	0	1	140235	0	140259	140259	130980	3	131383	70010	30020	10000	30000	60020	10000	50000	140259	140464	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	51	2	0	10000	1	0	1	0	0	3140	0	0	6	122	5	4	139985	40000	0	6	0	10000	20000	40010	140260	140260	140037	140260	140348
70024	140259	1049	0	0	0	0	0	1	0	0	0	0	0	0	140245	139488	139326	129564	25	80013	40010	30000	10000	30010	30000	10000	1266650	6692839	20111784	0	0	140235	0	140036	140259	130776	3	131162	70010	30020	10000	30000	60020	10000	50000	140036	140464	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	3140	0	0	4	122	5	4	139558	40000	9	9	0	10000	20000	40010	140037	140465	140037	140260	140260

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6263

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	1e	1f	22	23	37	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst simd alu (9a)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	50130	375	0	0	0	0	25	0	1	0	93	1	50126	2	10	10	0	0	26	240236	100	160161	80000	100	160000	80000	500	400068	1923081	1	50048	50114	50102	0	34	3	63	240100	200	80000	160000	200	80000	320000	50117	50103	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	23	80026	0	0	26	80026	6	1	20	0	0	15110	1	16	1	1	50132	1	0	10	0	80000	320000	100	50073	50073	50076	50068	50068
400204	50102	376	0	0	0	0	32	0	0	0	402	0	50052	2	10	0	0	0	34	240288	100	160189	80000	100	160000	80000	500	400068	1927223	1	50186	50108	50067	0	34	3	43	240100	200	80000	160000	200	80000	320000	50067	50101	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	23	80025	0	0	0	80020	0	1	0	29	0	15110	1	16	1	1	50105	0	0	0	6	80000	320000	100	50109	50068	50103	50119	50157
400204	50149	376	0	0	0	0	686	308	1	0	1605	0	50071	2	10	10	0	0	26	240700	100	160188	80000	100	160000	80000	500	400135	1916967	1	50149	50067	50180	0	35	3	65	240100	200	80000	160000	200	80000	320000	50089	50075	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	0	80000	0	0	26	80000	6	0	19	29	0	15110	1	16	1	1	50116	1	0	10	0	80000	320000	100	50123	50148	50138	50079	50068
400204	50072	375	0	0	0	0	0	0	1	0	95	0	50087	2	0	0	15	0	26	240314	100	160331	80000	100	160000	80000	500	400059	1916967	0	50107	50078	50067	0	0	3	54	240100	200	80000	160000	200	80000	320000	50103	50090	1	1	240201	100	99	100	100	80000	160000	80000	1	100	80000	0	0	80026	0	0	0	80026	6	1	26	0	0	15110	1	16	1	1	50105	0	0	0	0	80000	320000	100	50115	50068	50068	50102	50104
400204	50103	375	0	0	0	0	32	0	0	0	1710	0	50122	0	0	0	41	0	26	240314	100	160396	80000	100	160000	80000	500	400126	1923992	0	50059	50086	50086	2	114	3	32	240100	200	80000	160000	200	80000	320000	50152	50075	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	0	80019	0	0	46	80019	6	1	20	29	0	15110	1	16	1	1	50069	0	0	10	0	80000	320000	100	50141	50150	50107	50115	50068
400204	50067	375	0	0	0	0	0	0	0	0	317	0	50088	2	10	0	0	0	26	240100	100	160440	80000	100	160000	80000	500	400127	1923644	1	50083	50113	50108	0	38	3	24	240100	200	80000	160000	200	80070	320000	50103	50078	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	23	80000	0	0	0	80019	0	1	19	29	0	15110	1	16	1	1	50105	1	0	0	6	80000	320000	100	50068	50102	50153	50068	50120
400204	50067	375	0	0	0	0	31	0	0	0	205	0	50052	0	10	10	15	0	26	240100	100	160000	80000	100	160000	80000	500	400067	1916967	1	50121	50067	50108	0	0	3	24	240100	200	80000	160000	200	80000	320000	50101	50118	1	1	240201	100	99	100	100	80000	160000	80000	1	100	80000	0	23	80000	0	0	26	80025	0	0	25	29	0	15110	1	16	1	1	50105	1	0	10	0	80000	320000	100	50119	50117	50123	50104	50068
400204	50102	375	0	0	0	0	32	0	0	0	595	0	50125	2	10	0	61	0	26	240350	100	160000	80000	100	160000	80000	500	400065	1923746	1	50059	50067	50230	0	41	3	65	240100	200	80000	160000	200	80000	320000	50100	50089	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	23	80000	0	0	0	80026	6	0	19	0	0	15110	1	16	1	1	50083	1	0	0	0	80000	320000	100	50102	50068	50109	50109	50102
400204	50102	376	0	0	0	0	31	0	0	0	454	1	50129	2	10	10	0	0	26	240100	100	160346	80000	100	160000	80000	500	400126	1921642	1	50089	50195	50101	0	11	3	64	240100	200	80000	160000	200	80000	320000	50095	50112	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	0	80026	0	0	0	80026	6	1	0	29	0	15110	1	16	1	1	50099	1	0	0	6	80000	320000	100	50103	50108	50068	50078	50087
400204	50103	375	1	0	1	1	31	0	0	0	83	1	50137	2	10	0	27	0	26	240265	100	160214	80000	100	160000	80000	500	400126	1919716	1	50048	50119	50067	0	27	3	60	240100	200	80000	160000	200	80000	320000	50108	50195	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	23	80026	0	0	0	80019	0	1	25	23	0	15110	1	16	1	1	50064	0	0	0	6	80000	320000	100	50100	50141	50150	50079	50068

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6260

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	37	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst simd alu (9a)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	50109	375	0	0	0	0	0	0	0	0	49	0	1	281	0	50056	2	10	10	0	0	26	240247	10	160237	80000	10	160000	80000	50	400000	1918460	2	1	5	50060	50068	50044	0	29	3	50	240010	20	80000	160000	20	80000	320000	50079	50079	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	23	80019	0	0	0	19	80019	6	1	20	23	0	0	15071	17	4	4	42	17	8	4	4	43	31	50137	0	0	80	6	0	80000	320000	10	50053	50080	50045	50056	50045
400024	50105	375	0	0	0	0	0	0	0	0	25	0	1	0	0	50064	2	10	10	0	0	26	240247	10	160237	80000	10	160000	80000	50	400067	1918460	2	1	5	50060	50044	50044	0	11	3	62	240010	20	80000	160000	20	80000	320000	50055	50071	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	23	80019	0	0	0	20	80019	6	1	0	23	0	0	15028	17	4	4	34	17	8	4	4	49	26	50089	1	0	86	6	0	80000	320000	10	50080	50080	50080	50080	50080
400024	50079	375	0	0	0	0	0	0	0	0	32	0	0	56	0	50064	2	10	10	0	0	26	240010	10	160237	80000	10	160000	80000	50	400000	1911249	2	1	5	50060	50079	50079	0	0	3	34	240010	20	80000	160000	20	80000	320000	50079	50079	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	23	80019	0	0	0	19	80019	6	1	19	0	0	0	15028	17	4	4	35	17	8	4	4	17	39	50153	0	0	86	6	0	80000	320000	10	50045	50045	50045	50107	50045
400024	50079	375	0	0	0	0	0	0	0	0	157	0	0	519	4	50088	2	10	10	0	0	90	240010	10	160179	80000	10	160000	80000	50	400059	1918458	2	1	5	50036	50079	50044	0	35	3	58	240010	20	80000	160000	20	80000	320000	50079	50079	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	23	80019	0	0	0	19	80019	6	1	19	23	0	0	15030	20	5	5	33	17	10	4	4	24	30	50131	0	0	106	6	0	80000	320000	10	50080	50080	50080	50080	50084
400024	50072	375	1	0	1	0	0	0	0	0	25	0	0	56	0	50040	2	0	0	0	0	26	240247	10	160237	80000	10	160000	80000	50	400000	1918460	1	1	5	50060	50055	50079	0	19	3	58	240010	20	80000	160000	20	80000	320000	50079	50098	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	23	80020	0	0	0	0	80020	0	1	20	0	0	0	15030	20	5	4	34	17	10	5	5	36	23	50266	0	0	106	6	0	80000	320000	10	50074	50053	50080	50106	50072
400024	50055	374	0	0	0	0	0	0	0	0	25	0	1	216	0	50064	2	10	10	0	0	26	240291	10	160000	80000	10	160000	80000	50	400057	1911249	1	1	5	50047	50055	50044	0	35	3	58	240010	20	80000	160000	20	80000	320000	50079	50044	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	0	80019	0	0	0	0	80019	0	0	19	23	0	0	15030	20	5	5	35	17	8	4	4	35	34	50080	0	0	106	6	0	80000	320000	10	50080	50080	50080	50080	50064
400024	50044	375	0	0	1	0	0	0	0	0	25	0	1	191	3	50029	2	10	0	0	0	27	240010	10	160101	80000	10	160000	80000	50	400068	1918460	2	1	5	50054	50083	50052	0	35	3	46	240010	20	80000	160000	20	80000	320000	50079	50071	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	23	80020	0	0	0	19	80020	0	1	20	23	0	0	15028	20	4	5	20	17	10	5	5	16	34	50154	0	0	86	0	0	80000	320000	10	50045	50080	50080	50080	50080
400024	50106	375	0	0	0	0	0	0	0	0	25	0	0	270	0	50158	2	10	10	0	0	26	240247	10	160237	80000	10	160000	80000	50	400059	1911249	1	1	5	50025	50079	50079	0	0	3	58	240010	20	80000	160000	20	80000	320000	50079	50079	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	23	80020	0	0	0	20	80000	6	1	20	23	0	0	15028	17	4	4	36	17	8	4	5	26	30	50065	1	0	106	0	0	80000	320000	10	50080	50080	50080	50045	50045
400024	50079	375	0	0	0	0	0	0	0	0	25	0	1	77	0	50029	2	10	10	0	0	26	240164	10	160093	80000	10	160000	80000	50	400059	1920235	1	1	5	50060	50044	50065	0	35	3	58	240010	20	80000	160000	20	80000	320000	50068	50071	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	23	80019	0	0	0	20	80019	6	0	26	23	0	0	15028	20	10	8	38	17	13	12	4	30	37	50197	0	0	131	6	1	80000	320000	10	50053	50069	50080	50080	50080
400024	50064	375	0	0	0	0	0	0	0	0	25	0	1	121	0	50064	2	10	10	0	0	26	240010	10	160237	80000	10	160000	80000	50	400000	1914821	1	1	5	50033	50044	50079	0	0	3	23	240010	20	80000	160000	20	80000	320000	50073	50052	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	23	80019	0	1	0	0	80019	6	0	20	23	0	0	15030	20	49	5	23	17	8	4	4	27	32	50351	0	0	86	6	0	80000	320000	10	50080	50080	50080	50080	50045

LD2 (single, B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations