Firestorm: LD2 (single, D) measurements

Code:

  ld2 { v0.d, v1.d }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.002

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.002

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	0e	0f	1e	22	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
63005	29338	219	5	1	0	1	3	0	0	0	1	0	0	4573	28753	0	0	0	17210	3002	2002	1000	2000	1000	5000	23806	3	22732	29177	29368	3	10	3000	1000	2000	1000	4000	29153	29171	1	1	61001	1000	1000	0	1000	3	1000	0	3	1000	2	1	2	12880	9200	6837	3047	0	80	20614	3094	3813	11	53	49	28306	16297	14176	15038	1000	2000	29260	29257	29174	29165	29265
63004	29303	220	5	1	0	0	0	0	0	7	0	0	0	4577	28848	0	0	0	17182	3000	2002	1000	2000	1000	5000	23802	7	22703	29057	29311	3	10	3000	1000	2000	1000	4000	29286	29298	1	1	61001	1000	1000	0	1000	3	1000	0	0	1000	0	1	3	13076	9371	6815	3173	0	59	20651	3131	3812	20	54	53	28342	16271	13995	15090	1000	2000	29357	29250	29342	29340	29360
63004	29324	220	6	0	0	0	0	0	0	13	1	0	0	4590	28735	0	0	0	17236	3004	2002	1000	2000	1000	5000	23806	7	22751	29232	29348	3	10	3000	1000	2000	1000	4000	29169	29246	1	1	61001	1000	1000	0	1000	3	1002	0	0	1002	2	0	3	12771	9079	6799	3021	2	59	20662	3020	3809	19	59	59	28369	16305	14114	15215	1000	2000	29289	29303	29300	29266	29276
63004	29384	218	7	0	0	0	0	0	0	2	1	0	0	4715	28792	0	1	0	17189	3002	2002	1000	2000	1000	5000	23907	7	22725	29115	29407	3	10	3000	1000	2000	1000	4000	29154	29176	1	1	61001	1000	1000	0	1000	3	1000	0	0	1000	0	1	2	12892	9124	6831	3035	1	49	20645	3041	3808	12	47	52	28279	16167	13990	15276	1000	2000	29324	29273	29258	29331	29274
63004	29479	218	2	0	0	0	1	0	0	2	1	0	0	4752	28731	0	0	0	17200	3002	2000	1000	2000	1000	5000	23873	8	22699	29053	29276	13	10	3000	1000	2000	1000	4000	29210	29241	1	1	61001	1000	1000	0	1000	2	1000	0	0	1000	3	2	3	13137	9135	6796	3069	0	64	20660	3053	3808	10	50	52	28325	16313	13954	15123	1000	2000	29258	29239	29232	29339	29284
63004	29265	220	5	0	0	0	1	0	0	8	0	0	0	4571	28858	0	1	1	17243	3000	2002	1000	2000	1000	5000	23907	4	22731	29078	29257	3	10	3000	1000	2000	1000	4000	29161	29222	1	1	61001	1000	1000	0	1000	3	1000	0	2	1000	2	1	3	12906	9115	6795	3108	1	55	20651	3036	3808	15	53	52	28331	16398	14089	15070	1000	2000	29312	29290	29207	29290	29236
63004	29297	219	8	0	0	0	0	0	0	19	1	0	0	4711	28829	0	1	0	17120	3002	2002	1000	2000	1000	5000	23902	5	22651	29047	29349	3	10	3000	1000	2000	1000	4000	29189	29181	1	1	61001	1000	1000	0	1000	3	1000	0	0	1000	2	0	3	13649	9199	7086	3068	1	55	20627	3093	3813	13	60	51	28336	16182	14078	15195	1000	2000	29209	29278	29269	29396	29354
63004	29302	220	4	1	0	0	1	0	0	4	0	0	0	4884	28723	0	0	0	17187	3002	2000	1000	2000	1000	5000	23919	4	22737	29086	29181	3	10	3000	1000	2000	1000	4000	29192	29154	1	1	61001	1000	1000	0	1000	0	1000	0	3	1000	2	1	3	12784	9087	6829	3040	1	54	20554	3050	3804	15	57	55	28390	16056	13959	15168	1000	2000	29255	29207	29295	29263	29271
63004	29358	219	4	0	0	0	1	0	0	4	0	0	0	4495	28868	0	0	0	17194	3000	2000	1000	2000	1000	5000	23869	4	22711	29096	29257	3	10	3000	1000	2000	1000	4000	29085	29110	1	1	61001	1000	1000	0	1000	3	1000	0	0	1000	3	1	2	12861	9018	6843	3068	1	53	20629	3088	3813	12	49	47	28502	16366	14177	15082	1000	2000	29196	29307	29271	29292	29283
63004	29247	220	2	1	0	0	1	1	0	4	1	0	0	4568	28770	0	1	0	17183	3002	2002	1000	2000	1000	5000	23905	3	22737	29047	29274	3	10	3000	1000	2000	1000	4000	29124	29318	1	1	61001	1000	1000	0	1000	3	1000	0	0	1000	0	0	0	12683	9051	6831	3022	2	62	20658	3046	3811	16	60	57	28456	15623	14208	15096	1000	2000	29274	29349	29316	29311	29240

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.d, v1.d }[1], [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0053

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	22	23	24	3a	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140110	1049	1	1	0	0	0	0	0	2	1	0	0	1	140038	139592	139332	129359	25	80106	40100	30006	10000	30100	30000	10000	1264381	6693682	20082149	0	0	140029	0	140053	140053	130549	0	3	131149	70100	30200	10000	30000	60200	10000	50000	140053	140053	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	3	1	10001	0	1	277	10000	1	1	1	1	1	0	3210	1	128	1	1	139565	40000	0	6	6	10000	20000	40100	140054	140054	140054	140054	140054
70204	140053	1049	1	1	1	1	0	0	0	1	1	0	0	1	140026	139450	139345	129359	25	80106	40100	30006	10000	30100	30000	10000	1275377	6694594	20082581	0	0	140029	0	140053	140053	130561	0	3	131149	70100	30391	10000	30000	60200	10000	50000	140053	140053	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	3	0	10001	0	1	253	10000	1	1	0	1	2	0	3210	1	128	1	1	139565	40000	0	0	0	10000	20000	40100	140054	140054	140042	140042	140054
70204	140053	1049	1	1	1	1	1	1	0	1	1	0	0	0	140032	139431	139338	129353	25	80103	40100	30003	10002	30100	30000	10000	1264355	6693388	20081263	0	0	140023	0	140047	140047	130543	0	3	131118	70100	30200	10000	30000	60200	10000	50000	140047	140047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	3210	1	128	1	1	139565	40000	6	6	6	10000	20000	40100	140054	140054	140046	140054	140054
70204	140085	1049	1	1	1	1	0	0	0	2	1	0	0	1	140026	139592	139345	129359	25	80106	40223	30054	10000	30100	30000	10000	1264381	6693682	20082149	0	0	140029	0	140053	140053	130561	0	3	131149	70100	30200	10000	30000	60200	10000	50315	140078	140041	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	3	1	10002	0	1	283	10000	1	1	1	1	3	0	3210	1	128	1	1	139565	40000	0	6	6	10000	20000	40100	140054	140054	140054	140054	140054
70204	140053	1050	1	1	1	1	0	0	0	2	1	0	0	1	140038	139450	139345	129359	25	80103	40100	30003	10000	30100	30000	10000	1264358	6693682	20080361	0	0	140029	0	140053	140053	130549	0	3	131149	70100	30200	10000	30000	60200	10000	50000	140053	140053	1	1	50201	100	99	100	40100	10000	10000	1	100	10001	2	1	10002	0	1	1	10000	1	1	0	1	0	0	3210	1	128	1	1	139565	40000	6	0	6	10000	20000	40100	140054	140054	140054	140054	140054
70204	140053	1049	1	1	0	1	0	0	0	2	0	0	0	1	140038	139450	139345	129359	25	80106	40100	30006	10000	30100	30000	10000	1264381	6693682	20082149	0	0	140029	0	140041	140053	130561	0	3	131137	70100	30200	10000	30000	60200	10000	50000	140041	140041	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10002	0	0	361	10000	1	1	1	1	1	0	3210	1	128	1	1	139565	40000	6	0	6	10000	20000	40100	140054	140054	140042	140054	140054
70204	140053	1050	1	0	1	1	0	0	0	2	0	1	0	1	140038	139450	139345	129359	25	80106	40107	30006	10000	30100	30000	10000	1264381	6693682	20101239	0	0	140017	0	140053	140053	130561	0	3	131166	70100	30200	10000	30000	60200	10000	50000	140053	140053	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	2	1	10002	0	1	1	10000	1	1	1	1	0	0	3210	1	128	1	1	139565	40000	6	6	6	10000	20000	40100	140054	140054	140042	140054	140042
70204	140053	1049	1	0	1	1	0	0	0	2	0	0	0	1	140038	139592	139345	129359	25	80103	40100	30006	10000	30100	30000	10000	1264313	6693682	20082149	0	0	140029	0	140053	140053	130636	0	3	131149	70100	30200	10000	30000	60200	10000	50000	140053	140053	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	2	1	10002	0	1	1	10000	1	1	0	1	1	0	3210	1	128	1	1	139565	40000	6	6	6	10000	20000	40100	140042	140054	140054	140054	140054
70204	140053	1050	1	1	1	1	0	0	0	2	0	1	0	0	140026	139592	139345	129359	25	80106	40100	30003	10000	30100	30000	10000	1264417	6693682	20082149	0	0	140029	0	140053	140053	130561	0	3	131149	70100	30200	10000	30000	60200	10000	50000	140053	140041	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	3	1	10002	0	1	1	10000	1	1	1	1	0	0	3210	1	128	1	1	139554	40000	6	6	0	10000	20000	40100	140054	140054	140042	140042	140054
70204	140053	1050	1	0	1	0	0	0	0	2	0	1	0	1	140038	139450	139345	129359	25	80106	40100	30006	10000	30100	30000	10000	1264381	6693682	20091077	0	0	140029	0	140053	140053	130561	0	3	131137	70100	30200	10000	30000	60200	10000	50000	140053	140053	1	1	50201	100	99	100	40100	10000	10000	1	100	10001	1	1	10001	0	1	262	10000	0	1	0	1	1	0	3210	1	128	1	2	139565	40000	0	6	6	10000	20000	40100	140054	140054	140042	140042	140054

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	0e	0f	18	1e	1f	22	23	24	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140051	1049	0	0	0	0	0	0	0	0	0	140036	139485	139344	129342	25	80013	40010	30003	10000	30010	30000	10000	1264783	6692791	20081843	1	1	140027	140051	140051	130569	3	131176	70010	30020	10000	30000	60020	10000	50319	140051	140054	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	1	0	10000	1	1	0	0	3140	6	121	2	4	139573	40000	26	0	10	10000	20000	40010	140052	140036	140052	140055	140052
70024	140051	1049	0	0	0	0	0	0	0	0	0	140036	139487	139344	129341	25	80013	40010	30003	10000	30010	30000	10000	1264783	6693584	20079451	0	1	140027	140051	140051	130569	3	131177	70010	30020	10000	30000	60020	10000	50000	140035	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	7	0	0	10000	1	1	1	0	3140	2	121	4	2	139557	40000	28	10	0	10000	20000	40010	140052	140055	140036	140055	140052
70024	140051	1049	0	0	0	0	6	0	1	0	0	140020	139507	139344	129357	25	80013	40010	30000	10000	30010	30000	10000	1264783	6693731	20105141	0	1	140027	140051	140051	130569	3	131177	70010	30020	10000	30000	60020	10000	50000	140051	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	0	10000	1	1	0	0	3140	2	121	2	4	139557	40000	28	10	10	10000	20000	40010	140055	140052	140055	140036	140052
70024	140035	1049	0	1	1	0	1	0	1	0	0	140036	139564	139344	129357	25	80013	40010	30003	10000	30010	30000	10000	1264783	6693779	20079451	0	1	140027	140035	140054	130572	3	131161	70010	30020	10000	30000	60020	10000	50000	140054	140035	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	1	10000	0	0	0	10000	0	0	0	0	3140	3	121	3	5	139573	40000	28	10	0	10000	20000	40010	140036	140055	140052	140036	140052
70024	140035	1049	0	0	0	0	1	0	0	0	0	140020	139507	139325	129357	25	80013	40010	30003	10000	30010	30000	10000	1264783	6693584	20081843	0	1	140011	140051	140051	130569	3	131176	70010	30020	10000	30000	60020	10000	50320	140058	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	10000	0	0	0	10000	1	0	0	0	3140	4	121	2	4	139576	40000	28	10	13	10000	20000	40010	140052	140052	140052	140055	140036
70024	140051	1049	0	1	1	0	1	0	0	0	0	140020	139487	139346	129360	25	80013	40010	30003	10000	30010	30000	10000	1264719	6693584	20081843	0	1	140027	140035	140051	130569	3	131176	70010	30020	10000	30000	60020	10000	50000	140035	140051	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	1	10000	0	0	0	10000	1	1	0	0	3140	2	121	2	4	139573	40000	28	0	10	10000	20000	40010	140052	140052	140052	140052	140052
70024	140051	1049	0	0	0	0	1	0	0	0	0	140036	139507	139346	129341	56	80027	40010	30003	10000	30010	30000	10000	1267553	6698116	20081843	0	1	140096	140051	140035	130569	3	131179	70010	30020	10000	30000	60020	10000	50000	140051	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	0	10000	1	1	0	0	3140	4	120	4	2	139573	40000	28	10	10	10000	20000	40010	140052	140036	140055	140052	140074
70024	140051	1049	0	0	0	4	550	0	1	0	0	140036	139487	139344	129357	25	80013	40010	30003	10000	30010	30000	10000	1264719	6693584	20089478	0	1	140030	140051	140035	130591	3	131179	70010	30020	10000	30000	60020	10000	50314	140035	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	1	0	0	10000	1	1	0	0	3140	2	121	2	4	139576	40000	28	11	10	10000	20000	40010	140052	140052	140052	140036	140036
70024	140051	1049	0	0	0	0	1	0	1	0	0	140036	139564	139346	129360	25	80030	40010	30003	10000	30010	30000	10000	1264819	6693731	20080609	0	1	140011	140051	140035	130569	3	131176	70010	30020	10000	30000	60020	10000	50000	140051	140054	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	0	10000	1	1	0	0	3140	2	121	2	4	139576	40000	28	10	13	10000	20000	40010	140055	140055	140055	140036	140055
70024	140051	1049	0	0	0	0	27	0	1	0	0	140020	139487	139346	129357	25	80013	40010	30003	10000	30010	30000	10000	1264783	6693584	20079451	0	1	140027	140645	140265	130569	3	131176	70010	30020	10000	30000	60020	10000	50531	140056	140035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	0	10000	1	1	0	0	3140	4	121	2	4	139573	40000	28	0	13	10000	20000	40010	140055	140036	140055	140055	140055

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.d, v1.d }[1], [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0682

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140496	1054	1	1	0	1	0	0	2	1	0	1	140667	140276	139972	129985	25	80103	40100	30006	10000	30100	30000	10000	1269946	6723821	20172574	1	140658	140682	140682	131187	3	131777	70100	30200	10000	30000	60200	10000	50000	140682	140682	1	1	50201	100	99	100	40100	10000	10000	1	100	10001	3	1	10001	0	1	0	1	10000	1	1	0	1	1	0	3210	2	129	2	2	140192	40000	10	10	10	10000	20000	40100	140683	140683	140459	140683	140683
70204	140682	1052	1	1	1	1	0	0	2	0	0	1	140443	140276	139972	129987	25	80119	40100	30003	10000	30100	30000	10000	1269946	6723821	20172574	1	140517	140653	140695	130964	3	131777	70100	30200	10000	30000	60200	10054	50000	140682	140682	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10002	0	0	2	1	10000	1	1	1	1	1	0	3210	1	129	2	2	140192	40000	10	10	10	10000	20000	40100	140683	140683	140683	140683	140683
70204	140682	1053	1	1	1	0	0	0	1	1	0	1	140667	140281	139972	129985	25	80106	40100	30006	10000	30100	30000	10000	1269946	6723821	20172574	1	140658	140682	140682	130964	3	131777	70100	30200	10000	30189	60200	10000	50000	140682	140458	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	2	1	10002	0	0	1	1	10000	1	1	1	1	0	0	3210	2	129	2	1	139969	40000	10	10	10	10000	20000	40100	140683	140683	140683	140683	140459
70204	140682	1054	1	1	1	1	0	0	2	1	0	1	140667	140276	139972	129985	25	80106	40100	30016	10001	30100	30000	10000	1269946	6713069	20172574	1	140658	140682	140682	131187	3	131777	70100	30200	10000	30000	60200	10106	50000	140682	140682	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	4	1	10007	0	1	3	4121	10001	1	1	1	1	0	0	3210	2	125	2	2	140182	40000	10	10	10	10000	20000	40100	140683	140683	140685	140683	140685
70204	140682	1052	1	1	0	1	1	1	2	1	0	0	140667	140276	139747	129985	25	80106	40100	30006	10000	30100	30000	10000	1269973	6723821	20172574	0	140658	140684	140684	131187	3	131777	70100	30200	10000	30000	60200	10000	50000	140682	140682	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	3	1	10002	0	0	1	8285	10002	1	1	1	1	3	0	3210	2	129	2	2	140192	40000	10	10	10	10000	20000	40100	140683	140684	140683	140683	140462
70204	140682	1052	1	1	0	0	0	0	13	0	0	1	140668	140276	139747	129985	25	80106	40100	30006	10000	30100	30000	10000	1269946	6723821	20172574	1	140659	140682	140458	131187	3	131553	70100	30200	10000	30000	60200	10000	50000	140682	140686	5	1	50201	100	99	100	40100	10000	10000	1	100	10002	2	1	10001	0	0	1	1	10000	1	1	1	1	1	0	3210	2	129	2	2	140192	40000	10	10	10	10000	20000	40100	140683	140683	140683	140683	140683
70204	140458	1054	1	1	0	1	0	0	2	1	0	1	140667	140276	139972	129985	25	80106	40100	30006	10000	30100	30000	10000	1269946	6723821	20172574	1	140658	140682	140682	131187	3	131777	70100	30200	10000	30000	60200	10000	50000	140682	140682	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	2	1	10001	0	0	1	22	10000	1	1	1	1	0	0	3210	1	129	2	2	140192	40000	10	10	10	10000	20000	40100	140683	140683	140683	140683	140683
70204	140682	1051	1	1	1	1	0	1	2	1	0	1	140667	140276	139972	129985	25	80106	40100	30006	10000	30100	30000	10000	1269946	6723821	20172574	1	140658	140682	140682	131187	3	131777	70100	30200	10000	30000	60200	10000	50000	140684	140684	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	2	1	10001	0	0	2	4	10000	0	1	1	1	2	0	3210	2	129	2	2	140192	40000	10	10	10	10000	20000	40100	140459	140686	140683	140683	140685
70204	140458	1054	1	0	1	1	0	0	2	1	0	1	140667	140276	139972	129985	25	80124	40116	30006	10000	30100	30000	10000	1269946	6723821	20172574	0	140658	140682	140682	131187	3	131777	70100	30200	10000	30000	60200	10000	50000	140458	140682	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10003	0	0	2	1	10000	1	1	1	1	0	0	3210	2	129	1	2	140192	40000	10	10	10	10000	20000	40100	140683	140683	140459	140683	140683
70204	140682	1052	1	1	0	0	0	0	1	1	0	1	140667	140276	139972	129985	25	80106	40100	30003	10000	30100	30000	10000	1269973	6723821	20172574	0	140658	140682	140682	131187	3	131777	70100	30200	10000	30000	60200	10000	50000	140682	140682	1	1	50201	100	99	100	40100	10000	10000	1	100	10001	2	1	10001	0	0	0	4	10000	1	1	1	1	0	0	3210	2	129	2	2	139969	40000	10	10	10	10000	20000	40100	140683	140683	140683	140683	140683

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0260

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	3a	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140870	1053	1	0	1	0	0	0	0	2	1	0	1	140676	140235	139975	129985	25	80016	40010	30006	10000	30010	30000	10000	1270465	6723821	20172574	0	140658	140682	140465	131197	0	3	131806	70010	30020	10000	30000	60020	10000	50000	140682	140682	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	3	1	10002	0	0	0	1	10000	1	1	1	1	1	0	1	3234	0	15	122	4	0	2	2	139781	40000	10	10	10	10000	20000	40010	140261	140261	140261	140261	140261
70024	140260	1051	0	0	0	0	0	0	0	1	0	1	0	140021	139716	139552	129565	25	80010	40010	30003	10000	30010	30000	10000	1266662	6703613	20111930	0	140236	140036	140312	130779	0	3	131384	70010	30020	10000	30000	60020	10000	50000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10001	0	1	0	0	10000	1	0	1	0	0	0	0	3140	0	2	120	0	0	3	6	139781	40000	10	10	10	10000	20000	40010	140356	140263	140265	140263	140261
70024	140260	1051	0	0	0	0	0	0	0	1	0	1	0	140245	139716	139552	129565	25	80013	40010	30003	10000	30010	30000	10000	1266662	6703613	20111930	0	140236	140260	140036	130554	0	3	131384	70010	30020	10000	30000	60390	10000	50000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	0	0	3140	0	2	122	1	0	2	2	139781	40000	10	0	10	10000	20000	40010	140261	140261	140261	140261	140261
70024	140036	1049	0	0	0	0	0	0	0	1	0	1	0	140245	139716	139552	129565	25	80013	40010	30000	10000	30010	30000	10000	1266662	6703613	20111930	1	140236	140260	140260	130777	0	3	131384	70010	30020	10000	30000	60020	10000	50000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	0	0	3140	0	2	122	0	0	3	6	139781	40000	10	10	10	10000	20000	40010	140261	140037	140261	140037	140261
70024	140260	1051	0	0	0	0	0	0	0	1	0	1	0	140245	139709	139552	129342	25	80013	40010	30000	10000	30010	30000	10000	1264728	6703613	20111930	0	140236	140036	140263	130777	0	3	131384	70010	30020	10000	30000	60020	10000	50000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	0	0	3140	0	2	122	1	0	3	3	139781	40000	10	10	0	10000	20000	40010	140261	140037	140261	140261	140261
70024	140260	1051	0	0	0	0	0	0	0	0	0	1	0	140245	139716	139552	129565	25	80013	40010	30003	10000	30010	30000	10000	1266662	6703613	20079595	0	140236	140260	140260	130777	0	3	131384	70010	30020	10000	30000	60020	10062	50000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	0	0	3140	0	2	122	0	0	2	2	139781	40000	10	10	10	10000	20000	40010	140261	140261	140037	140261	140261
70024	140260	1049	0	0	0	0	0	0	0	1	0	0	0	140245	139716	139552	129565	25	80013	40010	30003	10000	30010	30000	10000	1266662	6703613	20111930	1	140236	140260	140260	130777	0	3	131384	70010	30020	10000	30000	60020	10000	50000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	0	0	3140	0	6	122	1	0	2	2	139781	40000	10	10	0	10000	20000	40010	140261	140261	140261	140261	140261
70024	140260	1051	0	0	0	0	0	0	0	10	0	1	0	140245	139716	139552	129565	25	80013	40010	30000	10000	30010	30000	10000	1266662	6703613	20111930	1	140012	140260	140260	130777	0	3	131384	70010	30020	10000	30000	60020	10000	50000	140260	140260	2	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	0	0	3140	0	2	120	1	0	3	3	139558	40000	0	10	10	10000	20000	40010	140261	140261	140261	140037	140261
70024	140260	1051	0	0	0	0	0	0	0	1	0	1	0	140245	139488	139552	129565	25	80013	40010	30003	10000	30010	30000	10000	1266662	6703613	20111930	0	140236	140260	140260	130777	0	3	131384	70010	30020	10000	30000	60020	10000	50000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	0	0	3140	0	2	122	0	0	3	2	139781	40000	10	10	10	10000	20000	40010	140261	140261	140261	140261	140261
70024	140260	1051	0	0	0	0	0	0	0	1	0	1	0	140245	139719	139760	129565	25	80013	40010	30003	10000	30010	30000	10000	1266662	6703613	20111930	0	140012	140036	140260	130777	0	3	131384	70010	30020	10000	30000	60020	10000	50000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	0	0	10000	1	0	0	0	0	0	0	3140	0	6	122	2	0	3	2	139781	40000	10	10	10	10000	20000	40010	140261	140261	140261	140261	140261

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6263

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	0e	0f	19	1e	22	23	24	37	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst simd alu (9a)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	50128	389	0	1	0	1	0	37	1	0	0	164	1	50138	2	10	0	0	26	240100	100	160000	80000	100	160000	80000	500	400192	1923746	0	50091	0	50144	50072	0	0	3	24	240100	200	80000	160000	200	80000	320000	50103	50067	1	1	240201	100	99	100	100	80000	160000	80000	1	100	80000	0	0	80031	0	32	80000	6	1	25	35	0	15110	6	16	4	4	50163	1	14	10	80000	320000	100	50068	50104	50141	50123	50102
400204	50168	376	0	0	0	0	0	12	1	0	0	0	0	50052	2	9	0	0	26	240494	100	160247	80000	100	160000	80000	500	400193	1916967	0	50074	0	50108	50103	0	77	3	24	240100	200	80000	160000	200	80000	320000	50087	50101	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	29	80032	0	31	80000	6	1	26	0	0	15110	4	16	4	4	50064	1	14	14	80000	320000	100	50068	50161	50068	50154	50169
400204	50067	375	0	0	0	0	0	0	0	0	0	153	0	50052	2	9	0	0	26	240100	100	160519	80000	100	160000	80000	500	400203	1926662	0	50084	0	50164	50135	0	87	3	24	240100	200	80000	160000	200	80000	320000	50067	50101	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	29	80031	0	32	80031	6	1	31	0	2	15110	4	16	4	4	50064	1	14	10	80000	320000	100	50117	50068	50186	50169	50068
400204	50185	377	0	0	0	0	0	0	1	0	0	276	1	50119	0	9	9	17	26	240632	100	160176	80000	100	160000	80000	500	400209	1916967	0	50084	0	50072	50117	0	34	3	91	240100	200	80000	160000	200	80000	320000	50067	50067	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	0	80031	0	31	80000	6	1	0	0	0	15110	4	16	4	4	50105	1	14	14	80000	320000	100	50107	50169	50274	50110	50139
400204	50067	375	0	0	1	1	0	38	1	0	0	267	1	50094	2	9	9	41	26	240482	100	160228	80000	100	160000	80000	500	400000	1933839	0	50083	0	50089	50150	0	55	3	81	240100	200	80000	160000	200	80000	320000	50147	50119	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	29	80031	0	32	80031	6	1	26	0	0	15110	4	16	4	4	50064	1	10	10	80000	320000	100	50158	50109	50158	50109	50211
400204	50067	375	0	0	0	0	0	37	0	0	0	431	1	50119	0	9	9	15	26	240448	100	160382	80000	100	160000	80000	500	400193	1935407	0	50084	0	50152	50162	0	141	3	24	240100	200	80000	160000	200	80000	320000	50108	50108	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	29	80031	0	0	80031	6	0	26	0	0	15110	4	16	4	4	50064	1	14	14	80000	320000	100	50111	50068	50120	50196	50109
400204	50113	375	0	0	0	0	0	37	1	0	0	192	0	50052	2	9	9	46	26	240603	100	160240	80000	100	160000	80000	500	400192	1932359	0	50077	0	50186	50072	0	67	3	24	240100	200	80000	160000	200	80000	320000	50099	50067	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	35	80032	0	0	80000	0	1	32	0	0	15110	4	16	4	4	50064	2	14	14	80000	320000	100	50068	50068	50068	50125	50068
400204	50108	374	0	0	0	0	0	0	0	0	0	127	0	50127	2	10	10	0	26	240482	100	160503	80000	100	160000	80000	500	400000	1924402	0	50171	0	50244	50839	8	45	15	117	240100	200	80000	160000	200	80000	320000	50102	50108	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	29	80000	0	0	80031	6	1	25	35	0	15110	4	16	4	4	50100	1	0	10	80000	320000	100	50161	50107	50180	50165	50158
400204	50144	376	0	0	0	0	0	0	1	0	0	181	1	50120	2	0	9	24	26	240390	100	160718	80000	100	160000	80000	500	400192	1924817	0	50100	0	50074	50221	0	57	3	24	240100	200	80000	160000	200	80000	320000	50101	50067	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	29	80032	0	34	80000	6	1	26	29	0	15110	3	16	4	4	50165	1	14	14	80000	320000	100	50109	50109	50068	50104	50068
400204	50103	375	0	0	0	0	0	38	0	0	0	431	0	50145	0	9	0	0	26	240299	100	160331	80000	100	160000	80000	500	400204	1916967	0	50048	0	50209	50226	0	0	3	95	240100	200	80000	160000	200	80000	320000	50067	50102	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	29	80000	0	31	80000	6	1	31	0	0	15110	4	16	4	4	50064	1	14	0	80000	320000	100	50120	50161	50099	50068	50175

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6260

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	37	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst simd alu (9a)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	50110	375	1	0	3	1	0	0	0	0	0	38	0	1	0	222	4	50051	2	9	9	0	0	26	240305	10	160000	80000	10	160000	80000	50	400135	1911249	3	1	5	50058	0	50078	50165	0	47	3	53	240010	20	80000	160000	20	80000	320000	50078	50091	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	0	80032	0	0	31	80032	6	0	26	0	0	15030	29	13	8	0	58	17	9	8	5	29	45	50041	1	98	10	80000	320000	10	50079	50045	50077	50067	50079
400024	50102	375	0	0	0	0	0	0	1	0	0	629	0	1	0	192	3	50064	0	0	0	0	0	26	240170	10	160154	80000	10	160000	80000	50	400000	1918226	3	1	5	50039	0	50044	50080	0	22	3	44	240010	20	80000	160000	20	80000	320000	50078	50092	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	29	80031	0	0	35	80031	0	1	26	35	0	15034	32	14	9	0	43	17	11	9	6	43	30	50063	1	117	14	80000	320000	10	50103	50067	50045	50067	50079
400024	50066	375	1	0	0	0	0	1	1	0	0	38	0	1	0	70	4	50029	2	9	9	0	0	26	240189	10	160235	80000	10	160000	80000	50	400204	1911249	0	1	5	50046	0	50085	50044	0	47	3	23	240010	20	80000	160000	20	80000	320000	50064	50103	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	29	80031	0	0	0	80026	6	1	25	35	0	15030	29	13	8	0	42	17	9	8	5	35	42	50092	0	102	10	80000	320000	10	50119	50124	50045	50096	50090
400024	50106	375	1	0	0	0	0	0	0	0	0	0	0	0	0	132	4	50057	2	9	0	0	0	26	240193	10	160269	80000	10	160000	80000	50	400000	1911249	3	1	5	50066	0	50044	50066	0	67	3	23	240010	20	80000	160000	20	80000	320000	50081	50075	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	0	80031	0	0	26	80000	6	1	26	35	0	15030	29	13	8	0	43	17	9	8	5	43	43	50041	1	128	0	80000	320000	10	50045	50096	50079	50081	50045
400024	50078	375	0	0	0	0	0	1	0	0	0	37	0	0	0	105	3	50065	2	9	0	17	0	26	240010	10	160000	80000	10	160000	80000	50	400000	1917602	0	1	5	50066	0	50066	50044	0	44	3	45	240010	20	80000	160000	20	80000	320000	50065	50108	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	0	80031	0	0	28	80000	0	1	26	29	0	15032	29	13	8	0	44	17	9	8	5	28	44	50041	2	88	10	80000	320000	10	50134	50082	50082	50045	50096
400024	50079	375	0	0	0	0	0	0	0	0	0	0	0	0	0	107	4	50063	0	9	9	0	0	26	240203	10	160000	80000	10	160000	80000	50	400000	1924102	3	1	5	50062	0	50078	50080	0	0	3	57	240010	20	80000	160000	20	80000	320000	50081	50044	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	0	80031	1	0	31	80032	0	1	31	35	0	15034	29	13	10	0	35	17	9	8	5	28	42	50088	1	102	0	80000	320000	10	50045	50079	50079	50081	50096
400024	50044	375	0	0	0	0	0	0	0	0	0	0	0	1	0	119	3	50063	2	0	9	0	0	26	240193	10	160269	80000	10	160000	80000	50	400203	1923983	0	1	5	50066	0	50044	50103	0	29	3	60	240010	20	80000	160000	20	80000	320000	50079	50071	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	29	80000	0	0	0	80031	6	1	31	35	0	15030	29	15	8	0	44	17	9	8	5	27	43	50041	0	102	0	80000	320000	10	50080	50080	50045	50073	50045
400024	50089	375	1	0	0	0	0	0	0	0	0	38	0	0	0	0	3	50051	2	9	10	0	0	26	240189	10	160000	80000	10	160000	80000	50	400000	1923740	4	1	5	50059	0	50078	50080	0	36	3	23	240010	20	80000	160000	20	80000	320000	50078	50103	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	29	80025	0	0	31	80000	6	1	32	35	0	15032	29	13	8	0	44	17	9	8	5	29	44	50092	2	88	10	80000	320000	10	50080	50045	50081	50079	50079
400024	50064	376	1	0	0	0	0	0	1	0	0	0	0	0	0	0	5	50029	2	9	10	20	0	26	240214	10	160180	80000	10	160000	80000	50	400144	1921699	4	1	5	50025	0	50044	50078	0	34	3	67	240010	20	80000	160000	20	80000	320000	50078	50083	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	35	80031	0	0	32	80031	6	1	26	29	0	15032	29	13	8	0	44	17	9	8	5	43	35	50074	1	98	0	80000	320000	10	50074	50084	50099	50859	50068
400024	50066	375	1	0	0	0	0	1	1	0	0	38	0	0	0	164	4	50057	2	9	9	0	40	26	240215	10	160168	80000	13	160000	80000	50	400204	1942222	4	1	5	50054	0	50107	50138	0	28	3	45	240010	20	80000	160000	20	80000	320000	50144	50089	1	1	240021	10	9	10	10	80000	160000	80000	1	10	80000	0	29	80000	1	0	0	80031	6	1	32	0	0	15030	29	15	8	0	39	17	9	8	5	43	44	50111	1	88	14	80000	320000	10	50071	50078	50091	50045	50045

LD2 (single, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations