Firestorm: LD2 (single, H) measurements

Code:

  ld2 { v0.h, v1.h }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.006

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	1e	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
63005	28564	213	2	1	20	0	1	14	1	0	0	0	13	1	0	5061	28299	0	0	0	16354	3000	2002	1000	2000	1000	5004	23840	3	0	22754	28278	28264	3	10	3000	1000	2000	1000	4000	28279	28201	1	1	61001	1000	1000	0	1003	2	0	1001	0	1	0	3	1000	2	0	3	0	0	13882	10174	7045	3413	8	79	19701	3303	3810	12	54	46	27865	14987	12271	13024	1000	2000	28141	28233	28239	28352	28698
63004	28236	212	0	1	14	1	0	20	1	0	0	1	5	1	0	5084	28019	0	0	0	16340	3002	2007	1000	2000	1000	5000	23818	9	0	22787	28235	28107	3	10	3000	1000	2000	1000	4000	27995	28323	1	1	61001	1000	1000	0	1002	2	0	1005	0	0	2	5	1002	2	2	2	1	2	13830	10052	7077	3348	6	56	19655	3396	3807	8	56	56	28049	13972	12383	14368	1000	2000	28237	28719	28743	28220	28333
63004	28597	214	0	1	16	0	1	18	1	0	0	0	4	0	0	5082	28385	0	0	0	16294	3006	2006	1000	2000	1000	5000	23898	0	0	22760	28538	28281	3	10	3000	1000	2000	1000	4000	28312	28169	1	1	61001	1000	1000	0	1003	3	2	1001	0	36	1	4	1000	0	1	2	1	2	13890	10364	7268	3354	4	54	19699	3388	3812	17	59	54	27894	15284	12504	13136	1000	2000	28235	28362	28381	28131	28268
63004	28285	214	1	1	19	1	1	18	0	0	0	0	1	0	0	5172	28449	0	0	1	16312	3006	2007	1000	2000	1000	5000	23880	4	0	22763	28082	28212	3	10	3000	1000	2000	1000	4000	28222	28628	1	1	61001	1000	1000	0	1003	1	3	1003	0	0	2	5	1001	1	1	3	1	1	13401	9651	7212	3405	4	50	19612	3275	3808	8	44	48	27980	15198	12280	13871	1000	2000	28166	28294	28232	28656	28270
63004	28171	212	0	1	19	1	1	13	1	0	0	0	2	0	0	5141	27932	0	0	1	16345	3007	2007	1000	2000	1000	5000	23902	2	0	22816	28499	28265	3	10	3000	1000	2000	1000	4000	28142	28142	1	1	61001	1000	1000	0	1001	1	0	1004	0	0	1	71	1001	2	2	0	1	1	13958	10346	7292	3459	5	50	19534	3326	3813	18	51	49	27890	14499	12306	14142	1000	2000	28642	28193	28230	28107	28275
63004	28286	212	0	1	20	1	0	16	1	0	0	0	4	1	0	5137	27971	0	0	0	16272	3010	2002	1000	2000	1000	5000	23820	2	0	22778	28113	28634	3	10	3000	1000	2000	1000	4000	28532	28357	1	1	61001	1000	1000	0	1003	1	0	1004	0	0	2	6	1003	2	2	3	1	2	13164	10174	7194	3191	5	52	19528	3158	3814	17	58	55	28114	14514	13177	13187	1000	2000	28290	28638	28252	28564	28226
63004	28394	213	0	1	18	1	1	14	1	0	0	0	1	0	0	5071	28409	0	0	0	16338	3008	2008	1000	2000	1000	5000	23871	4	0	22831	28118	28372	3	10	3000	1000	2000	1000	4000	28136	28499	1	1	61001	1000	1000	0	1002	2	3	1001	0	0	0	9	1002	0	1	3	1	2	14137	10164	7272	3349	6	57	19539	3379	3811	7	49	51	28000	14376	12620	13599	1000	2000	28340	28678	28226	28075	28289
63004	28267	212	0	1	16	0	0	19	1	0	0	0	17	0	0	4959	28121	0	1	0	16297	3006	2006	1000	2000	1000	5000	23826	0	0	22758	28204	28382	3	10	3000	1000	2000	1000	4000	28598	28210	1	1	61001	1000	1000	0	1003	2	2	1002	0	0	1	4	1000	2	2	0	1	0	13282	9674	7207	3416	7	63	19498	3197	3811	10	52	53	27813	14048	12602	14024	1000	2000	28320	28305	28386	28423	28627
63004	28566	211	0	1	18	1	0	21	1	0	0	0	3	0	0	5192	28287	0	0	0	16250	3006	2006	1000	2000	1000	5000	23878	6	0	22763	28289	28389	3	10	3000	1000	2000	1000	4000	28195	28621	1	1	61001	1000	1000	0	1002	3	2	1004	0	0	1	16	1000	2	1	3	1	1	13219	10088	7279	3213	6	60	19626	3414	3818	10	53	55	27810	15317	12678	13594	1000	2000	28292	28140	28598	28609	28390
63004	28711	212	0	1	21	1	0	15	0	0	0	0	5	1	0	5225	27966	0	0	0	16234	3006	2008	1000	2000	1000	5001	23878	2	0	22774	28196	28623	3	10	3000	1000	2000	1000	4000	28232	28478	1	1	61001	1000	1000	0	1002	3	2	1001	0	0	2	8	1000	0	2	2	1	2	13550	10298	6969	3400	6	48	19656	3205	3813	6	52	46	27970	14352	12987	13197	1000	2000	28334	28215	28263	28142	28349

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.h, v1.h }[1], [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140041	1049	1	1	1	0	1	0	0	0	0	2	0	1	0	0	1	140042	139457	139350	129363	25	80106	40100	30003	10000	30100	30000	10000	1264210	6693878	20082745	1	140033	140057	140057	130565	3	131153	70100	30200	10000	30000	60200	10000	50000	140057	140057	1	1	50201	100	99	100	40100	10000	10000	0	100	10008	4	1	10008	0	0	0	4147	10000	1	1	1	1	1	3210	2	17	2	2	139569	40000	10	10	10	10000	20000	40100	140072	140069	140058	140059	140058
70204	140057	1049	1	1	1	0	1	0	1	0	0	2	0	1	0	0	1	140026	139657	139332	129363	25	80106	40100	30006	10000	30100	30000	10000	1264210	6693878	20082745	0	140033	140057	140057	130565	3	131153	70100	30200	10000	30000	60200	10000	50000	140057	140057	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	1	1	10002	0	0	2	1	10001	1	1	1	1	1	3210	2	128	2	2	139569	40000	10	10	10	10000	20000	40100	140097	140058	140059	140058	140058
70204	140057	1049	1	1	1	0	1	0	0	0	0	1	0	1	0	0	1	140042	139652	139350	129363	25	80106	40100	30006	10000	30100	30000	10000	1264210	6693878	20082745	0	140033	140057	140057	130565	3	131153	70100	30200	10000	30000	60200	10000	50000	140041	140041	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	1	0	10002	0	0	1	1	10000	1	1	1	1	1	3210	2	128	2	2	139569	40000	10	10	10	10000	20000	40100	140103	140060	140058	140058	140058
70204	140057	1049	1	1	1	0	1	0	0	0	0	2	0	1	0	0	1	140042	139652	139350	129363	25	80106	40100	30006	10000	30100	30000	10000	1264210	6693878	20082745	1	140033	140057	140057	130565	3	131153	70100	30200	10000	30000	60200	10000	50000	140058	140057	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10002	0	0	2	4	10000	1	1	1	1	0	3210	2	128	2	2	139569	40000	10	10	10	10000	20000	40100	140128	140062	140058	140058	140058
70204	140057	1049	1	0	1	0	1	0	0	0	0	2	0	1	0	0	1	140042	139654	139350	129363	25	80106	40100	30006	10000	30100	30000	10000	1264210	6693878	20082745	1	140033	140057	140057	130565	3	131153	70100	30200	10000	30000	60200	10000	50000	140057	140057	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	1	1	10002	0	1	1	1	10000	1	1	1	1	0	3210	2	128	2	2	139569	40000	10	0	0	10000	20000	40100	140064	140085	140060	140060	140058
70204	140057	1049	1	1	1	0	1	0	0	0	0	2	0	1	0	0	1	140042	139655	139350	129363	25	80106	40100	30006	10000	30100	30000	10000	1264210	6693091	20082745	1	140033	140041	140060	130549	3	131153	70100	30200	10000	30000	60200	10000	50000	140057	140057	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	3	1	10001	0	0	1	1	10000	1	1	1	1	1	3210	2	128	2	2	139569	40000	10	10	10	10000	20000	40100	140065	140058	140058	140058	140058
70204	140057	1049	1	0	1	0	1	0	0	0	0	2	0	1	0	0	0	140042	139652	139350	129363	25	80106	40100	30003	10000	30100	30000	10000	1264210	6694022	20082745	0	140033	140057	140041	130565	3	131153	70100	30200	10000	30000	60584	10000	50000	140057	140057	1	1	50201	100	99	100	40100	10000	10000	1	100	10014	1	1	10002	0	0	1	1	10000	1	1	1	1	1	3210	2	128	2	2	139569	40000	10	10	10	10000	20000	40100	140096	140042	140058	140058	140058
70204	140057	1049	1	0	1	0	0	0	0	0	0	2	0	1	0	0	1	140042	139652	139350	129347	25	80106	40100	30006	10000	30100	30000	10000	1264210	6693878	20082745	0	140033	140057	140057	130565	3	131153	70100	30200	10000	30000	60200	10000	50000	140057	140057	1	1	50201	100	99	100	40100	10000	10000	0	100	10005	1	1	10002	0	0	2	1	10000	1	1	0	1	1	3210	2	128	2	2	139569	40000	10	10	10	10000	20000	40100	140110	140061	140058	140058	140058
70204	140057	1049	1	1	0	0	1	0	0	0	0	2	0	1	0	0	0	140042	139652	139350	129363	25	80106	40100	30006	10000	30100	30000	10000	1264210	6693878	20082745	1	140017	140057	140057	130565	3	131153	70100	30200	10000	30000	60200	10000	50000	140041	140057	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	2	1	10003	0	0	1	1	10000	1	1	1	1	1	3210	2	128	2	2	139554	40000	10	10	0	10000	20000	40100	140152	140058	140058	140058	140058
70204	140041	1049	1	1	1	0	1	0	0	0	0	2	0	1	0	0	1	140042	139652	139350	129363	25	80106	40132	30003	10000	30100	30000	10000	1264210	6693878	20082745	0	140033	140041	140057	130565	3	131153	70100	30200	10000	30000	60200	10000	50000	140041	140057	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10001	0	0	1	1	10000	1	1	1	1	0	3210	2	128	2	2	139569	40000	10	0	10	10000	20000	40100	140136	140046	140058	140058	140058

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	1f	22	23	3a	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	df	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140073	1089	1	0	0	1	0	0	0	1	140020	139487	139343	129356	25	80010	40010	30003	10000	30010	30000	10000	1264771	6693535	20081263	1	140026	140050	140050	130553	0	3	131173	70010	30020	10000	30000	60020	10000	50000	140050	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	0	10000	1	1	0	0	1	3148	6	2	120	1	1	8	139569	40000	6	6	6	10000	20000	40010	140054	140036	140061	140050	140049
70024	140035	1049	0	1	0	0	0	1	0	1	140032	139448	139325	129353	25	80013	40010	30003	10000	30010	30000	10000	1264719	6693388	20081263	1	140011	140050	140035	130553	0	3	131161	70010	30020	10000	30000	60020	10000	50000	140035	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	0	1	0	0	0	3148	6	1	121	1	1	8	139557	40000	9	6	9	10000	20000	40010	140114	140052	140048	140036	140051
70024	140050	1049	0	0	0	1	0	1	0	1	140020	139446	139343	129353	25	80013	40010	30003	10000	30010	30000	10000	1264748	6693535	20081263	0	140026	140050	140050	130568	0	3	131175	70010	30020	10000	30189	60020	10000	50000	140050	140035	1	1	50021	10	9	10	40010	10000	10000	0	10	10010	0	1	10000	2	0	33	10000	1	1	2	0	0	3148	6	1	120	1	1	8	139557	40000	0	6	9	10000	20000	40010	140054	140051	140036	140048	140077
70024	140035	1049	0	0	0	1	0	1	0	1	140032	139487	139343	129419	25	80010	40010	30003	10000	30160	30000	10000	1264748	6693535	20081697	0	140011	140050	140050	130568	7	3	131161	70010	30020	10000	30000	60020	10000	50000	140035	140094	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	12	10000	1	0	0	0	0	3148	6	1	121	1	1	8	139569	40000	9	6	0	10000	20000	40010	140036	140036	140048	140048	140048
70024	140047	1049	0	0	0	0	0	0	0	1	140035	139446	139325	129341	25	80010	40010	30003	10000	30010	30000	10000	1264719	6693388	20081263	0	140023	140035	140047	130565	0	3	131173	70010	30020	10000	30000	60020	10000	50000	140047	140047	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	0	10000	0	0	0	10000	1	1	0	0	0	3148	6	1	121	1	1	8	139557	40000	6	6	9	10000	20000	40010	140037	140048	140051	140051	140051
70024	140050	1049	0	0	0	1	0	1	0	1	140035	139491	139338	129356	25	80013	40010	30003	10000	30010	30000	10000	1264771	6693535	20087209	0	140015	140050	140035	130553	0	3	131173	70010	30020	10000	30000	60020	10000	50000	140035	140047	1	1	50022	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	0	1	0	0	0	3148	6	1	121	1	1	8	139569	40000	6	6	6	10000	20000	40010	140051	140051	140036	140048	140036
70024	140050	1049	0	0	0	4	0	0	0	1	140020	139446	139325	129356	25	80013	40010	30000	10000	30010	30000	10000	1264748	6693388	20079451	0	140011	140035	140050	130553	0	3	131175	70010	30020	10000	30000	60020	10063	50000	140047	140035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	0	10000	0	1	0	0	0	3148	6	1	121	1	1	8	139557	40000	9	0	9	10000	20000	40010	140051	140048	140036	140051	140036
70024	140050	1049	0	0	0	6	0	1	0	1	140035	139446	139338	129341	25	80013	40010	30003	10000	30010	30000	10000	1264748	6692791	20081697	0	140023	140047	140047	130565	0	3	131173	70010	30020	10000	30000	60020	10000	50000	140050	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	3148	6	1	120	1	1	8	139569	40005	0	9	6	10000	20000	40010	140036	140051	140048	140048	140048
70024	140050	1049	0	0	0	1	0	1	0	1	140020	139446	139343	129341	25	80013	40010	30003	10000	30010	30000	10000	1264771	6693535	20081263	0	140011	140035	140050	130568	0	3	131173	70010	30020	10000	30000	60020	10000	50000	140050	140047	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	0	10000	1	0	0	10000	1	0	0	0	0	3148	6	1	120	1	1	8	139572	40000	6	6	6	10000	20000	40010	140036	140051	140036	140048	140048
70024	140035	1049	0	0	0	1	0	1	0	1	140035	139491	139343	129341	25	80013	40010	30006	10000	30010	30000	10000	1264870	6692791	20081697	1	140011	140047	140050	130565	0	3	131161	70010	30020	10000	30000	60020	10000	50000	140050	140035	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	3148	6	1	121	1	1	8	139572	40000	0	9	0	10000	20000	40010	140051	140036	140051	140036	140036

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.h, v1.h }[1], [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0260

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	18	19	1e	1f	22	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140682	1050	0	0	0	0	1	0	1	140245	139770	140175	129565	25	80103	40100	30003	10000	30100	30000	10000	1266232	6692839	20111930	140236	0	140260	140260	131391	3	131355	70100	30200	10000	30000	60200	10000	50000	140085	140260	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	10000	0	0	10000	1	1	0	0	3210	0	1	129	1	1	140396	40000	13	10	0	10000	20000	40100	140888	140888	140888	140906	140888
70204	140260	1049	1	1	0	0	1	0	1	140872	140439	140175	129342	25	80100	40100	30000	10000	30100	30000	10000	1272055	6702616	20111930	140863	0	140887	140887	131391	3	131982	70100	30200	10000	30000	60200	10000	50000	140260	140260	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	10000	0	0	10000	1	1	0	0	3210	0	1	133	1	1	140396	40000	13	0	13	10000	20000	40100	140261	140888	140037	140888	140888
70204	140887	1049	0	0	0	0	1	0	0	140872	139770	139326	130189	25	80103	40100	30003	10000	30100	30000	10000	1266232	6692839	20079595	140863	0	140036	140036	131391	3	131127	70100	30200	10000	30000	60200	10000	50000	140887	140260	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	10000	1	1	0	0	3210	0	1	17	1	1	139772	40000	0	10	0	10000	20000	40100	140037	140533	140358	140433	140261
70204	140260	1051	0	1	1	2	436	192	0	140245	140439	139326	130189	25	80100	40100	30000	10000	30100	30000	10000	1264319	6692839	20079595	140863	0	140260	140260	130532	3	131127	70100	30200	10000	30000	60200	10000	50000	140260	140036	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	1	10000	1	3	10000	1	1	0	0	3210	0	1	129	1	1	140396	40000	13	0	13	10000	20000	40100	140310	140889	140404	140839	140296
70204	140036	1052	0	0	4	1	6	0	0	140245	139770	139326	129565	25	80103	40100	30003	10000	30100	30000	10000	1264319	6733631	20079595	140236	0	140260	140261	130532	3	131129	70100	30200	10000	30000	60200	10000	50000	140261	140260	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	1	10000	1	0	10000	1	0	0	0	3210	0	1	133	1	1	140396	40000	10	10	0	10000	20000	40100	140261	140268	140261	140889	140889
70204	140887	1050	0	0	0	0	1	0	0	140872	140439	140175	130189	25	80103	40100	30003	10000	30100	30000	10000	1272055	6692839	20202004	140863	0	140036	140260	131391	3	131982	70100	30200	10000	30000	60200	10000	50000	140260	140260	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	10000	0	0	10000	1	1	0	0	3210	0	1	133	1	1	140396	40000	13	13	0	10000	20000	40100	140685	140037	140037	140888	140037
70204	140887	1051	0	0	0	0	1	0	0	140021	140439	140175	129342	25	80100	40100	30003	10000	30100	30000	10000	1272055	6692839	20079595	140236	0	140887	140260	131391	3	131127	70100	30200	10000	30000	60200	10000	50000	140887	140887	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	10000	1	1	0	0	3210	0	1	129	1	1	140396	40000	13	13	13	10000	20000	40100	140888	140888	140037	140888	140888
70204	140887	1050	0	0	0	0	0	0	0	140872	140439	140175	129342	25	80103	40100	30003	10000	30100	30000	10000	1272055	6733631	20202436	140863	0	140036	140887	131391	3	131982	70100	30200	10000	30000	60200	10000	50000	140887	140036	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	1	10000	0	0	10000	1	0	0	0	3210	0	1	133	1	1	139545	40000	13	0	13	10000	20000	40100	140037	140261	140888	140888	140037
70204	140260	1050	0	0	0	0	6	0	0	140872	140439	139326	130189	25	80103	40100	30003	10000	30100	30000	10000	1264319	6733631	20111930	140863	0	140036	140469	130532	3	131982	70100	30200	10000	30000	60200	10000	50000	140887	140260	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	1	10000	0	0	10000	0	1	0	0	3210	0	1	129	1	1	139772	40000	10	13	0	10000	20000	40100	140261	140037	140888	140038	140243
70204	140887	1049	1	1	0	0	1	0	0	140021	139405	139326	129342	25	80103	40100	30003	10000	30100	30000	10000	1272055	6692839	20111930	140863	0	140887	140036	130532	3	131127	70100	30200	10000	30000	60200	10000	50000	140887	140260	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	1	10000	0	0	10000	0	1	0	0	3210	0	1	129	1	1	140396	40000	0	10	10	10000	20000	40100	140888	140037	140037	140037	140037

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0260

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	1f	22	24	3a	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140532	1050	0	0	1	0	0	1	0	1	0	1	0	1	140472	139488	139552	129342	25	80010	40010	30000	10000	30010	30000	10000	1266662	6703613	20112362	1	140239	140260	140260	130777	3	131162	70010	30020	10000	30000	60020	10000	50000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	1	10001	0	1	1	10000	1	1	1	1	1	0	3140	5	122	2	4	140241	40000	10	10	10	10000	20000	40010	140683	140683	140683	140683	140683
70024	140036	1051	0	0	0	0	0	0	0	0	0	1	0	1	140668	140235	139972	129985	25	80016	40010	30003	10000	30010	30000	10000	1270465	6723821	20140295	1	140658	140682	140682	131197	3	131806	70010	30020	10000	30000	60020	10000	50000	140682	140682	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	3140	2	122	2	4	140266	40000	10	10	10	10000	20000	40010	140683	140683	140683	140683	140716
70024	140682	1054	1	0	0	1	0	0	0	10	0	1	0	1	140667	139716	139552	129565	25	80013	40010	30003	10000	30010	30000	10000	1266662	6703613	20111930	1	140236	140260	140260	130777	3	131384	70010	30020	10000	30000	60020	10000	50000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	0	0	10000	0	0	0	10000	0	0	1	0	0	0	3140	5	122	4	2	140201	40000	10	10	10	10000	20000	40010	140683	140683	140683	140683	140683
70024	140458	1053	1	1	0	0	0	0	0	0	0	1	0	1	140667	139716	139552	129565	25	80013	40010	30003	10000	30010	30000	10000	1266662	6703613	20111930	1	140236	140260	140260	130777	3	131384	70010	30020	10000	30000	60020	10000	50000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10001	2	0	27	10000	0	0	1	0	0	0	3140	2	122	2	4	140201	40000	10	10	10	10000	20000	40010	140261	140261	140037	140261	140261
70024	140036	1051	0	0	0	0	0	0	0	1	0	1	0	0	140245	139716	139552	129565	25	80013	40010	30003	10000	30010	30000	10000	1266662	6703613	20111930	1	140236	140260	140260	130777	3	131384	70010	30020	10000	30000	60020	10000	50000	140260	140260	2	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	3140	2	122	4	2	140247	40000	10	10	10	10000	20000	40010	140727	140635	140683	140683	140261
70024	140261	1050	0	0	0	0	0	0	0	1	0	1	0	1	140988	140235	139799	129728	25	80016	40010	30006	10000	30010	30000	10000	1270465	6723821	20172574	1	140236	140260	140260	130777	3	131386	70010	30020	10000	30000	60020	10000	50000	140260	140036	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	3140	4	122	4	2	139781	40000	10	10	10	10000	20000	40010	140261	140261	140261	140037	140037
70024	140260	1050	0	0	0	0	1	0	0	1	0	1	0	0	140245	139488	139552	129565	25	80013	40010	30003	10000	30010	30000	10000	1266662	6703613	20111930	1	140236	140260	140260	130777	3	131384	70010	30020	10000	30000	60020	10000	50000	140327	140264	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	3140	2	122	2	4	139781	40000	10	10	10	10000	20000	40010	140261	140261	140261	140261	140261
70024	140260	1051	0	0	0	0	0	0	0	1	0	1	0	0	140667	140235	139326	129342	25	80013	40010	30003	10000	30010	30000	10000	1266662	6703613	20111930	1	140236	140260	140264	130777	3	131384	70010	30020	10000	30000	60020	10000	50000	140682	140682	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	3	1	10002	0	0	1	10000	1	0	1	0	0	0	3140	2	122	4	4	139781	40000	10	10	10	10000	20000	40010	140442	140261	140261	140261	140261
70024	140037	1050	0	0	0	0	0	0	2	1078	108	1	0	0	140245	139716	139552	129565	25	80013	40010	30003	10000	30010	30000	10000	1266662	6703613	20111930	1	140236	140260	140260	130777	3	131384	70010	30020	10000	30000	60020	10000	50000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	2	0	3	10000	1	0	1	0	0	0	3140	2	122	5	2	139781	40000	10	10	10	10000	20000	40010	140261	140262	140261	140455	140261
70024	140639	1051	0	0	0	0	0	0	0	13	0	1	0	0	140245	139716	139552	129565	25	80013	40010	30003	10000	30010	30000	10000	1266662	6703613	20111930	1	140236	140260	140260	130777	3	131384	70010	30020	10000	30000	60020	10000	50000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	1	0	3	10000	1	0	1	0	0	0	3140	2	120	3	4	139781	40000	10	10	10	10000	20000	40010	140261	140261	140261	140261	140261

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.h, v1.h }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.h, v1.h }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.h, v1.h }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.h, v1.h }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.h, v1.h }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.h, v1.h }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.h, v1.h }[1], [x6]
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.h, v1.h }[1], [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6263

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	37	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst simd alu (9a)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	50129	376	0	0	1	0	0	0	25	1	0	206	1	50073	2	0	10	0	26	240331	100	160264	80008	100	160022	80012	500	400071	1922723	1	50103	50067	50067	0	9	6	99	240134	200	80012	160022	200	80012	320044	50102	50098	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80014	11	0	80047	0	0	44	80035	6	1	44	37	11	2	1	1	1	15117	3	16	4	4	50097	0	9	9	80000	320000	100	50151	50099	50142	50142	50142
400204	50096	375	1	1	0	1	0	0	50	1	0	94	1	50068	2	0	10	12	26	240501	100	160236	80008	100	160022	80012	500	400071	1931765	1	50078	50098	50098	0	9	6	44	240134	200	80012	160022	200	80012	320044	50082	50067	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80014	11	37	80015	0	2	44	80002	6	1	43	37	11	1	1	1	1	15117	4	16	3	3	50102	0	0	9	80000	320000	100	50126	50106	50083	50101	50131
400204	50082	375	1	0	1	0	0	0	11	0	0	174	0	50160	0	10	0	0	26	240344	100	160476	80008	100	160022	80012	500	400071	1925702	0	50048	50186	50100	0	42	6	96	240134	200	80012	160022	200	80012	320044	50076	50097	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80013	13	37	80015	0	0	43	80002	6	1	11	37	11	0	1	1	1	15117	3	16	2	4	50102	0	9	9	80000	320000	100	50068	50119	50106	50103	50198
400204	50098	375	1	1	1	1	0	0	10	0	0	92	1	50052	2	0	10	5	27	240149	100	160088	80008	100	160022	80012	500	400299	1915232	0	50112	50089	50127	0	15	6	74	240134	200	80012	160022	200	80012	320044	50105	50067	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80013	11	37	80046	0	0	43	80002	6	1	43	37	11	0	1	1	1	15117	3	16	3	3	50095	0	9	9	80000	320000	100	50071	50097	50081	50098	50248
400204	50103	375	1	0	0	0	0	0	50	0	0	116	1	50083	2	10	10	0	26	240155	100	160307	80008	100	160022	80012	500	400296	1919114	1	50048	50098	50067	0	36	6	143	240134	200	80012	160022	200	80012	320044	50068	50108	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80011	11	0	80045	0	1	44	80033	6	0	10	0	11	0	0	0	0	15110	5	16	3	7	50094	0	9	9	80000	320000	100	50122	50068	50082	50129	50083
400204	50096	375	1	0	0	1	1	1	10	0	0	429	0	50135	0	10	0	0	26	240567	100	160228	80000	100	160000	80000	500	400248	1926176	1	50079	50098	50098	0	74	3	55	240100	200	80000	160000	200	80000	320000	50067	50119	1	1	240201	100	99	100	100	80000	160000	80000	1	100	80012	11	0	80044	0	0	47	80000	6	1	44	37	10	0	0	0	0	15110	5	16	4	5	50093	0	9	9	80000	320000	100	50151	50142	50226	50068	50070
400204	50119	375	1	1	1	0	0	0	11	0	0	120	0	50126	0	10	10	0	26	240135	100	160218	80000	100	160000	80000	500	400242	1917725	1	50063	50098	50225	0	15	3	24	240100	200	80000	160000	200	80000	320000	50098	50087	1	1	240201	100	99	100	100	80000	160000	80000	1	100	80012	12	37	80045	0	2	44	80033	6	1	43	0	11	1	0	0	0	15110	4	16	4	4	50071	0	9	0	80000	320000	100	50126	50124	50128	50068	50099
400204	50117	375	0	0	0	0	0	0	32	0	0	105	0	50142	0	10	10	0	26	240100	100	160312	80000	100	160000	80000	500	400067	1927327	1	50069	50100	50088	0	0	3	24	240100	200	80000	160000	200	80000	320000	50097	50077	1	1	240201	100	99	100	100	80000	160000	80000	1	100	80000	0	23	80000	0	0	0	80026	6	0	19	0	0	0	0	0	0	15110	4	16	5	6	50106	0	0	10	80000	320000	100	50099	50068	50116	50125	50103
400204	50081	375	0	0	0	0	0	0	41	0	0	193	1	50073	0	10	10	0	26	240364	100	160000	80000	100	160000	80000	500	400000	1925756	1	50095	50144	50106	0	47	3	34	240100	200	80000	160000	200	80000	320000	50094	50106	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	0	80026	0	0	25	80026	6	1	20	29	0	0	0	0	0	15110	4	16	3	5	50656	0	10	10	80000	320000	100	50124	50139	50068	50108	50115
400204	50114	375	0	0	0	0	0	0	32	0	0	237	1	50099	2	10	0	4	26	240498	100	160000	80000	100	160000	80000	500	400000	1916967	1	50079	50106	50096	0	0	3	24	240100	200	80000	160000	200	80000	320000	50096	50114	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	0	80026	1	0	25	80026	6	1	20	0	0	0	0	0	0	15110	4	16	3	4	50098	0	6	10	80000	320000	100	50096	50068	50068	50089	50102

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6259

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	1f	22	37	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst simd alu (9a)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	50129	375	1	1	0	1	0	50	0	0	102	3	50063	0	10	10	0	29	240123	13	160000	80000	13	160000	80000	68	400060	1915088	2	1	0	50097	0	50075	50106	21	3	63	240013	20	80000	160000	20	80000	320000	50150	50389	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80012	13	37	80045	0	0	0	43	80033	6	0	42	37	11	0	0	15029	25	10	8	21	31	14	12	8	17	9	50057	0	3	162	0	0	80000	320000	10	50061	50059	50101	50080	50108
400024	50073	375	0	0	0	0	0	31	0	0	99	4	50076	2	10	0	0	29	240376	13	160162	80000	13	160000	80000	68	400067	1920648	3	1	0	50088	0	50090	50060	48	3	57	240010	20	80000	160000	20	80000	320000	50060	50397	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	0	80000	0	0	0	0	80025	0	0	20	23	0	0	0	15030	25	10	8	11	29	16	14	9	7	16	50065	0	3	126	10	2	80000	320000	10	50076	50045	50106	50108	50107
400024	50044	376	0	0	0	0	0	31	0	0	172	3	50074	2	0	10	8	29	240447	10	160348	80000	10	160000	80000	68	400067	1914496	3	1	0	50072	0	50060	50091	73	3	58	240010	20	80000	160000	20	80000	320000	50060	50362	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	23	80026	0	1	0	26	80025	6	1	19	29	0	0	0	15030	25	10	8	14	29	14	8	6	9	14	50041	0	3	116	6	2	80000	320000	10	50045	50098	50059	50090	50061
400024	50125	374	0	0	0	0	0	32	0	1	67	4	50066	2	10	10	0	29	240334	13	160338	80000	10	160000	80000	50	400242	1921350	3	1	0	50124	0	50090	50058	83	3	158	240013	20	80000	160000	20	80000	320000	50062	50382	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	0	80019	0	0	0	25	80019	0	0	19	29	0	0	0	15029	28	10	9	10	31	12	8	8	8	15	50057	0	3	126	0	1	80000	320000	10	50088	50092	50105	50106	50144
400024	50071	375	0	0	0	0	0	89	0	1	262	4	50045	2	10	10	0	29	240013	13	160362	80000	13	160000	80000	68	400067	1922683	1	1	0	50088	0	50116	50094	0	3	23	240013	20	80000	160000	20	80000	320000	50060	50367	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80010	10	0	80045	0	0	1	11	80049	0	1	10	0	11	1	0	15033	31	13	10	10	31	14	10	7	14	10	50120	1	0	136	6	2	80000	320000	10	50117	50120	50083	50059	50117
400024	50090	375	0	0	0	0	0	32	0	1	39	6	50045	0	10	0	0	29	240183	13	160268	80000	13	160000	80000	68	400242	1918326	2	1	0	50072	0	50090	50060	0	3	60	240013	20	80000	160000	20	80000	320000	50090	50405	1	1	240021	10	9	10	10	80000	160000	80000	1	10	80000	0	0	80026	0	0	0	25	80026	6	1	0	0	0	0	0	15034	31	13	10	9	31	28	10	10	13	14	50100	0	3	181	9	2	80000	320000	10	50101	50074	50059	50098	50098
400024	50046	374	1	1	1	0	0	10	0	0	0	5	50045	2	10	10	0	29	240344	13	160000	80000	10	160000	80000	68	400068	1914496	1	1	0	50088	0	50058	50122	0	3	23	240010	20	80000	160000	20	80000	320000	50060	50658	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	23	80000	0	0	0	0	80000	0	0	19	29	0	0	0	15033	31	13	10	8	31	14	10	10	8	13	50065	0	3	182	10	0	80000	320000	10	50061	50059	50103	50059	50071
400024	50044	375	0	0	0	0	0	0	0	1	0	4	50066	0	10	0	0	29	240013	13	160196	80000	10	160000	80000	50	400135	1933972	2	1	0	50088	0	50060	50092	31	3	44	240013	20	80000	160000	20	80000	320000	50044	50366	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	23	80026	0	0	0	28	80019	0	1	25	29	0	0	0	15034	31	13	10	8	29	12	10	7	6	14	50086	0	3	142	6	1	80000	320000	10	50090	50059	50088	50059	50082
400024	50073	375	0	0	0	0	0	26	0	1	224	5	50084	2	0	0	0	29	240298	13	160160	80000	13	160000	80000	68	400126	1921001	1	1	0	50039	0	50119	50124	0	3	58	240010	20	80000	160000	20	80000	320000	50060	50362	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80012	11	37	80046	0	0	1	43	80000	6	1	11	37	11	0	0	15032	31	13	10	7	29	20	16	9	16	8	50055	0	3	146	6	1	80000	320000	10	50061	50106	50112	50059	50095
400024	50061	375	0	0	0	0	0	31	0	0	219	5	50091	0	10	10	17	29	240782	13	160302	80000	13	160000	80000	68	400059	1912518	1	1	0	50072	0	50133	50060	75	3	105	240213	20	80000	160000	20	80000	320000	50119	50329	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	23	80025	0	0	0	0	80000	6	0	20	29	0	0	0	15030	31	13	10	7	29	26	10	9	13	13	50114	0	3	126	10	2	80000	320000	10	50061	50106	50098	50077	50061

LD2 (single, H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations