Firestorm: LD2 (single, post-index, B) measurements

Code:

  ld2 { v0.b, v1.b }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.006

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch ret indir mispred nonspec (c8)	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
63005	29608	230	1	22	0	0	23	1	1	1	0	0	5	0	1	0	4565	28765	0	1	1	17190	4006	1000	2006	1000	1000	2000	1000	5000	5000	23923	23	0	0	22675	29136	29328	3	10	4000	1000	2000	2000	4000	29212	29220	1	1	61001	1000	1000	0	1002	2	2	1002	0	2	2	1001	2	1	3	1	1	0	0	13052	9443	6814	3128	11	53	20682	3155	3795	25	52	54	28518	1000	16059	13235	14525	1000	2000	1000	29409	29408	29271	29363	29314
63004	29514	229	1	26	0	0	21	1	1	0	0	0	1	0	0	0	4687	28941	0	0	0	17409	4002	1000	2002	1000	1000	2000	1000	5000	5002	23940	5	0	0	22667	29213	29461	3	10	4008	1000	2000	2000	4000	29355	29209	1	1	61001	1000	1000	0	1002	2	4	1001	2	1	185	1000	3	2	4	1	6	0	0	12994	9324	6894	3051	8	46	20805	3236	3799	23	44	48	28637	1000	16219	13145	14412	1000	2000	1000	29333	29420	29599	29327	29477
63004	29589	228	1	25	1	0	17	0	0	0	0	0	4	0	0	0	4548	28811	0	0	1	17261	4006	1000	2006	1000	1000	2000	1000	5000	5001	23859	20	0	0	22699	29042	29475	3	10	4000	1000	2000	2000	4000	29272	29220	1	1	61001	1000	1000	0	1001	1	4	1002	0	0	1	1001	0	1	3	1	1	0	0	13051	9340	6877	3142	8	53	20962	3412	3809	25	47	46	28709	1000	16071	13159	14361	1000	2000	1000	29864	29615	29633	29575	29612
63004	29702	239	1	24	0	0	19	1	0	0	0	0	3	0	0	0	4599	29107	0	0	0	17326	4000	1000	2006	1000	1000	2000	1000	5000	5000	23918	6	0	0	22741	29179	29415	3	10	4000	1000	2000	2000	4000	29206	29251	1	1	61001	1000	1000	1	1001	2	4	1001	0	3	88	1001	3	2	4	1	1	0	0	13061	9321	6908	3105	11	47	20760	3243	3797	24	51	42	28486	1000	16204	13368	14496	1000	2000	1000	29414	29313	29337	29306	29497
63004	29533	228	1	16	1	0	10	0	0	0	0	0	3	0	0	0	4651	28886	0	0	0	17411	4006	1000	2006	1000	1000	2000	1000	5000	5000	23795	5	0	5	22716	29105	29423	3	10	4000	1000	2000	2000	4000	29262	29268	1	1	61001	1000	1000	0	1002	0	4	1002	0	2	2	1001	2	0	0	1	0	0	0	12941	9240	6833	3056	6	47	20803	3230	3809	25	50	42	28309	1000	16286	13261	14377	1000	2000	1000	29507	29474	29383	29488	29459
63004	29431	228	1	19	0	0	21	0	1	1	0	0	3	0	0	0	4622	28894	0	0	0	17219	4002	1000	2006	1000	1000	2000	1000	5000	5000	23972	0	0	0	22768	29317	29425	3	10	4000	1000	2000	2000	4000	29231	29250	1	1	61001	1000	1000	0	1002	2	4	1001	0	0	1	1000	3	2	4	1	1	0	0	13127	9264	6979	3132	8	53	20657	3208	3795	29	48	48	28549	1000	16024	13036	14605	1000	2000	1000	29363	29373	29463	29235	29369
63004	29446	228	1	20	1	0	23	0	1	1	0	0	3	0	0	0	4675	28770	0	0	1	17289	4006	1000	2006	1000	1000	2000	1000	5000	5000	23895	6	0	0	22750	29098	29419	3	10	4000	1000	2000	2000	4000	29296	29148	1	1	61001	1000	1000	0	1001	0	4	1003	0	0	257	1000	2	1	0	1	1	0	0	13130	9242	6879	3099	7	44	20684	3241	3802	28	49	53	28500	1005	17427	14035	14402	1000	2000	1000	29479	29384	29372	29334	29455
63004	29423	228	1	16	1	0	20	0	0	0	0	0	5	0	0	0	4608	28812	0	0	0	17326	4000	1000	2006	1000	1000	2000	1000	5000	5001	23902	11	0	0	22752	29188	29410	3	10	4000	1000	2000	2000	4000	29226	29179	1	1	61001	1000	1000	0	1002	1	0	1001	1	0	1	1000	0	1	2	1	1	0	0	13072	9306	6912	3094	9	48	20671	3226	3809	19	48	54	28577	1000	16395	13352	14562	1000	2000	1000	29488	29352	29369	29391	29349
63004	29341	228	1	27	0	0	24	0	0	0	0	0	5	0	0	0	4575	28945	1	1	0	17428	4006	1000	2002	1000	1000	2000	1000	5000	5003	23864	0	0	0	22690	29218	29458	3	10	4000	1000	2000	2000	4000	29348	29254	1	1	61001	1000	1000	0	1001	0	4	1003	1	2	257	1001	0	1	0	1	0	0	85	12774	9306	6885	3141	10	44	20735	3257	3804	18	47	45	28592	1000	16514	13621	14713	1000	2000	1000	29437	29333	29307	29374	29460
63004	29511	232	1	22	0	0	19	0	0	0	0	0	159	0	0	0	4552	28823	0	1	1	17205	4002	1000	2006	1000	1000	2000	1000	5000	5000	23897	5	0	0	22746	29150	29273	3	10	4000	1000	2000	2000	4000	29243	29272	1	1	61001	1000	1000	0	1002	2	4	1000	1	1	0	1000	3	1	0	1	1	0	0	13136	9247	6870	3056	11	40	20736	3240	3807	27	48	49	28521	1000	16343	13441	14614	1000	2000	1000	29349	29337	29470	29446	29368

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.b, v1.b }[1], [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0056

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140053	1086	1	0	0	1	0	1	0	0	0	0	47	0	0	1	140038	0	139598	25	90106	50100	30006	10000	40100	30000	10000	1237008	5331584	16114812	0	140029	140053	140056	130807	3	131159	80100	30200	10000	30000	60200	20098	50000	140041	140041	1	1	50201	100	99	0	100	40100	10000	10000	100	10001	1	1	10001	1	0	1	10000	1	1	1	1	1	0	3210	1	121	1	1	139717	50000	6	9	0	10000	20000	50100	140057	140054	140042	140051	140042
70204	140035	1085	1	0	0	0	0	0	0	0	0	0	11	0	0	0	140041	0	139598	25	90103	50100	30006	10000	40100	30000	10000	1236903	5330042	16115726	0	140026	140056	140056	130727	3	131159	80100	30200	10000	30000	60200	20000	50000	140056	140041	36	1	50201	100	99	0	100	40100	10000	10000	100	10001	1	1	10001	0	0	1	10001	1	1	1	1	1	0	3210	1	121	1	1	139723	50009	9	9	9	10000	20000	50100	140057	140045	140152	140042	140042
70204	140056	1085	1	0	1	1	0	0	0	0	0	0	53	0	0	0	140137	4	139649	25	90106	50108	30006	10000	40100	30000	10000	1237008	5330042	16114109	1	140029	140117	140058	130736	3	131162	80400	30200	10000	30000	60200	20000	50000	140047	140047	1	1	50201	100	99	0	100	40100	10000	10000	100	10001	1	1	10002	0	1	22	10001	1	1	1	1	0	0	3210	1	80	1	1	139713	50000	9	6	0	10000	20000	50100	140057	140057	140057	140144	140057
70204	140056	1086	1	0	1	1	0	0	0	1	0	0	1	0	0	0	140130	0	139750	25	90103	50100	30003	10000	40100	30000	10000	1237008	5331547	16106822	0	140032	140053	140056	130742	3	131159	80399	30200	10000	30000	60200	20000	50000	140056	140047	1	1	50201	100	99	0	100	40100	10000	10000	100	10002	1	1	10001	0	0	16	10000	1	1	1	1	0	0	3210	1	121	1	1	139726	50000	9	0	6	10000	20000	50100	140054	140057	140057	140157	140054
70204	140056	1085	0	0	1	1	0	1	0	0	0	0	2	0	0	0	140124	0	139612	25	90103	50100	30003	10000	40100	30000	10000	1237008	5331625	16120441	0	140032	140050	140056	130751	3	131159	80100	30200	10000	30000	60200	20000	50000	140053	140053	1	1	50201	100	99	4	100	40100	10000	10000	100	10002	2	1	10002	0	1	1	10000	1	1	1	1	2	0	3235	1	121	1	1	139729	50000	6	6	9	10000	20000	50100	140057	140057	140057	140057	140054
70204	140041	1125	1	0	1	0	0	1	0	0	1	0	1	0	0	0	140042	0	139552	25	90106	50100	30006	10000	40100	30234	10000	1237008	5333893	16115726	0	140032	140154	140050	130833	3	131138	80100	30200	10000	30000	60200	20000	50000	140056	140053	1	1	50201	100	99	0	100	40100	10000	10000	100	10002	2	1	10001	0	0	1	10000	1	1	1	1	0	0	3236	1	121	1	4	139723	50000	0	0	10	10000	20000	50100	140057	140057	140059	140057	140042
70204	140053	1086	1	0	1	2	0	0	1	0	0	0	2	0	0	0	140039	0	139615	25	90106	50100	30006	10000	40100	30000	10000	1237008	5331667	16114812	0	140032	140112	140074	130757	3	131159	80100	30200	10000	30000	60200	20000	50000	140056	140056	1	1	50201	100	99	0	100	40100	10000	10000	100	10002	2	0	10002	1	0	1	10000	0	1	1	1	0	0	3210	1	121	1	3	139725	50000	9	6	6	10000	20000	50100	140057	140052	140051	140149	140054
70204	140053	1085	1	0	0	0	0	0	0	0	0	0	398	0	0	0	140036	0	139598	25	90106	50100	30006	10000	40100	30000	10000	1239824	5331547	16119684	0	140032	140056	140056	130718	3	131159	80100	30200	10000	30000	60200	20000	50000	140056	140053	1	1	50201	100	99	0	100	40100	10000	10000	100	10001	1	1	10004	0	0	1	10000	1	1	1	1	0	1	3210	0	121	1	1	139705	50010	9	6	9	10000	20000	50100	140409	140152	140143	140048	140057
70204	140145	1087	1	1	1	0	0	2	0	0	2	2	398	88	0	0	140331	0	139749	82	90137	50148	30011	10004	40525	30357	10080	1252423	5336681	16119974	0	140219	140156	140341	130838	364	132567	88517	30445	10040	30358	60696	20162	50402	140323	140243	4	1	50201	100	99	0	100	40100	10000	10000	100	10005	3	0	10007	0	0	6441	10003	1	1	1	0	0	0	3210	1	121	1	1	139726	50000	9	6	9	10000	20000	50100	140057	140057	140054	140042	140042
70204	140057	1086	1	0	1	0	0	1	0	0	0	0	2	0	0	0	140041	0	139595	25	90106	50100	30006	10000	40100	30000	10000	1237008	5331547	16115726	0	140032	140056	140056	130746	3	131159	80100	30200	10000	30000	60200	20000	50000	140050	140053	1	1	50201	100	99	0	100	40100	10000	10000	100	10001	1	1	10001	1	0	1	10000	1	1	1	0	0	0	3210	1	121	1	1	139713	50000	9	9	9	10000	20000	50100	140058	140042	140042	140057	140057

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5e	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140047	1124	0	0	1	0	0	0	0	0	0	16	0	0	0	0	140035	139650	25	90013	50010	30003	10002	40010	30000	10000	1245916	5333173	16114779	1	0	140026	140134	140082	130746	3	131209	80010	30020	10000	30000	60020	20000	50000	140050	140047	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	0	10000	1	1	0	3140	3	87	3	2	139722	50021	9	6	9	10000	20000	50010	140036	140048	140051	140036	140039
70024	140050	1125	0	0	0	0	0	0	0	0	0	13	0	1	0	0	140036	139650	25	90013	50010	30003	10000	40010	30000	10000	1245907	5332706	16114399	0	0	140023	140107	140089	130749	3	131209	80010	30020	10000	30000	60020	20000	50000	140050	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	0	1	0	3140	4	87	4	4	139722	50000	9	11	9	10000	20000	50010	140036	140051	140051	140051	140051
70024	140047	1124	0	0	0	0	0	0	0	0	0	13	0	0	0	0	140035	139650	25	90013	50010	30003	10001	40010	30000	10000	1245907	5335013	16114779	0	0	140026	140047	140160	130749	3	131206	80309	30020	10000	30000	60266	20000	50000	140050	140050	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	3225	10000	1	1	0	3164	3	87	3	3	139783	50000	0	9	9	10000	20000	50010	140051	140051	140052	140051	140051
70024	140051	1125	0	0	0	0	0	0	0	0	0	0	0	0	1	0	140035	139653	25	90013	50010	30003	10000	40010	30236	10079	1245907	5333285	16119238	0	0	140024	140204	140054	130781	3	131194	80010	30020	10000	30000	60260	20000	50000	140050	140131	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	3	10000	1	1	0	3140	3	87	2	2	139722	50000	9	0	9	10000	20000	50010	140051	140051	140037	140036	140238
70024	140052	1125	0	0	0	0	0	0	0	1	0	1	0	0	0	0	140032	139650	25	90013	50010	30003	10001	40161	30000	10000	1245898	5333096	16114779	0	0	140023	140131	140056	130734	3	131206	80010	30020	10000	30000	60020	20000	50000	140050	140035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	2	0	12	10000	1	1	0	3140	2	87	3	3	139722	50000	6	6	6	10000	20000	50010	140142	140149	140054	140140	140053
70024	140141	1125	0	0	0	0	0	1	1	0	0	1	0	0	0	0	140134	139653	54	90013	50010	30003	10000	40010	30000	10039	1245907	5333285	16114779	0	0	140026	140123	140053	130751	3	131215	80010	30020	10000	30000	60020	20000	50000	140051	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	1	0	3	10001	1	1	0	3140	3	87	3	3	139723	50000	9	4169	6	10000	20000	50010	140051	140098	140145	140054	140051
70024	140050	1125	0	0	0	0	0	0	0	1	0	112	0	0	0	0	140035	139647	25	90013	50010	30003	10000	40010	30000	10000	1245879	5333285	16114779	0	0	140023	140188	140146	130734	3	131209	80010	30020	10000	30000	60020	20000	50000	140050	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	3140	3	87	2	2	139719	50000	9	6	9	10000	20000	50010	140051	140051	140148	140051	140049
70024	140047	1124	0	0	0	0	0	0	0	0	0	13	0	0	0	0	140033	139650	25	90013	50020	30003	10000	40010	30000	10000	1245925	5335694	16114779	0	0	140105	140151	140040	130749	3	131209	80010	30020	10048	30124	60020	20000	50000	140047	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	1	0	0	10000	1	1	0	3140	2	87	3	2	139722	50000	9	6	9	10000	20000	50010	140051	140052	140152	140052	140051
70024	140050	1125	0	0	0	0	0	1	1	0	1	1	0	0	0	0	140033	139651	25	90013	50010	30003	10000	40010	30000	10000	1245906	5333327	16114779	0	0	140011	140100	140107	130751	3	131212	80304	30020	10000	30000	60020	20000	50000	140051	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	1	0	6350	10000	0	1	0	3140	3	87	3	2	139722	50000	7	0	9	10000	20000	50010	140051	140051	140036	140051	140036
70024	140106	1125	0	0	0	0	0	0	0	0	0	1	0	0	0	0	140035	139650	25	90013	50021	30000	10000	40010	30000	10000	1248314	5333173	16114779	0	0	140011	140140	140050	130749	3	131208	80010	30020	10041	30000	60020	20082	50000	140050	140050	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	2	0	9	10000	1	1	2	3186	3	87	3	4	141930	50031	9	6	9	10000	20000	50010	140245	140329	140232	140328	140428

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.b, v1.b }[1], [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0066

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	24	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140063	1125	1	1	0	1	0	0	0	0	88	0	0	140060	139597	25	90103	50100	30003	10000	40118	30027	10010	1231384	5332763	16118838	0	140050	140055	140075	130830	8	131270	80155	30227	10010	30027	60254	20020	50045	140075	140055	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	9	10000	1	1	0	0	3210	1	121	1	1	139745	50000	13	10	10	10000	20000	50100	140076	140066	140079	140066	140066
70204	140075	1086	0	0	0	0	1	0	0	1	0	0	0	140060	139618	25	90100	50100	30003	10000	40100	30000	10000	1237206	5332262	16117312	0	140031	140075	140075	130752	3	131178	80100	30200	10000	30000	60200	20000	50000	140177	140065	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	1	0	0	10000	1	1	0	0	3210	1	121	1	1	139745	50000	10	10	13	10000	20000	50100	140066	140076	140076	140076	140076
70204	140075	1086	0	0	0	0	0	0	0	13	0	0	0	140040	139617	25	90103	50100	30003	10000	40100	30000	10000	1237179	5332262	16116123	0	140031	140075	140075	130751	3	131178	80100	30200	10000	30000	60200	20000	50000	140075	140055	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	1	0	0	10000	1	1	0	0	3210	1	121	1	1	139745	50000	13	0	13	10000	20000	50100	140076	140076	140076	140076	140056
70204	140075	1125	0	0	0	0	0	0	0	7	0	0	0	140050	139617	25	90103	50100	30003	10000	40100	30000	10000	1245924	5331499	16116480	0	140031	140075	140075	130731	3	131178	80100	30200	10000	30000	60200	20000	50000	140075	140075	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	1	0	0	10000	1	0	0	0	3210	1	121	1	1	139745	50000	13	10	10	10000	20000	50100	140076	140066	140076	140076	140076
70204	140075	1125	0	0	0	0	0	0	0	13	0	0	0	140060	139617	25	90103	50100	30003	10000	40100	30000	10000	1237179	5332262	16116123	0	140031	140075	140075	130751	3	131178	80100	30200	10000	30000	60200	20000	50000	140075	140065	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	3	10000	1	1	0	0	3210	1	121	1	1	139735	50000	13	14	13	10000	20000	50100	140076	140080	140066	140076	140066
70204	140075	1125	0	0	0	0	0	0	0	13	0	0	0	140060	139617	25	90103	50100	30003	10000	40100	30000	10000	1237179	5331577	16116123	0	140051	140075	140065	130731	3	131178	80100	30200	10000	30000	60200	20000	50000	140075	140065	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	3	10000	0	1	0	0	3210	1	121	1	1	139745	50000	13	10	13	10000	20000	50100	140076	140076	140075	140076	140076
70204	140055	1125	0	0	0	0	0	0	0	12	0	0	0	140060	139597	25	90103	50100	30003	10000	40100	30000	10000	1237179	5332262	16117271	0	140051	140065	140075	130751	3	131178	80100	30200	10000	30000	60200	20000	50000	140065	140067	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	18	10035	1	0	0	0	3210	1	121	1	1	139745	50000	13	13	0	10000	20000	50100	140076	140066	140076	140078	140076
70204	140075	1125	0	0	0	0	0	0	0	16	88	1	0	140060	139620	43	90103	50100	30000	10000	40243	30000	10000	1237214	5332262	16116123	0	140117	140076	140075	130751	3	131178	80100	30200	10000	30000	60200	20000	50000	140075	140075	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	2	1	10000	0	0	0	10000	1	1	0	0	3210	1	121	1	1	139725	50000	13	13	13	10000	20000	50100	140076	140076	140076	140076	140076
70204	140065	1125	0	1	0	0	0	0	0	4	0	0	0	140069	139617	25	90103	50100	30000	10000	40100	30000	10000	1237088	5333777	16116123	0	140041	140157	140055	130751	3	131178	80100	30200	10000	30000	60442	20000	50000	140075	140055	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	1	0	3	10000	1	0	0	0	3210	1	121	1	1	139746	50000	0	10	13	10000	20000	50100	140076	140076	140076	140076	140076
70204	140076	1125	0	0	0	0	0	0	0	1	0	0	0	140060	139617	25	90103	50100	30003	10000	40100	30000	10000	1237083	5332221	16116123	0	140031	140075	140065	130759	3	131169	80100	30200	10000	30000	60200	20000	50000	140164	140072	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	0	1	0	0	3210	1	121	1	1	139745	50000	13	10	13	10000	20000	50100	140076	140056	140076	140076	140076

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0058

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70026	140253	1085	1	1	1	0	0	0	3	2	265	264	1	0	140426	139744	25	90045	50020	30007	10001	40151	30000	10080	1245979	5334317	16125796	140175	140058	140158	130757	44	131217	80010	30143	10040	30243	60020	20162	50205	140147	140055	3	1	50021	10	9	10	40010	10000	10000	0	10	10004	0	1	10002	0	0	2	3280	10002	1	1	0	3142	5	87	4	6	139708	50000	13	11	13	10000	20000	50010	140059	140063	140059	140059	140059
70024	140058	1086	1	0	0	0	0	1	0	0	1	0	0	0	140043	139658	25	90010	50010	30003	10000	40010	30000	10000	1245979	5333591	16115708	140034	140058	140058	130757	3	131217	80010	30020	10000	30000	60020	20000	50000	140055	140055	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	3142	5	87	3	6	139730	50000	13	11	14	10000	20000	50010	140059	140060	140059	140059	140059
70024	140058	1086	1	0	0	0	0	0	0	0	1	0	0	0	140043	139658	25	90013	50010	30000	10000	40010	30000	10000	1245979	5333591	16115974	140034	140058	140058	130758	3	131217	80357	30020	10000	30000	60020	20000	50000	140058	140058	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	3142	5	87	6	4	139708	50000	13	11	13	10000	20000	50010	140059	140059	140061	140037	140059
70024	140058	1085	1	0	0	0	1	0	0	0	1	0	0	0	140043	139636	25	90013	50010	30003	10000	40010	30000	10000	1245952	5333669	16115708	140012	140058	140058	130757	3	131217	80010	30020	10000	30000	60020	20000	50000	140058	140055	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	0	1	0	3142	4	87	4	5	139729	50000	13	17	13	10000	20000	50010	140059	140059	140037	140037	140059
70024	140058	1085	1	0	0	0	0	0	0	0	1	0	0	0	140043	139658	25	90013	50010	30003	10000	40010	30000	10000	1245979	5332745	16115708	140012	140058	140059	130754	3	131217	80010	30020	10000	30000	60020	20000	50000	140058	140055	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	1	0	3	10000	1	1	0	3142	5	87	4	4	139730	50000	13	11	13	10000	20000	50010	140059	140059	140056	140062	140059
70024	140058	1085	1	0	0	0	0	0	0	0	6	0	1	0	140043	139658	25	90013	50010	30003	10000	40010	30000	10000	1245979	5333591	16115942	140034	140058	140058	130757	3	131217	80010	30020	10000	30000	60020	20000	50000	140058	140058	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	0	0	3142	5	87	5	6	139708	50000	13	13	13	10000	20000	50010	140059	140061	140059	140059	140059
70024	140059	1086	1	0	0	0	0	0	0	0	1	0	0	0	140043	139658	25	90010	50010	30000	10000	40010	30000	10000	1245979	5333591	16115708	140034	140058	140058	130757	3	131217	80010	30020	10000	30000	60020	20000	50000	140058	140055	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	8	0	0	10000	1	1	0	3142	5	87	6	5	139727	50000	11	14	13	10000	20000	50010	140059	140059	140059	140059	140059
70024	140058	1086	1	0	0	0	0	0	0	0	1	0	1	0	140043	139638	25	90013	50010	30003	10000	40010	30000	10000	1245856	5333591	16113460	140012	140036	140058	130757	3	131217	80010	30020	10000	30000	60020	20000	50000	140058	140057	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	3142	4	87	3	4	139730	50000	13	13	13	10000	20000	50010	140154	140136	140153	140132	140292
70024	140341	1086	1	0	0	1	0	0	3	2	405	264	0	0	142392	139811	109	90043	50030	30012	10006	40292	30236	10078	1255247	5338855	16126496	140318	140251	140340	130832	43	131365	80907	30143	10121	30356	60508	20240	50604	140230	140333	2	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	9	10000	1	1	0	3142	6	87	4	4	139727	50000	13	11	13	10000	20000	50010	140059	140059	140059	140037	140059
70024	140060	1085	1	0	0	0	1	1	0	0	1	0	0	0	140043	139658	25	90013	50010	30003	10000	40010	30000	10000	1245856	5332745	16115708	140034	140058	140058	130759	3	131217	80010	30020	10000	30000	60020	20000	50000	140058	140058	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10002	1	0	0	3142	4	87	4	6	139730	50000	13	0	16	10000	20000	50010	140059	140037	140037	140059	140038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.b, v1.b }[1], [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	37	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6b	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst simd alu (9a)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	80042	621	0	1	0	1	1	0	0	22	0	0	0	0	80027	1	6	6	0	4	26	320148	80100	160000	80000	80100	160000	80000	4447133	3757696	9983591	0	0	80023	0	80042	80042	29924	0	3	29999	320100	200	80000	160000	200	160000	320000	80042	80042	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	20	80017	0	1	0	17	80016	6	1	15	23	0	15110	0	3	16	3	3	80039	1	80000	0	0	80000	320000	80100	80043	80043	80043	80043	80043
400204	80042	620	0	0	0	1	1	0	0	35	0	0	0	22	80027	1	6	6	0	0	26	320142	80100	160045	80000	80100	160000	80000	4447142	3757697	9984206	0	0	80023	0	80042	80042	29924	13	3	30000	320100	200	80000	160000	200	160000	320000	80042	80042	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	21	80018	0	0	0	0	80017	6	1	17	0	0	15110	0	3	16	3	3	80039	0	80000	13	10	80000	320000	80100	80043	80043	80043	80043	80043
400204	80042	620	0	0	0	1	1	0	0	22	0	0	0	99	80027	1	6	6	0	0	26	320161	80100	160045	80000	80100	160000	80000	4447126	3757676	9983185	0	0	80023	0	80042	80042	29924	0	3	29999	320100	200	80000	160000	200	160000	320000	80042	80042	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	19	80017	0	0	0	20	80016	0	1	15	21	0	15110	0	3	16	3	3	80039	1	80000	10	0	80000	320000	80100	80043	80043	80043	80043	80043
400204	80042	620	0	0	0	1	1	0	0	22	0	0	0	3	80027	1	6	0	0	4	26	320145	80100	160255	80000	80100	160000	80000	4447142	3757680	9983128	0	0	80023	0	80042	80042	29924	19	3	29999	320100	200	80000	160000	200	160000	320000	80042	80042	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	23	80017	0	0	0	17	80017	6	1	0	21	0	15110	0	3	16	3	3	80039	1	80000	13	13	80000	320000	80100	80043	80043	80043	80043	80043
400204	80042	620	0	0	0	1	0	0	0	34	0	0	0	0	80027	1	6	6	0	0	26	320161	80100	160102	80000	80100	160000	80000	4447142	3757692	9984221	0	0	80023	0	80042	80042	29924	0	27	29999	320100	200	80000	160000	200	160000	320000	80042	80186	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	19	80017	0	0	0	17	80016	6	0	15	21	0	15110	0	3	16	3	3	80039	0	80000	13	10	80000	320000	80100	80043	80043	80043	80043	80177
400204	80042	621	0	0	0	1	0	0	0	0	0	1	0	0	80027	1	6	6	0	0	26	320165	80100	160062	80000	80100	160000	80000	4446269	3757697	9983632	0	0	80023	0	80042	80184	29905	0	3	29999	320441	200	80000	160000	200	160000	320000	80042	80042	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	0	80017	0	1	0	14	80015	6	1	0	21	4	15110	0	3	16	3	3	80039	1	80000	0	10	80000	320000	80100	80043	80043	80043	80043	80043
400204	80042	620	0	0	0	1	1	0	0	22	0	0	0	3	80027	1	6	6	0	0	71	320145	80100	160000	80000	80100	160000	80000	4447142	3757669	9983185	0	5	80023	0	80042	80042	29924	0	3	29999	320100	200	80000	160000	200	160166	320000	80042	80042	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	19	80017	0	0	0	0	80017	0	1	0	21	0	15110	0	3	16	3	3	80039	1	80000	13	10	80000	320000	80100	80043	80043	80185	80043	80043
400204	80042	620	0	0	0	1	0	0	0	22	0	0	0	16	80169	0	6	0	0	0	26	320100	80100	160045	80000	80100	160000	80083	4446616	3757676	9983574	1	5	80023	0	80042	80042	29924	0	3	29999	320100	200	80000	160000	200	160000	320000	80042	80042	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80000	0	19	80017	0	0	0	17	80016	6	1	0	21	0	15110	0	3	16	3	3	80039	0	80000	13	10	80000	320000	80100	80043	80043	80043	80043	80043
400204	80042	620	0	0	0	1	1	0	0	25	0	0	0	0	80027	1	6	6	0	5	26	320147	80100	160000	80000	80100	160000	80000	4447142	3757676	9984160	0	0	80023	0	80042	80042	29924	123	3	29999	320100	200	80000	160000	200	160000	320000	80042	80042	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80083	0	19	80017	0	0	0	20	80016	6	1	0	21	0	15110	0	3	25	3	3	80159	0	80000	13	13	80000	320000	80100	80043	80043	80187	80043	80043
400204	80183	620	0	0	0	1	1	1	1	154	88	0	0	18	80170	1	6	6	0	44	26	320560	80184	160465	80000	80100	160000	80084	4447142	3757479	9980951	0	0	80133	0	80328	80183	29868	224	329	31386	327082	202	81411	162771	200	161494	320332	80042	80184	2	1	240201	100	99	100	100	80000	160000	80000	0	100	80169	2	19	80100	0	0	2	1196	80182	6	0	0	0	2	15136	0	4	23	3	3	80039	1	80166	13	10	80000	320000	80100	80043	80043	80043	80043	80043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	37	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst simd alu (9a)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	80191	621	2	0	1	0	1	1	0	2	132	176	1	66	12	80027	0	6	6	0	44	26	320748	80509	163401	81411	81424	162813	81329	4412157	3767981	9981601	12	1	0	80133	0	80187	80328	29890	220	27	30184	320343	20	80166	160166	20	160500	320330	80183	80467	2	1	240021	10	9	10	10	80000	160000	80000	0	10	80083	0	19	80267	0	0	2362	80083	6	1	0	0	2	12	15118	63	39	19	44	284	26	30	10	44	44	80152	1	80084	249	0	80000	320000	80010	80185	80184	80473	80186	80325
400024	80478	621	1	0	1	1	0	0	2	2	418	88	0	197	14	80027	1	6	6	0	4	26	320071	80010	160060	80000	80010	160000	80000	4446669	3757695	9982800	11	1	5	80023	0	80042	80042	29947	0	3	30021	320010	20	80000	160000	20	160000	320000	80042	80042	1	1	240021	10	9	10	10	80000	160000	80000	1	10	80000	0	0	80017	0	0	0	80017	6	1	0	0	0	0	15073	63	43	26	47	17	33	23	11	48	46	80039	0	80000	247	0	80000	320000	80010	80043	80043	80043	80043	80043
400024	80042	621	0	0	0	0	0	0	0	0	12	0	0	16	10	80027	1	6	6	0	0	26	320052	80010	160044	80000	80010	160000	80000	4446669	3757697	9983688	11	1	5	80023	0	80042	80042	29947	0	3	30021	320010	20	80000	160000	20	160000	320000	80042	80042	1	1	240021	10	9	10	10	80000	160000	80000	1	10	80000	0	19	80184	0	0	0	80000	0	1	15	21	0	0	15060	63	37	18	47	17	27	24	11	46	28	80039	0	80000	246	10	80000	320000	80010	80043	80043	80043	80043	80043
400024	80042	621	1	0	1	0	0	0	0	0	22	0	0	0	8	80027	0	0	6	0	0	26	320077	80010	160000	80000	80010	160000	80000	4446651	3757703	9983291	11	1	5	80023	0	80042	80042	29947	0	3	30022	320010	20	80000	160000	20	160000	320000	80042	80042	1	1	240021	10	9	10	10	80000	160000	80000	1	10	80000	0	19	80016	0	0	20	80016	6	1	0	0	0	0	15058	63	38	19	46	17	28	25	12	45	44	80039	0	80000	302	0	80000	320000	80010	80043	80043	80043	80043	80043
400024	80042	620	1	0	1	0	0	0	0	0	21	0	0	0	8	80027	1	6	6	0	0	26	320010	80010	160060	80000	80010	160000	80000	4446652	3757676	9983983	9	1	5	80023	0	80042	80042	29947	0	3	30021	320010	20	80000	160000	20	160000	320000	80042	80042	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	0	80015	0	0	0	80000	6	1	15	21	0	0	15062	63	36	18	43	17	28	24	11	47	45	80039	0	80000	236	13	80000	320000	80010	80043	80043	80043	80043	80043
400024	80042	620	1	0	0	0	0	0	0	0	23	0	0	0	10	80027	1	0	6	0	4	26	320075	80010	160047	80000	80010	160000	80000	4446669	3757676	9983290	10	1	5	80023	0	80042	80042	29947	0	3	30021	320010	20	80000	160000	20	160000	320000	80042	80042	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	19	80017	0	0	16	80000	6	1	15	21	0	0	15062	63	37	19	45	17	28	24	11	43	25	80039	0	80000	230	0	80000	320000	80010	80043	80043	80043	80043	80043
400024	80042	621	0	0	1	0	0	0	0	0	0	0	0	10	9	80027	1	6	6	0	4	26	320077	80010	160045	80000	80010	160000	80000	4446669	3757676	9982624	8	1	5	80023	0	80042	80042	29947	0	3	30021	320010	20	80000	160000	20	160000	320000	80042	80042	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	19	80015	0	0	26	80019	6	1	15	21	0	0	15065	70	36	19	46	17	29	25	11	44	44	80039	0	80000	252	0	80000	320000	80010	80043	80043	80043	80043	80043
400024	80042	620	1	0	0	0	0	0	0	0	23	0	0	0	10	80027	1	6	6	0	0	26	320069	80010	160053	80000	80010	160000	80000	4446669	3757695	9983918	10	1	5	80023	0	80042	80042	29947	0	3	30021	320010	20	80000	160000	20	160000	320000	80042	80042	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	21	80016	0	0	17	80000	6	1	15	21	0	0	15062	60	44	24	45	17	27	24	14	23	43	80039	0	80000	234	10	80000	320000	80010	80043	80043	80043	80043	80043
400024	80042	620	0	0	1	0	0	0	0	0	0	0	0	0	14	80027	1	6	6	0	0	26	320054	80010	160048	80000	80010	160000	80000	4446669	3757703	9982662	12	1	5	80023	0	80042	80042	29947	0	3	30021	320010	20	80000	160000	20	160000	320000	80042	80042	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	0	80017	0	0	16	80000	6	0	15	21	0	0	15060	63	40	21	49	17	28	26	12	26	48	80039	0	80000	255	0	80000	320000	80010	80043	80043	80043	80043	80043
400024	80042	621	1	0	0	0	0	0	0	0	23	0	0	0	9	80027	1	6	6	0	0	26	320010	80010	160000	80000	80010	160000	80000	4446669	3757676	9984003	12	1	5	80023	0	80183	80042	29947	0	3	30021	320010	20	80000	160000	20	160000	320000	80042	80042	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80000	0	21	80017	0	0	17	80017	6	0	17	19	0	0	15062	63	36	19	43	17	26	24	11	46	42	80039	1	80000	230	10	80000	320000	80010	80043	80043	80043	80043	80043

LD2 (single, post-index, B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations