Firestorm: LD2 (single, post-index, D) measurements

Code:

  ld2 { v0.d, v1.d }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.006

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.003

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	df	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
63005	28828	231	1	24	1	0	19	1	0	0	0	0	4	0	0	0	4757	28458	0	1	0	0	16812	4002	1000	2002	1000	1000	2000	1000	5000	5001	23952	12	22708	28669	28733	3	10	4000	1000	2000	2000	4000	28610	28663	1	1	61001	1000	1000	0	1002	2	2	1003	0	0	1	82	1000	2	1	3	1	0	0	13141	9405	6879	3160	10	52	20071	3159	3810	19	54	56	1	28187	1000	15498	12709	13931	1000	2000	1000	28796	28907	28886	28840	28813
63004	28841	230	0	21	1	0	17	0	0	0	0	0	5	0	0	0	4683	28409	0	0	0	0	16727	4008	1000	2008	1000	1000	2000	1000	5000	5000	23856	11	22777	28605	28742	3	10	4000	1000	2000	2000	4000	28703	28738	1	1	61001	1000	1000	0	1001	2	0	1004	0	0	2	97	1001	2	1	0	1	1	149	13253	9419	6942	3106	8	55	20187	3310	3802	18	54	53	1	28202	1000	15490	12584	13604	1000	2000	1000	28855	28811	28777	28899	28777
63004	28897	231	1	21	0	0	15	1	0	0	0	0	1	0	0	0	4731	28380	0	0	1	0	16760	4006	1000	2000	1000	1000	2000	1000	5000	5000	23932	8	22680	28723	28836	3	10	4000	1000	2000	2000	4000	28713	28728	1	1	61001	1000	1000	0	1002	2	3	1003	0	0	1	82	1003	3	2	0	1	1	0	13125	9423	6913	3126	12	51	20122	3226	3808	17	56	53	1	28262	1000	15740	13004	13868	1000	2000	1000	28846	28805	28792	28956	28973
63004	28835	231	0	20	1	0	22	1	1	0	0	0	3	0	0	0	4720	28414	1	1	0	0	16826	4008	1000	2006	1000	1000	2000	1000	5000	5036	24001	5	22758	28697	28809	3	10	4000	1000	2000	2000	4000	28715	28680	1	1	61001	1000	1000	0	1002	2	3	1002	0	0	0	4	1001	1	1	0	1	1	0	13197	9337	6976	3204	8	54	20116	3197	3816	24	56	58	2	28223	1000	15774	12407	13986	1000	2000	1000	28671	28795	28748	28906	28830
63004	28796	231	1	22	1	0	19	1	0	0	0	0	13	0	1	0	4705	28492	0	0	0	0	16709	4002	1000	2006	1000	1000	2000	1000	5000	5002	23888	2	22650	28794	28708	3	10	4000	1000	2000	2000	4000	28640	28731	1	1	61001	1000	1000	0	1000	2	4	1001	0	1	0	97	1003	2	4	2	1	1	0	13469	9414	6957	3221	10	60	20328	3245	3808	16	58	56	1	28211	1000	15590	12531	13896	1000	2000	1000	28739	28841	28836	28873	28899
63004	28912	231	1	22	1	0	16	0	0	0	0	0	1	0	0	0	4711	28510	0	1	1	0	16737	4002	1000	2006	1000	1000	2000	1000	5000	5000	23820	3	22741	28657	28947	3	10	4000	1000	2000	2000	4000	28755	28819	1	1	61001	1000	1000	0	1002	0	3	1002	0	0	2	106	1000	2	1	0	0	1	0	13014	9424	6933	3134	4	49	20177	3158	3818	19	51	51	1	28252	1000	15429	12550	13876	1000	2000	1000	28813	28821	28960	28892	28829
63004	28856	232	1	13	0	0	22	0	0	0	0	0	1	0	0	0	4669	28521	0	0	0	0	16726	4003	1000	2006	1000	1000	2000	1000	5000	5000	23904	0	22734	28654	28805	3	10	4000	1000	2000	2000	4000	28716	28766	1	1	61001	1000	1000	0	1002	2	3	1003	0	0	1	97	1000	3	2	3	1	0	0	13291	9435	6929	3123	12	54	20308	3183	3813	14	51	55	1	28363	1000	15397	12633	13817	1000	2000	1000	28832	28730	28808	28844	28828
63004	28841	232	1	20	0	0	20	1	0	0	0	0	3	0	0	0	4819	28385	0	0	0	0	16676	4006	1000	2006	1000	1000	2000	1000	5000	5002	23900	5	22721	28640	28795	3	10	4000	1000	2000	2000	4000	28747	28770	1	1	61001	1000	1000	0	1002	2	0	1001	0	0	0	113	1000	2	1	0	1	1	0	13178	9440	6904	3140	9	54	20145	3221	3813	18	49	52	2	28123	1000	15768	12564	13856	1000	2000	1000	28671	28767	28850	28813	28695
63004	28945	230	1	22	1	0	19	1	0	0	0	0	4	0	0	0	4661	28328	0	0	1	0	16615	4006	1000	2002	1000	1000	2000	1000	5000	5089	23853	16	22685	28700	29035	3	10	4000	1000	2000	2000	4000	28755	28749	1	1	61001	1000	1000	0	1002	2	0	1000	0	0	0	141	1000	3	1	0	1	0	0	13074	9544	6898	3118	8	54	20222	3229	3810	15	59	52	1	28201	1000	15659	12636	13802	1000	2000	1000	28795	28830	28895	28852	28804
63004	28786	231	1	19	1	0	19	0	0	0	0	0	1	0	0	0	4756	28473	0	0	0	0	16763	4002	1000	2008	1000	1000	2000	1000	5000	5001	23894	1	22710	28652	28855	3	10	4000	1000	2000	2000	4000	28835	28642	1	1	61001	1000	1000	0	1007	2	0	1005	0	0	1	89	1002	2	1	4	1	2	0	13166	9309	6943	3164	9	46	20242	3172	3807	20	54	49	1	28194	1000	15811	12672	13705	1000	2000	1000	28704	28848	28754	28719	28923

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.d, v1.d }[1], [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140151	1085	0	0	1	0	0	0	0	0	1	88	0	0	0	0	140040	0	0	141034	25	90103	50100	30003	10000	40100	30000	10049	1237300	5330902	16114908	140030	140035	140056	130711	3	131157	80399	30200	10000	30000	60200	20000	50000	140054	140035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	3	10000	1	0	0	0	0	3210	1	121	1	1	139787	50000	13	13	13	10000	20000	50100	140036	140036	140055	140055	140036
70204	140035	1086	0	0	0	0	0	0	0	0	13	0	0	0	0	0	140039	0	0	139596	25	90103	50100	30003	10000	40100	30000	10000	1236990	5331471	16114560	140030	140054	140035	130730	3	131157	80100	30200	10000	30000	60200	20000	50000	140054	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3210	1	121	1	1	139744	50000	13	13	13	10000	20000	50100	140055	140055	140055	140388	140055
70204	140054	1086	0	0	0	0	0	0	0	0	1	0	0	0	0	0	140036	0	0	139641	25	90103	50100	30003	10000	40100	30000	10000	1236990	5331471	16114560	140079	140051	140035	130711	3	131157	80396	30200	10000	30000	60200	20096	50000	140054	140071	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10001	0	0	1	10001	1	1	1	0	0	3210	1	121	1	1	139714	50011	13	10	13	10000	20000	50100	140036	140055	140148	140052	140056
70204	140054	1085	0	0	0	0	0	0	0	0	1	0	0	0	0	0	140133	0	0	139620	25	90100	50100	30003	10000	40100	30000	10000	1236990	5331509	16113968	140102	140035	140054	130712	3	131157	80100	30200	10000	30000	60200	20000	50000	140054	140054	2	1	50201	100	99	100	40100	10000	10000	0	100	10003	2	1	10003	0	0	3255	10001	1	0	1	0	7	3257	1	136	1	3	141865	50020	0	10	13	10000	20000	50100	140225	140334	140239	140215	140248
70204	140335	1087	0	0	1	2	0	0	2	2	396	88	0	0	0	2	140311	0	0	139645	111	90151	50133	30016	10002	40408	30241	10078	1248720	5333559	16118935	140099	140038	140051	130730	3	131260	80100	30200	10000	30000	60200	20000	50000	140054	140054	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	1	0	0	10000	1	0	1	0	0	3210	1	121	1	1	139729	50000	11	13	13	10000	20000	50100	140055	140055	140055	140055	140055
70204	140054	1086	0	0	0	0	0	0	0	0	1	0	0	0	0	0	140039	0	0	139593	25	90103	50100	30003	10000	40100	30000	10000	1236990	5331471	16114560	140030	140054	140054	130730	3	131157	80100	30200	10000	30000	60200	20000	50000	140054	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3210	1	121	1	1	139772	50000	10	13	13	10000	20000	50100	140053	140055	140036	140052	140055
70204	140055	1085	0	0	0	0	0	0	0	0	13	0	0	0	0	0	140039	0	0	139596	25	90103	50100	30003	10000	40100	30000	10000	1236990	5331357	16114560	140030	140036	140054	130711	3	131138	80100	30200	10000	30000	60200	20000	50000	140054	140035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	10000	1	0	1	0	0	3210	1	121	1	1	139883	50000	11	10	10	10000	20000	50100	140060	140062	140060	140060	140044
70204	140059	1086	0	0	0	0	0	0	0	0	2	0	0	0	0	0	140039	0	0	139596	25	90100	50100	30003	10000	40100	30000	10000	1236972	5330746	16114560	140030	140060	140054	130730	3	131158	80100	30200	10000	30000	60200	20000	50000	140054	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	3	10000	1	0	1	0	0	3210	1	121	1	1	139728	50000	13	10	10	10000	20000	50100	140055	140055	140055	140055	140055
70204	140054	1086	0	0	0	0	0	0	0	0	1	0	0	0	0	0	140037	0	0	139593	25	90103	50100	30003	10000	40100	30000	10000	1236999	5330746	16114560	140027	140054	140054	130730	3	131138	80100	30200	10000	30000	60200	20000	50000	140055	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3210	1	121	1	1	139728	50000	13	10	0	10000	20000	50100	140036	140036	140055	140055	140036
70204	140054	1086	0	0	0	0	0	0	0	0	13	0	0	0	0	0	140039	0	0	139596	25	90103	50100	30003	10000	40100	30000	10000	1236990	5331471	16114560	140030	140054	140055	130711	3	131157	80100	30200	10000	30000	60200	20000	50000	140054	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	1	0	3	10000	1	0	1	0	0	3210	1	121	1	1	139806	50000	0	13	10	10000	20000	50100	140055	140055	140055	140055	140055

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140051	1085	0	1	0	0	0	0	0	10	0	0	0	0	140039	139635	25	90013	50010	30003	10000	40010	30000	10000	1245943	5333561	16115181	1	0	140030	140054	140054	130753	3	131213	80010	30020	10000	30000	60020	20000	50000	140051	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	3140	0	0	4	87	4	4	139726	50000	10	0	0	10000	20000	50010	140055	140036	140055	140055	140055
70024	140051	1085	0	0	0	0	0	0	0	1	0	0	0	0	140036	139635	25	90013	50010	30000	10000	40010	30000	10000	1245943	5332706	16115181	0	0	140030	140054	140054	130753	3	131213	80010	30020	10000	30000	60020	20000	50000	140035	140054	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	0	1	0	0	0	3140	0	0	4	87	3	4	139738	50000	15	13	13	10000	20000	50010	140036	140055	140055	140055	140036
70024	140035	1086	0	0	0	0	0	0	0	1	0	0	0	0	140039	139635	25	90013	50010	30003	10000	40010	30000	10000	1245943	5333327	16113697	0	0	140030	140054	140035	130734	3	131213	80010	30020	10000	30000	60020	20000	50000	140054	140052	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	1	0	0	10002	1	1	0	0	0	3140	0	0	3	87	4	4	139726	50000	13	13	13	10000	20000	50010	140058	140036	140056	140055	140037
70024	140054	1085	0	1	0	0	0	0	0	1	0	0	0	0	140040	139654	25	90010	50010	30003	10000	40010	30000	10000	1245943	5333441	16119298	1	0	140030	140054	140054	130755	3	131213	80010	30020	10000	30000	60020	20000	50000	140111	140044	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	6	10000	1	1	0	0	0	3140	0	0	5	87	3	5	139729	50000	13	10	13	10000	20000	50010	140036	140055	140055	140055	140036
70024	140054	1086	0	1	0	0	0	0	0	19	0	0	0	0	140039	139655	25	90010	50010	30003	10002	40010	30000	10000	1245961	5333441	16115181	0	0	140030	140054	140054	130734	3	131213	80010	30020	10000	30000	60020	20000	50000	140054	140035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	1	0	0	10000	1	1	0	0	0	3140	0	0	4	87	12	15	139726	50000	13	13	13	10000	20000	50010	140055	140055	140055	140053	140052
70024	140054	1086	0	0	0	0	0	1	0	13	0	1	0	0	140039	139657	25	90025	50010	30000	10000	40010	30000	10000	1245943	5333441	16115181	1	0	140030	140035	140150	130753	3	131213	80010	30143	10000	30000	60020	20000	50000	140054	140054	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	3140	0	0	4	87	5	5	139801	50000	0	13	13	10000	20000	50010	140055	140055	140055	140058	140055
70024	140054	1086	0	0	0	0	0	0	0	97	0	1	0	0	140039	139654	25	90013	50010	30007	10000	40010	30000	10000	1245847	5333441	16115181	0	0	140030	140054	140035	130777	3	131213	80010	30020	10000	30121	60020	20000	50000	140054	140054	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	1	0	0	10000	1	0	0	0	1	3140	0	0	4	87	5	6	139729	50000	13	0	13	10000	20000	50010	140057	140055	140055	140055	140149
70024	140054	1086	0	0	0	0	0	0	0	1	0	0	0	0	140020	139635	25	90013	50010	30007	10000	40010	30000	10000	1245943	5333441	16115181	0	0	140030	140054	140054	130753	3	131213	80010	30020	10000	30000	60266	20000	50000	140054	140054	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	0	1	10000	0	0	9	10000	1	1	0	0	0	3140	0	0	4	87	4	4	139726	50000	0	10	0	10000	20000	50010	140052	140055	140037	140036	140135
70024	140051	1086	0	0	0	0	1	0	0	1	0	0	0	0	140133	139654	134	90013	50020	30130	10022	40292	30000	10197	1250289	5335263	16115181	0	0	140030	140159	140229	130777	320	132325	80917	30266	10121	30362	60506	20162	50805	140251	140323	4	1	50021	10	9	10	40010	10000	10000	0	10	10005	2	1	10001	0	2	3215	10002	1	1	2	0	0	3186	0	0	5	110	5	4	139943	50010	13	10	13	10000	20000	50010	140150	140414	140240	140242	140307
70024	140038	1086	0	1	0	0	0	0	0	1	0	0	0	0	140040	139654	25	90013	50010	30003	10000	40010	30000	10000	1245943	5333517	16115181	1	5	140030	140054	140054	130753	3	131214	80010	30020	10000	30000	60020	20000	50000	140054	140054	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	0	1	0	0	0	3140	5	0	5	87	5	3	139726	50000	13	13	13	10000	20000	50010	140056	140055	140055	140055	140036

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2 { v0.d, v1.d }[1], [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0075

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140070	1086	0	1	0	0	0	0	0	1	0	0	0	140053	139565	25	90103	50100	30007	10000	40254	30120	10000	1244902	5331579	16116236	1	140042	0	140063	140066	130739	3	131207	80100	30200	10000	30000	60200	20000	50000	140063	140066	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	3	10000	1	1	0	0	3210	1	121	1	1	139735	50000	9	9	0	10000	20000	50100	140064	140064	140066	140064	140064
70204	140055	1086	0	0	0	0	0	0	2	541	0	0	0	140040	139565	25	90103	50100	30003	10000	40100	30000	10000	1244902	5331917	16116236	1	140031	0	140063	140063	130739	3	131207	80100	30200	10000	30000	60200	20000	50000	140063	140067	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	15	0	3	10000	1	1	0	0	3210	1	121	1	1	139735	50000	9	9	9	10000	20000	50100	140064	140067	140064	140057	140064
70204	140063	1086	0	0	0	0	0	0	0	13	0	0	0	140048	139565	54	90103	50270	30164	10001	40100	30000	10078	1244938	5331499	16116236	0	140042	0	140063	140063	130809	3	131207	80100	30200	10040	30000	60200	20000	50000	140063	140067	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	3	10000	1	0	0	0	3210	1	80	1	1	139799	50000	9	9	9	10000	20000	50100	140070	140064	140067	140064	140064
70204	140063	1085	0	0	0	0	0	0	0	0	0	0	0	140048	139565	109	90103	50100	30000	10000	40100	30000	10000	1237096	5331499	16114980	0	140031	0	140056	140063	130739	3	131207	80100	30200	10000	30000	60200	20000	50000	140063	140063	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10006	0	0	0	10000	1	1	0	0	3210	1	80	1	1	139802	50000	0	6	9	10000	20000	50100	140065	140056	140064	140064	140064
70204	140063	1085	0	0	0	0	0	1	0	13	0	0	0	140048	139565	53	90100	50100	30000	10000	40100	30000	10000	1237083	5330530	16116236	0	140039	0	140150	140063	130739	3	131207	80100	30200	10000	30000	60200	20000	50000	140063	140055	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	3236	1	121	1	1	139735	50000	9	6	9	10000	20000	50100	140064	140064	140064	140064	140057
70204	140063	1086	1	0	0	0	0	0	0	1	0	0	0	140048	139563	25	90103	50100	30003	10000	40100	30000	10000	1244902	5330530	16116236	0	140040	0	143390	141010	130739	3	131207	80100	30325	10000	30000	60200	20000	50000	140055	140066	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10001	0	0	0	10000	0	1	0	0	3210	1	80	1	2	139735	50000	9	6	9	10000	20000	50100	140056	140064	140064	140064	140064
70204	140063	1086	0	0	0	1	0	1	0	1	0	0	0	140048	139565	25	90103	50100	30003	10000	40100	30000	10000	1237088	5330530	16114980	0	140039	0	140066	140055	130739	3	131207	80100	30200	10000	30000	60200	20000	50000	140063	140055	1	1	50202	100	99	100	40100	10000	10000	1	100	10000	0	0	10000	0	0	0	10000	1	1	0	0	3210	1	121	1	1	139738	50000	9	6	6	10000	20000	50100	140064	140064	140064	140064	140056
70204	140063	1086	0	0	0	0	0	0	0	1	0	0	0	140133	139565	25	90103	50100	30003	10000	40100	30000	10000	1244902	5332056	16116470	0	140045	0	140063	140066	130739	3	131237	80100	30200	10000	30000	60200	20000	50000	140055	140063	1	1	50201	100	99	100	40100	10000	10000	1	100	10002	0	1	10000	1	0	0	10000	1	1	0	0	3210	1	80	1	1	139735	50000	9	9	9	10000	20000	50100	140064	140119	140107	140064	140064
70204	140066	1085	0	0	0	1	0	0	0	13	0	0	0	140051	139565	25	90103	50114	30003	10000	40100	30000	10000	1237083	5330530	16116236	0	140041	0	140063	140066	130813	3	131208	80437	30470	10000	30000	60200	20000	50000	140063	140066	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	0	10000	0	0	0	10000	1	1	0	0	3257	1	108	2	1	139800	50060	9	9	9	10000	20000	50100	140256	142584	142779	142392	140246
70205	140331	1087	0	0	0	0	0	3	2	133	358	0	1	142406	139702	140	90130	50147	30011	10004	40544	30232	10118	1250318	5332497	16127126	0	140265	0	140273	140343	130829	29	131337	80721	30562	10081	30241	60940	20158	50603	140157	140346	3	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	1	0	0	10000	1	1	0	0	3210	1	80	1	1	139735	50000	9	0	9	10000	20000	50100	140064	140066	140067	140066	140066

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	24	3a	3f	4d	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140056	1086	0	0	0	0	0	0	0	0	1	0	0	0	0	140040	139652	0	25	90013	50010	30003	10000	40010	30000	10000	1245925	5332745	16115004	140025	140052	140057	130751	0	3	131198	80010	30020	10000	30000	60020	20000	50000	140049	140049	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	0	3140	6	87	10	9	139724	50000	0	0	0	10000	20000	50010	140053	140050	140053	140037	140050
70024	140052	1085	0	0	0	0	0	0	0	0	0	0	0	0	0	140037	139649	0	25	90013	50010	30003	10000	40010	30000	10000	1245925	5333361	16115004	140028	140052	140052	130751	0	3	131208	80010	30020	10000	30000	60020	20000	50000	140052	140049	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	0	0	0	0	0	0	0	0	3140	10	87	7	9	139721	50000	0	0	9	10000	20000	50010	140053	140053	140053	140053	140053
70024	140052	1085	0	0	0	0	1	1	0	0	1	0	0	0	0	140037	139652	0	25	90013	50010	30003	10000	40010	30000	10000	1245925	5333249	16113460	140028	140052	140052	130751	0	3	131211	80010	30020	10000	30000	60020	20000	50000	140052	140049	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	0	3140	11	87	10	7	139724	50000	6	6	0	10000	20000	50010	140050	140053	140053	140053	140037
70024	140036	1085	0	0	0	0	0	0	0	0	1	0	0	0	0	140037	139652	0	25	90013	50010	30003	10000	40010	30000	10000	1245925	5333553	16119747	140028	140057	140052	130735	0	3	131211	80010	30020	10000	30000	60020	20000	50000	140052	140036	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	0	0	0	3140	8	87	6	9	139724	50000	6	6	9	10000	20000	50010	140053	140053	140053	140053	140050
70024	140049	1086	0	0	0	0	0	0	0	0	1	0	0	0	0	140037	139652	0	25	90013	50010	30003	10000	40010	30000	10000	1245925	5333361	16115004	140028	140052	140053	130748	0	3	131198	80010	30020	10000	30000	60020	20000	50000	140052	140036	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	0	3140	10	87	8	8	139721	50000	0	6	6	10000	20000	50010	140050	140050	140050	140050	140192
70024	140049	1085	0	0	0	0	0	0	0	0	1	0	0	0	0	140037	139650	0	25	90044	50010	30024	10014	43966	31650	10000	1245925	5333996	16116288	140070	140049	140052	130751	0	34	131218	80010	30020	10000	30000	60020	20000	50246	140103	140175	4	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	1	0	3140	9	87	9	9	139725	50000	6	6	9	10000	20000	50010	140050	140037	140050	140037	140050
70024	140733	1089	0	0	0	0	0	0	0	1	6	0	0	0	0	140037	139652	0	25	90013	50010	30003	10000	40010	30000	10000	1245897	5332745	16115004	140103	140079	140050	130751	0	3	131211	80010	30161	10000	30000	60020	20000	50000	140052	140049	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	2	1	10002	3	0	9	10000	1	0	1	0	0	0	0	0	3140	10	87	9	9	139726	50000	9	8	9	10000	20000	50010	140053	140054	140053	145094	145300
70025	145807	1142	0	1	0	1	1	1	71	73	5809	0	0	0	0	140037	139652	0	25	90010	50010	30000	10000	40010	30000	10000	1245925	5333361	16115004	140028	140049	140105	130798	0	3	131211	80010	30020	10000	30000	60020	20000	50000	140052	140049	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	9	10000	1	0	0	0	0	0	0	0	3140	7	87	6	10	139725	50000	9	9	9	10000	20000	50010	140050	140053	140053	140053	140050
70024	140052	1049	0	0	0	0	1	1	0	0	13	0	0	0	0	140034	139652	0	25	90013	50010	30000	10000	40010	30000	10000	1245897	5335816	16115352	140028	140108	140059	130748	0	3	131211	80010	30020	10000	30000	60020	20000	50000	140059	140049	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	3	10000	1	0	1	0	0	0	0	0	3140	6	87	10	7	139724	50000	9	9	6	10000	20000	50010	140038	140041	140050	140050	140053
70024	140052	1049	0	0	0	0	0	0	0	0	1	0	0	1	0	140037	139649	0	25	90013	50010	30003	10000	40010	30000	10000	1245897	5333361	16115004	140028	140049	140126	130751	0	3	131211	80010	30020	10000	30000	60020	20000	50000	140050	140049	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	1	0	6	10000	1	0	0	0	0	0	0	0	3140	9	87	9	9	139724	50000	0	0	9	10000	20000	50010	140053	140037	140053	140098	140050

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6], x8
  movi v0.16b, 0
  movi v1.16b, 0
  ld2 { v0.d, v1.d }[1], [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	37	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst simd alu (9a)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	80042	620	1	0	1	0	1	1	0	0	31	0	0	0	0	27	0	80027	1	6	6	0	4	26	320161	80100	160077	80000	80100	160000	80000	4446566	3757484	9984465	0	80023	80042	80042	29893	20	3	29999	320100	200	80000	160000	200	160000	320358	80042	80042	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80007	7	23	80025	0	1	1	25	80019	6	1	25	23	7	1	15110	1	16	2	1	80039	0	80000	9	9	80000	320000	80100	80043	80043	80043	80043	80043
400204	80042	620	1	0	0	1	0	0	0	0	33	0	0	0	0	27	0	80027	1	6	6	0	0	26	320160	80100	160126	80000	80100	160000	80000	4446566	3757354	9984548	0	80023	80042	80042	29920	26	3	29999	320100	200	80000	160000	200	160000	320000	80042	80042	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80007	7	23	80025	0	1	0	30	80018	6	1	28	23	7	1	15110	1	16	2	1	80039	0	80000	9	0	80000	320000	80100	80043	80043	80043	80043	80043
400204	80042	620	1	0	0	1	0	0	0	0	31	0	0	0	0	10	0	80027	1	6	0	0	4	26	320112	80100	160090	80000	80100	160000	80000	4446522	3757059	9984408	0	80023	80042	80042	29924	24	3	29999	320100	200	80000	160000	200	160000	320000	80042	80042	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80008	8	23	80025	0	1	0	26	80000	0	0	26	23	6	0	15110	2	16	1	2	80039	0	80000	9	9	80000	320000	80100	80043	80178	80043	80043	80043
400204	80042	621	1	0	1	0	0	0	0	0	31	0	1	0	0	47	0	80027	1	0	6	0	155	26	320190	80100	160298	80000	80100	160000	80000	4447142	3757314	9983197	0	80023	80042	80042	29920	24	3	29999	320100	200	80000	160000	200	160000	320000	80042	80042	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80007	7	23	80007	0	0	0	26	80018	6	1	26	23	7	0	15110	1	16	1	2	80039	0	80000	0	9	80000	320000	80100	80043	80043	80043	80043	80043
400204	80042	620	1	0	0	0	0	0	0	0	6	0	1	0	0	1	0	80027	1	6	6	0	4	26	320179	80100	160077	80000	80100	160000	80000	4447142	3757677	9984313	0	80023	80042	80042	29924	24	3	29999	320100	200	80000	160000	200	160000	320000	80042	80042	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80008	7	23	80007	0	1	1	26	80018	6	1	7	0	7	0	15110	1	16	2	1	80039	0	80000	0	9	80000	320000	80100	80043	80043	80043	80043	80043
400204	80042	621	1	1	1	0	0	0	0	0	31	0	0	0	1	67	0	80027	1	6	0	0	4	26	320170	80100	160092	80000	80100	160000	80000	4446076	3757075	9984577	0	80023	80042	80042	29904	20	3	29999	320100	200	80000	160000	200	160000	320000	80042	80042	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80008	8	23	80025	0	0	1	25	80019	6	1	26	23	7	0	15110	1	16	1	1	80039	1	80000	0	9	80000	320000	80100	80043	80043	80043	80043	80043
400204	80042	620	1	0	0	0	0	1	0	0	31	0	0	0	1	0	0	80027	0	0	6	0	0	26	320187	80100	160014	80000	80100	160000	80000	4446522	3757477	9982757	0	80023	80042	80042	29924	0	3	29999	320100	200	80000	160000	200	160000	320000	80042	80042	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80007	7	23	80027	0	1	1	26	80018	0	1	25	23	6	0	15110	1	16	2	1	80039	1	80000	9	9	80000	320000	80100	80043	80043	80043	80043	80043
400204	80042	620	1	0	1	0	0	0	0	0	31	0	0	0	0	16	1	80027	1	0	0	0	0	26	320212	80100	160127	80000	80100	160000	80000	4446444	3757551	9983560	0	80023	80042	80042	29900	20	3	29999	320100	200	80000	160000	200	160000	320000	80042	80042	1	1	240201	100	99	100	100	80000	160000	80000	1	100	80008	8	23	80026	0	0	2	6	80018	6	1	26	0	7	0	15110	1	16	2	1	80039	1	80000	9	9	80000	320000	80100	80043	80043	80043	80043	80043
400204	80042	620	1	0	0	1	0	0	0	0	31	0	0	0	1	0	1	80027	0	6	6	0	0	26	320197	80100	160090	80000	80100	160000	80000	4447132	3757678	9984543	0	80023	80042	80042	29920	20	3	29999	320100	200	80000	160000	200	160000	320000	80042	80042	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80006	7	23	80026	0	1	0	25	80018	6	1	26	23	7	0	15110	2	16	2	1	80039	1	80000	9	9	80000	320000	80100	80043	80043	80043	80043	80043
400204	80042	621	1	0	1	0	0	0	0	0	43	0	0	0	1	0	0	80027	1	6	6	0	0	26	320114	80100	160077	80000	80100	160000	80000	4447135	3757710	9984547	0	80023	80042	80042	29904	4	3	29999	320100	200	80000	160000	200	160000	320000	80042	80042	1	1	240201	100	99	100	100	80000	160000	80000	0	100	80007	7	23	80025	0	0	0	25	80018	6	1	25	23	7	0	15110	2	16	2	2	80265	1	80166	9	9	80000	320000	80100	80327	80330	80186	80330	80325

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	37	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst simd alu (9a)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	80042	620	1	1	1	0	1	0	1	1	0	0	36	0	0	0	37	9	80027	1	0	0	0	0	26	320117	80010	160107	80000	80010	160000	80000	4446334	3757460	9981053	4	1	5	80023	80042	80042	29947	0	3	30021	320010	20	80000	160000	20	160000	320000	80042	80042	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80006	7	28	80030	0	0	0	33	80023	0	1	30	27	7	2	0	15053	59	29	14	0	27	17	30	25	13	26	25	80039	1	80000	215	0	80000	320000	80010	80043	80043	80043	80043	80043
400024	80042	620	1	1	2	1	1	1	0	1	0	0	37	0	0	0	0	7	80027	1	6	6	0	4	69	320024	80010	160101	80000	80010	160000	80000	4446669	3757680	9984763	5	1	5	80023	80042	80042	29915	0	3	30021	320010	20	80000	160000	20	160166	320000	80042	80042	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80007	7	28	80031	0	0	2	31	80107	6	0	30	28	6	0	0	15052	53	28	17	0	27	16	26	20	10	13	29	80039	1	80000	185	18	80000	320000	80010	80043	80043	80185	80043	80043
400024	80042	620	1	1	1	0	1	0	1	1	0	0	19	0	0	0	34	7	80027	0	6	6	0	0	26	320106	80010	160105	80000	80095	160000	80000	4445237	3757180	9984464	6	1	5	80134	80183	80042	29908	0	3	30021	320010	20	80000	160000	20	160000	320000	80042	80042	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80006	7	28	80030	0	0	0	48	80024	6	1	30	27	7	1	0	15052	53	29	16	0	28	17	24	19	10	13	27	80039	1	80000	185	0	80000	320000	80010	80043	80043	80043	80043	80043
400024	80042	621	1	1	0	0	1	1	1	1	0	0	7	0	0	0	0	7	80169	0	0	0	0	0	26	320022	80010	160014	80083	80010	160000	80000	4446649	3757725	9984830	5	1	5	80023	80042	80042	29922	0	3	30021	320010	20	80000	160000	20	160000	320000	80042	80042	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80008	7	0	80007	0	0	1	36	80107	0	1	31	28	7	0	0	15052	53	29	16	0	27	17	24	19	10	27	26	80039	1	80000	185	0	80000	320000	80010	80043	80043	80043	80043	80043
400024	80186	621	1	1	0	2	1	0	1	1	0	1	37	88	1	0	28	7	80027	0	0	0	0	8	26	320118	80010	160089	80000	80010	160000	80000	4446640	3757680	9983509	5	1	5	80023	80042	80042	29947	5	3	30021	320677	20	80000	160000	20	160000	320000	80042	80042	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80006	6	28	80030	0	0	0	33	80000	6	1	30	28	6	1	0	15052	53	29	16	0	27	26	24	19	10	26	14	80039	1	80000	213	1	80000	320000	80010	80043	80043	80043	80043	80043
400024	80042	620	1	1	1	0	1	0	1	1	0	0	168	0	0	0	40	7	80167	1	0	6	0	0	26	320022	80010	160105	80084	80010	160000	80000	4446669	3756673	9982731	5	1	5	80023	80042	80042	29947	20	3	30022	320010	20	80000	160000	20	160000	320000	80042	80042	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80008	6	27	80007	0	0	0	30	80023	0	0	30	0	7	1	0	15052	68	36	16	0	25	16	24	19	10	25	26	80039	1	80000	198	0	80000	320000	80010	80043	80043	80043	80043	80043
400024	80042	620	1	1	0	1	1	0	1	1	0	0	36	0	0	0	120	7	80027	0	6	6	0	0	71	320081	80010	160014	80083	80010	160166	80000	4444558	3755698	9981559	4	1	5	80133	80198	80184	29860	132	26	30022	320343	20	80167	160000	20	160332	320000	81642	82643	18	1	240021	10	9	10	10	80000	160000	80000	0	10	80090	10	27	80198	2	0	3	1220	80107	6	1	6	28	6	3	0	15080	56	29	17	0	15	25	26	20	11	28	27	80262	1	80165	234	0	80000	320000	80010	80204	80328	80185	80327	80473
400024	80186	645	1	1	0	2	1	0	1	0	2	2	271	0	0	0	216	7	80332	1	6	6	45	44	119	320510	80176	160539	80166	80094	160165	80166	4441342	3757030	9985525	5	1	5	80134	80324	80184	29818	217	27	30184	320341	20	80166	160332	20	160332	320662	80183	80328	2	1	240021	10	9	10	10	80000	160000	80000	0	10	80093	8	28	80007	0	1	3	30	80023	6	1	30	28	6	0	0	15053	56	29	17	0	16	16	26	20	11	27	28	80039	1	80000	233	13	80000	320000	80010	80043	80043	80043	80043	80043
400024	80042	620	1	1	0	1	1	0	1	1	0	0	19	0	0	0	38	7	80027	1	0	6	0	0	26	320024	80010	160099	80000	80010	160000	80000	4446149	3757680	9983427	5	1	5	80023	80042	80042	29929	20	3	30021	320010	20	80000	160000	20	160000	320000	80042	80042	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80007	8	0	80031	0	1	0	7	80023	0	1	7	28	7	0	0	15053	56	29	17	0	15	17	26	20	12	26	15	80039	1	80000	217	18	80000	320000	80010	80043	80043	80043	80043	80043
400024	80042	621	1	1	1	1	1	1	1	0	0	0	7	0	0	0	0	7	80027	0	6	6	0	4	26	320024	80010	160116	80000	80104	160000	80000	4446669	3757724	9984828	4	1	5	80023	80042	80042	29927	20	3	30021	320010	20	80000	160000	20	160000	320000	80042	80042	1	1	240021	10	9	10	10	80000	160000	80000	0	10	80006	6	27	80030	0	0	1	7	80024	6	1	30	0	7	1	0	15053	56	29	17	0	14	16	26	20	11	26	28	80039	0	80000	205	0	80000	320000	80010	80043	80043	80043	80043	80043

LD2 (single, post-index, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations