Firestorm: LD3R (16B) measurements

Code:

  ld3r { v0.16b, v1.16b, v2.16b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.012

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.012

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	1f	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
64005	29278	219	1	18	1	13	0	1	0	10	0	1	0	4523	28844	0	0	1	17013	4012	3012	1000	3000	1000	5000	35745	4	22891	0	29094	29282	3	10	4000	1000	3000	1000	3000	29211	29195	1	1	61001	1000	1000	0	1002	3	3	1002	0	1	2	1	1000	3	0	2	0	0	12922	9116	6835	3162	5	48	20279	3101	3818	14	49	48	28430	16332	13791	14889	1000	3000	29271	29285	29275	29326	29258
64004	29209	219	0	14	0	11	0	0	0	4	0	1	0	4538	28759	1	1	0	17133	4009	3012	1000	3000	1000	5000	35708	7	22848	0	29135	29190	3	10	4000	1000	3000	1000	3000	29192	29191	1	1	61001	1000	1000	0	1002	1	2	1003	0	1	2	6	1000	2	1	3	1	1	13009	9260	6863	3073	5	45	20280	3061	3820	17	41	44	28327	16310	13945	14976	1000	3000	29217	29307	29264	29385	29312
64004	29237	220	1	8	1	13	1	0	0	3	0	1	0	4624	28736	1	0	0	17142	4009	3006	1000	3000	1000	5000	35773	2	22847	0	29076	29259	3	10	4000	1000	3000	1000	3000	29187	29101	1	1	61001	1000	1000	0	1000	0	3	1000	0	0	0	3	1002	2	1	0	1	1	12916	9150	6903	3109	6	43	20281	3090	3826	16	43	43	28392	16202	14073	14734	1000	3000	29330	29192	29238	29225	29269
64004	29388	218	1	16	1	16	1	0	0	4	0	1	0	4519	28773	0	0	0	17017	4012	3009	1000	3000	1000	5000	35749	8	22858	0	29104	29267	3	10	4000	1000	3000	1000	3000	29206	29212	1	1	61001	1000	1000	1	1000	0	0	1000	0	0	0	1	1000	2	1	2	0	0	12878	9395	6843	3058	4	40	20293	3072	3816	13	37	38	28437	16309	13928	14800	1000	3000	29179	29273	29257	29366	29299
64004	29159	219	0	15	0	13	0	0	0	1	0	0	0	4582	28793	0	0	0	17139	4003	3012	1000	3000	1000	5000	35749	6	22838	0	29061	29181	3	10	4000	1000	3000	1000	3000	29214	29213	1	1	61001	1000	1000	0	1002	2	2	1001	0	0	1	1	1000	3	0	2	0	0	13024	9173	6859	3019	8	44	20361	3114	3817	19	38	36	28372	16358	13958	15050	1000	3000	29284	29322	29280	29263	29307
64004	29287	219	0	12	0	15	0	0	0	1	0	1	0	4702	28866	0	0	0	17046	4003	3012	1000	3000	1000	5000	35634	1	22817	0	29079	29253	3	10	4000	1000	3000	1000	3000	29176	29233	1	1	61001	1000	1000	0	1003	3	2	1002	0	0	1	1	1000	3	1	3	1	0	12825	9128	6816	3055	8	42	20193	3090	3828	15	42	42	28356	16191	14000	15109	1000	3000	29319	29287	29209	29329	29283
64004	29223	220	1	15	1	8	1	0	0	3	0	1	0	4544	28700	0	0	0	17090	4003	3015	1000	3000	1000	5000	35776	7	22825	0	29131	29260	3	10	4000	1000	3000	1000	3000	29120	29179	1	1	61001	1000	1000	0	1003	1	3	1004	0	0	0	3	1000	3	1	3	1	1	13253	9270	6858	3094	5	31	20229	3103	3816	13	40	44	28297	16288	14090	15058	1000	3000	29270	29273	29298	29257	29309
64004	29300	220	1	15	0	17	0	0	0	4	0	1	0	4577	28832	0	0	0	17009	4012	3009	1000	3000	1000	5000	35644	3	22857	0	29141	29252	3	10	4000	1000	3000	1000	3000	29218	29194	1	1	61001	1000	1000	0	1004	3	3	1003	0	0	1	3	1000	3	1	2	1	1	12982	9251	6862	3070	4	38	20282	3092	3823	18	35	41	28287	16345	13850	15090	1000	3000	29271	29267	29290	29334	29315
64004	29178	218	1	16	1	10	1	0	0	3	0	0	0	4616	28794	0	0	0	17016	4003	3003	1000	3000	1000	5000	35768	0	22929	0	29062	29272	3	10	4000	1000	3000	1000	3000	29132	29118	1	1	61001	1000	1000	1	1003	3	3	1003	0	0	0	4	1000	2	1	3	1	2	12701	9124	6813	3044	8	44	20359	3138	3812	14	41	42	28307	16615	13795	15129	1000	3000	29235	29290	29262	29272	29248
64004	29227	219	1	11	1	13	0	0	0	5	0	0	0	4610	28721	0	0	0	16984	4003	3012	1000	3000	1000	5000	35760	6	22922	0	29107	29225	3	10	4000	1000	3000	1000	3000	29120	29080	1	1	61001	1000	1000	0	1002	2	3	1001	0	1	1	4	1000	2	1	3	1	1	12761	9257	6826	3016	5	42	20294	3093	3822	17	37	33	28354	16341	14218	15222	1000	3000	29244	29345	29294	29281	29288

Count: 8

Code:

  ld3r { v0.16b, v1.16b, v2.16b }, [x6]
  ld3r { v0.16b, v1.16b, v2.16b }, [x6]
  ld3r { v0.16b, v1.16b, v2.16b }, [x6]
  ld3r { v0.16b, v1.16b, v2.16b }, [x6]
  ld3r { v0.16b, v1.16b, v2.16b }, [x6]
  ld3r { v0.16b, v1.16b, v2.16b }, [x6]
  ld3r { v0.16b, v1.16b, v2.16b }, [x6]
  ld3r { v0.16b, v1.16b, v2.16b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320205	80067	600	1	1	1	0	0	35	1	0	0	80026	1	6	0	0	0	25	320120	100	240018	80000	100	240000	80000	500	400046	2883981	1	80022	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80006	7	28	80029	0	0	30	80000	6	1	29	0	7	0	5109	1	17	1	1	80038	1	0	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	1	0	1	0	0	6	0	0	0	80026	0	6	0	0	0	25	320120	100	240020	80000	100	240000	80000	500	400046	2883981	1	80022	80041	80041	3	23	320100	200	80000	240000	200	80033	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80008	8	28	80032	0	1	29	80024	6	1	7	0	7	0	5109	1	17	1	1	80038	0	13	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	600	1	0	1	0	0	6	1	0	0	80026	0	0	6	0	0	25	320120	100	240086	80000	100	240000	80000	500	400151	2880220	0	80022	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80008	8	27	80031	0	0	29	80024	6	0	7	28	7	0	5109	1	17	1	1	80038	1	13	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	600	1	1	0	0	1	36	0	0	0	80026	1	6	0	0	0	25	320186	100	240086	80000	100	240000	80000	500	400001	2883981	0	80022	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80007	6	0	80029	0	0	31	80023	6	1	7	28	6	0	5109	1	17	1	1	80038	0	13	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	1	0	0	0	0	37	1	0	1	80026	1	6	6	0	0	25	320120	100	240018	80000	100	240000	80000	500	400054	2883981	0	80022	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80008	8	27	80031	1	1	31	80000	6	1	29	0	7	1	5109	1	17	1	1	80038	1	0	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	1	1	0	0	1	37	0	0	0	80026	1	6	6	0	0	25	320120	100	240079	80000	100	240000	80000	500	400000	2880220	0	80022	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80007	7	28	80007	0	0	31	80000	6	0	29	27	7	1	5109	1	17	1	1	80038	0	0	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	600	1	0	1	0	0	7	1	0	0	80026	1	6	6	0	0	25	320183	100	240086	80000	100	240000	80000	500	400046	2880220	0	80022	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80007	7	27	80048	0	0	34	80023	6	1	31	0	6	0	5109	1	17	1	1	80038	1	13	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	600	1	1	1	0	0	35	1	0	0	80026	1	6	0	0	0	25	320183	100	240083	80000	100	240000	80000	500	400046	2883981	1	80022	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80007	7	28	80031	0	0	7	80023	0	1	6	27	7	1	5109	1	17	1	1	80038	0	13	0	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	1	1	0	0	0	36	0	0	1	80026	1	6	6	0	0	25	320183	100	240020	80000	100	240000	80000	500	400046	2883981	0	80022	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80007	9	27	80032	59	0	6	80000	6	1	6	27	7	1	5109	1	17	1	1	80038	0	13	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	1	1	1	0	0	7	0	0	0	80026	1	6	6	0	0	25	320179	100	240079	80000	100	240000	80000	500	400011	2884033	0	80022	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	2	1	80201	100	99	100	100	80000	80000	0	100	80008	8	27	80031	0	1	29	80024	6	1	30	0	7	1	5109	1	17	1	1	80038	0	13	13	80000	240000	100	80042	80042	80042	80042	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	80054	599	0	0	1	0	0	0	0	0	17	0	1	0	0	0	80026	1	6	6	0	0	25	320082	10	240018	80000	10	240000	80000	50	400038	2882887	0	1	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	15	80010	0	0	11	80000	6	0	0	15	0	0	0	5019	0	4	17	0	0	0	4	2	80038	1	0	9	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	1	0	0	1	1	0	0	0	32	0	1	0	0	0	80079	0	6	6	0	0	25	320010	10	240000	80000	10	240000	80000	50	400009	2880961	0	1	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80007	7	24	80026	0	0	26	80000	6	0	26	23	7	2	0	5019	0	4	17	0	0	0	4	2	80038	0	6	6	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	0	17	0	1	0	0	0	80026	1	0	6	0	0	25	320082	10	240075	80000	10	240000	80000	50	400038	2882839	0	1	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	15	80000	0	0	11	80011	6	0	11	15	0	0	0	5019	0	4	17	0	0	0	4	2	80038	0	6	6	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	0	16	0	1	0	0	0	80026	1	6	0	0	0	25	320052	10	240042	80000	10	240000	80000	50	400007	2880000	0	1	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	15	80000	0	0	14	80011	0	0	11	15	0	0	0	5019	0	4	17	0	0	0	2	4	80038	1	6	0	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	600	0	0	0	0	0	0	0	0	17	0	1	0	0	0	80026	1	6	0	0	0	25	320052	10	240042	80000	10	240000	80000	50	400000	2880961	0	1	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	15	80011	0	0	10	80011	0	0	11	0	0	0	0	5019	0	4	17	0	0	0	4	2	80038	0	9	9	80000	240000	10	80093	80042	80042	80042	80042
320024	80041	600	1	1	0	1	0	0	0	0	7	0	0	0	0	1	80026	0	0	6	0	0	25	320052	10	240042	80000	10	240000	80000	50	400008	2880964	0	1	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80007	8	24	80027	0	1	26	80000	6	1	26	24	7	1	0	5019	0	4	17	0	0	0	4	2	80038	0	6	6	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	0	17	0	1	0	0	0	80026	1	6	0	0	0	25	320081	10	240071	80000	10	240000	80000	50	400033	2882839	0	1	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	15	80000	0	0	11	80010	6	0	11	0	0	0	0	5019	0	2	17	0	0	0	4	2	80038	1	6	6	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	600	0	0	0	0	0	0	0	0	17	0	1	0	0	0	80026	1	6	6	0	0	25	320052	10	240099	80000	10	240000	80032	50	400173	2882192	0	0	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80093	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	15	80014	0	0	0	80010	6	0	10	0	0	0	0	5019	0	4	17	0	0	0	4	2	80038	0	0	6	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	0	16	0	1	0	0	0	80026	1	0	6	0	0	25	320077	10	240067	80000	10	240000	80000	50	400039	2882774	0	1	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80007	6	24	80006	0	1	26	80020	0	1	25	24	6	2	0	5019	0	2	17	0	0	0	3	4	80038	1	6	6	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	0	0	0	1	0	0	0	80026	1	6	6	0	0	25	320082	10	240067	80000	10	240000	80000	50	400038	2882774	0	1	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80012	0	0	10	80000	6	0	0	15	0	0	0	5019	0	3	17	0	0	0	2	4	80038	0	6	6	80000	240000	10	80042	80042	80042	80042	80042

LD3R (16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations