Firestorm: LD3R (1D) measurements

Code:

  ld3r { v0.1d, v1.1d, v2.1d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.006

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 3.006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	61	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	df	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
65005	29326	220	0	15	0	17	0	0	0	0	0	0	1	0	0	4534	28765	0	0	2	17070	5006	3009	2000	3000	2000	10000	35751	4	0	22864	0	29048	29227	3	10	5000	2000	3000	2000	6000	29115	29126	1	1	61001	1000	1000	1	2000	0	0	2002	1	0	4	2000	4	0	4	0	13003	9400	6891	3051	4	41	20161	3118	3818	11	35	45	3	28365	16272	13154	14997	2000	3000	29259	29308	29290	29288	29193
65004	29395	219	0	12	0	12	0	1	0	0	0	5	0	0	0	4638	28838	0	0	2	16974	5012	3006	2000	3000	2000	10000	35603	0	0	22955	0	29132	29248	3	10	5000	2000	3000	2000	6000	29168	29116	1	1	61001	1000	1000	0	2000	0	4	2002	0	0	2	2000	6	2	4	0	12783	9111	6846	3036	9	41	20151	3122	3812	6	45	44	3	28419	16362	13356	15006	2000	3000	29334	29323	29265	29274	29283
65004	29263	219	0	16	0	14	0	0	0	0	0	5	0	0	0	4589	28808	0	0	0	16976	5006	3006	2000	3000	2000	10000	35702	2	0	22912	0	29113	29341	3	10	5000	2000	3000	2000	6000	29170	29167	1	1	61001	1000	1000	0	2000	0	6	2000	0	0	0	2000	0	0	4	0	13144	9068	6816	3056	10	35	20263	3072	3816	9	42	38	2	28407	16422	13287	14804	2000	3000	29266	29262	29336	29219	29326
65004	29214	219	0	16	0	14	0	0	0	0	0	0	0	0	0	4521	28763	0	0	0	17066	5012	3012	2000	3000	2000	10000	35694	2	0	22930	0	29097	29176	3	10	5000	2000	3000	2000	6000	29127	29128	1	1	61001	1000	1000	0	2000	0	4	2000	0	0	3	2000	4	0	6	0	13181	9180	6810	3031	7	38	20120	3098	3817	10	43	39	3	28419	16302	13348	14981	2000	3000	29278	29314	29286	29242	29327
65004	29308	220	0	15	0	9	0	1	0	0	0	2	0	0	0	4588	28846	0	0	0	16989	5003	3006	2000	3000	2000	10000	35690	7	0	23007	0	29148	29260	3	10	5000	2000	3000	2000	6000	29146	29205	1	1	61001	1000	1000	0	2000	0	0	2000	0	0	0	2000	4	0	4	0	12903	9172	6830	3045	8	36	20207	3090	3820	15	33	29	2	28349	16237	13471	14686	2000	3000	29335	29250	29312	29243	29247
65004	29300	219	0	11	0	10	0	0	0	0	0	0	0	0	0	4537	28761	0	0	0	16960	5006	3006	2000	3000	2000	10000	35771	2	0	22926	0	29159	29314	3	10	5000	2000	3000	2000	6000	29158	29119	1	1	61001	1000	1000	1	2000	0	4	2000	0	0	0	2000	6	0	4	0	12693	9156	6823	3064	8	39	20183	3062	3817	10	36	34	3	28445	16289	13439	14870	2000	3000	29267	29326	29228	29229	29284
65004	29265	218	0	16	0	16	0	0	0	0	0	0	0	0	0	4559	28854	0	0	0	16983	5000	3009	2000	3000	2000	10000	35717	3	0	22908	0	29129	29244	3	10	5000	2000	3000	2000	6000	29134	29124	1	1	61001	1000	1000	1	2000	0	6	2000	0	0	2	2000	4	2	4	0	12900	9102	6841	3034	8	42	20149	3124	3816	6	35	40	3	28416	16489	13461	14741	2000	3000	29236	29262	29273	29222	29292
65004	29310	220	0	13	0	13	0	0	0	0	0	0	0	0	0	4540	28880	0	2	0	17088	5006	3000	2000	3000	2000	10000	35615	3	0	22943	0	29044	29243	3	10	5000	2000	3000	2000	6000	29202	29127	1	1	61001	1000	1000	1	2000	0	0	2000	0	0	0	2000	4	0	4	0	12949	9163	6884	3067	9	35	20245	3083	3819	10	37	37	2	28459	16377	13454	15004	2000	3000	29333	29226	29250	29198	28777
65004	29207	219	0	18	0	16	0	1	0	0	0	4	0	0	0	4609	28870	0	0	0	16999	5006	3000	2000	3000	2000	10000	35800	2	0	22934	0	29053	29221	3	10	5000	2000	3000	2000	6000	29081	29102	1	1	61001	1000	1000	1	2000	3	0	2000	0	0	0	2002	4	0	0	0	12749	9122	6801	3061	7	36	20107	3095	3819	10	47	36	2	28421	16348	13541	14948	2000	3000	29262	29246	29303	29214	29296
65004	29365	219	0	8	0	14	0	0	0	0	0	5	0	0	0	4580	28818	0	2	0	16961	5000	3000	2000	3000	2000	10000	35718	4	0	22887	0	29104	29244	3	10	5000	2000	3000	2000	6000	29203	29192	1	1	61001	1000	1000	1	2000	0	6	2000	0	0	0	2002	4	0	4	0	12963	9155	6865	3053	6	35	20150	3060	3818	10	40	30	2	28382	16384	13411	14993	2000	3000	29329	29205	29311	29211	29287

Count: 8

Code:

  ld3r { v0.1d, v1.1d, v2.1d }, [x6]
  ld3r { v0.1d, v1.1d, v2.1d }, [x6]
  ld3r { v0.1d, v1.1d, v2.1d }, [x6]
  ld3r { v0.1d, v1.1d, v2.1d }, [x6]
  ld3r { v0.1d, v1.1d, v2.1d }, [x6]
  ld3r { v0.1d, v1.1d, v2.1d }, [x6]
  ld3r { v0.1d, v1.1d, v2.1d }, [x6]
  ld3r { v0.1d, v1.1d, v2.1d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	80069	600	0	0	0	1	0	0	0	75	0	1	0	0	2	80027	2	0	5	3	25	400185	100	240083	160012	100	240024	160016	500	801456	2885084	1	80022	80043	80042	0	6	13	400140	200	160016	240024	200	160016	480048	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160018	12	0	160056	0	0	1	52	160043	6	1	51	43	12	0	1	1	1	5116	0	16	0	0	80039	0	13	13	0	160000	240000	100	80043	80043	80043	80043	80043
400204	80042	600	1	1	0	0	0	0	0	56	0	1	0	0	2	80028	2	5	5	3	25	400141	100	240077	160012	100	240024	160016	500	801456	2885078	1	80022	80043	80042	0	7	13	400140	200	160016	240024	200	160016	480048	80042	80043	1	1	80201	100	99	100	100	80000	80000	0	100	160018	14	43	160057	0	0	2	52	160044	6	1	52	0	13	2	1	1	1	5117	0	16	0	0	80039	0	13	13	1	160000	240000	100	80043	80043	80043	80044	80043
400204	80043	600	1	0	0	0	0	0	0	58	0	0	0	0	0	80026	0	5	5	3	25	400168	100	240067	160000	100	240000	160000	500	801372	2884895	1	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160013	14	43	160013	0	0	0	13	160039	6	1	13	43	13	1	0	0	0	5109	1	17	1	1	80038	0	0	13	1	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	600	1	1	0	0	0	0	1	57	0	1	0	0	2	80026	2	5	5	3	25	400119	100	240079	160000	100	240000	160000	500	801386	2884892	1	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160013	12	43	160053	0	0	0	52	160039	6	1	52	43	13	1	0	0	0	5109	1	17	1	1	80038	0	13	13	0	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	599	1	0	0	0	0	0	0	58	0	1	0	0	2	80026	2	5	5	3	25	400179	100	240079	160000	100	240000	160000	500	800102	2884892	1	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160014	14	43	160112	0	7	2	51	160039	6	1	12	43	13	0	0	0	0	5109	1	17	1	1	80038	0	0	13	1	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	599	1	0	1	0	0	0	0	57	0	0	0	0	2	80026	0	5	7	3	25	400166	100	240079	160000	100	240000	160000	500	801386	2884895	1	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160013	13	43	160053	0	0	2	52	160000	6	1	52	43	13	2	0	0	0	5109	1	17	1	1	80038	0	0	13	0	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	600	1	1	1	0	0	0	0	58	0	1	0	0	2	80026	2	5	5	3	25	400118	100	240074	160000	100	240000	160000	500	801383	2884899	1	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160014	12	43	160053	0	0	1	52	160039	6	1	52	43	13	1	0	0	0	5109	1	17	1	1	80038	0	13	13	0	160000	240000	100	80108	80042	80042	80042	80042
400204	80041	600	1	1	1	0	0	0	0	58	0	1	0	0	2	80026	0	5	5	3	25	400168	100	240079	160000	100	240000	160000	500	801382	2884895	1	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160013	15	43	160052	0	0	0	51	160000	6	1	51	0	13	0	0	0	0	5109	1	17	1	1	80038	0	13	0	0	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	599	1	1	0	0	0	0	0	58	0	0	0	0	2	80026	2	5	0	0	25	400174	100	240018	160000	100	240000	160000	500	801383	2884906	0	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160012	13	43	160051	0	0	2	51	160000	6	1	51	0	12	1	0	0	0	5109	1	17	1	1	80038	0	13	0	1	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	599	1	1	1	0	0	0	0	12	0	1	0	0	2	80026	2	5	5	3	25	400174	100	240074	160000	100	240000	160000	500	801383	2884996	1	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160015	13	43	160051	0	0	0	13	160039	6	1	13	43	13	2	0	0	0	5109	1	17	1	1	80038	0	13	13	1	160000	240000	100	80042	80042	80042	80042	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	1f	22	23	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	d9	db	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	80042	600	0	1	0	1	0	0	0	0	1	0	0	80026	0	12	12	25	400010	10	240063	160000	10	240000	160000	50	800853	2880000	0	80022	80041	80041	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160032	0	0	35	160036	6	1	0	40	0	0	5019	6	17	6	0	7	8	80038	0	0	0	0	160000	240000	10	80042	80042	80042	80042	80105
400024	80041	600	0	0	0	0	0	0	0	0	1	0	2	80026	2	0	12	25	400073	10	240063	160000	10	240000	160000	50	800853	2882004	0	80022	80041	80041	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	40	160000	0	0	36	160000	0	0	32	0	0	0	5019	5	17	0	0	5	8	80038	0	14	14	0	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	599	0	0	0	0	0	0	42	0	0	0	0	80026	2	12	12	25	400068	10	240060	160000	10	240000	160000	50	800377	2881975	0	80022	80041	80041	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160000	1	0	36	160036	6	0	0	40	0	0	5019	8	17	0	0	5	7	80038	0	10	14	0	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	600	0	0	0	0	0	0	0	0	1	0	2	80026	2	12	12	25	400073	10	240063	160000	10	240000	160000	50	800853	2881975	0	80022	80041	80041	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	160032	0	0	32	160000	6	1	0	35	0	0	5019	5	17	0	1	8	8	80038	0	14	14	0	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	599	1	0	0	0	0	0	42	0	0	0	2	80026	2	12	12	25	400073	10	240063	160000	10	240000	160000	50	800853	2881977	0	80022	80041	80041	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160000	0	0	36	160036	6	1	0	40	0	0	5019	6	17	0	0	8	8	80038	0	14	10	0	160000	240000	10	80042	80042	80042	80042	80042
400025	80041	599	0	0	0	0	0	0	42	0	0	0	0	80026	0	0	12	25	400010	10	240063	160000	10	240000	160000	50	800377	2881978	0	80022	80041	80041	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160036	0	0	0	160032	6	1	36	0	0	0	5019	8	17	0	0	7	6	80038	0	14	10	0	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	600	0	0	0	0	0	0	38	0	0	0	0	80026	2	12	12	25	400010	10	240063	160000	10	240000	160000	50	800853	2881978	0	80022	80041	80041	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	160000	0	0	32	160032	0	0	32	35	0	0	5019	5	17	0	0	7	7	80038	0	14	0	0	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	600	0	0	0	0	0	0	42	0	0	0	0	80026	2	12	0	25	400073	10	240000	160000	10	240000	160000	50	800000	2881968	0	80022	80041	80041	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80022	10	9	10	10	80000	80000	0	10	160000	0	160036	0	0	0	160036	0	0	36	35	0	0	5019	7	17	0	0	8	5	80038	0	14	14	0	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	599	0	0	0	0	0	0	0	0	0	0	2	80026	2	12	12	25	400068	10	240000	160000	10	240000	160000	50	800378	2881975	0	80022	80041	80041	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	160033	0	0	36	160032	6	1	36	40	0	0	5019	8	17	0	0	7	6	80038	1	10	10	0	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	599	0	0	0	0	0	0	0	0	1	0	2	80026	0	0	12	25	400068	10	240000	160000	10	240000	160000	50	800853	2883337	0	80022	80041	80041	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160000	0	0	32	160000	6	0	32	40	1	0	5019	7	17	0	0	8	7	80038	0	14	10	0	160000	240000	10	80042	80042	80042	80042	80042

LD3R (1D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations