Firestorm: LD3R (2D) measurements

Code:

  ld3r { v0.2d, v1.2d, v2.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.006

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 3.006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	0e	0f	18	1e	1f	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
65005	29248	220	16	0	0	16	1	1	0	5	0	1	0	0	4575	28835	2	0	16996	5006	3006	2000	3000	2000	10000	35613	3	22928	29146	29201	3	10	5000	2000	3000	2000	6000	29146	29172	1	1	61001	1000	1000	1	2000	0	2002	0	2	2000	4	0	0	0	13057	9116	6825	3076	5	58	20250	3015	3808	5	34	33	28458	16426	13324	14892	2000	3000	29294	29141	29278	29205	29281
65004	29298	219	11	0	0	14	1	0	0	0	0	1	0	0	4596	28795	1	0	17013	5006	3009	2000	3000	2000	10002	35661	5	22950	29135	29277	3	10	5000	2000	3000	2000	6000	29168	29175	1	1	61001	1000	1000	0	2000	6	2000	0	0	2000	0	0	0	6	12925	9314	6855	3037	7	46	20152	3131	3812	12	32	37	28443	16493	13197	14769	2000	3000	29242	29249	29262	29237	29305
65004	29309	219	11	0	0	15	0	0	0	6	0	1	0	0	4552	28768	0	0	16980	5000	3006	2000	3000	2000	10000	35683	5	22923	29042	29209	3	10	5000	2000	3000	2000	6000	29089	29144	1	1	61001	1000	1000	0	2000	6	2000	0	0	2000	4	0	0	0	12815	9116	6822	3040	2	46	20101	3098	3817	6	42	36	28424	16482	13362	14973	2000	3000	29153	29317	29208	29263	29253
65004	29302	219	13	0	0	11	0	0	0	7	0	0	0	0	4608	28843	0	0	16976	5009	3006	2000	3000	2000	10000	35610	5	22885	29126	29226	3	10	5000	2000	3000	2000	6000	29161	29031	1	1	61001	1000	1000	0	2000	4	2000	0	0	2000	0	0	0	0	12866	9218	6822	3067	8	40	20177	3034	3823	6	27	30	28559	16030	13309	14981	2000	3000	29303	29229	29279	29271	29222
65004	29222	219	14	0	0	14	0	0	0	7	0	0	0	0	4627	28843	0	0	16978	5006	3000	2000	3000	2000	10000	35705	2	22867	29037	29264	3	10	5000	2000	3000	2000	6000	29165	29187	1	1	61001	1000	1000	0	2000	6	2000	0	3	2000	4	0	0	4	12916	9178	6800	3088	4	41	20126	3062	3808	14	40	36	28358	16376	13287	14869	2000	3000	29201	29235	29283	29293	29198
65004	29258	219	16	0	0	9	0	0	0	0	0	1	0	0	4606	29002	0	0	16903	5000	3009	2000	3000	2000	10000	35686	2	22887	29160	29248	3	10	5000	2000	3000	2000	6000	29154	29034	1	1	61001	1000	1000	0	2000	6	2000	0	0	2000	4	0	0	0	12827	9245	6868	3043	5	48	20110	3134	3813	4	42	38	28364	16463	13353	14808	2000	3000	29257	29350	29339	29274	29317
65004	29273	219	9	0	0	10	0	0	0	7	0	1	0	0	4583	28813	0	0	16941	5009	3006	2000	3000	2000	10000	35624	5	22880	29159	29251	3	10	5000	2000	3000	2000	6000	29215	29185	1	1	61001	1000	1000	0	2000	4	2000	0	3	2002	4	0	0	4	12855	9154	6855	3068	6	51	20203	3088	3813	7	36	38	28370	16407	13371	15040	2000	3000	29223	29225	29217	29313	29210
65004	29292	219	17	0	0	8	0	0	0	6	0	0	0	0	4598	28824	0	0	16988	5006	3000	2000	3000	2000	10000	35693	5	22937	29182	29262	3	10	5000	2000	3000	2000	6000	29212	29207	1	1	61001	1000	1000	0	2000	4	2000	0	0	2001	4	0	0	4	12893	9107	6809	3071	5	48	20140	3090	3811	7	34	39	28395	16347	13375	14804	2000	3000	29272	29236	29282	29255	29257
65004	29256	219	14	0	1	11	0	0	0	6	0	1	0	0	4546	28846	0	0	17018	5009	3006	2000	3000	2000	10000	35689	5	22886	29054	29232	3	10	5000	2000	3000	2000	6000	29085	29150	1	1	61001	1000	1000	0	2000	6	2000	0	0	2000	4	0	0	6	12852	9175	6816	3116	6	37	20203	3144	3808	8	35	37	28469	16440	13117	14824	2000	3000	29222	29246	29321	29222	29239
65004	29272	219	15	0	1	12	0	0	0	5	0	1	0	0	4523	28831	0	2	17031	5009	3006	2000	3000	2000	10000	35712	5	22932	29112	29247	3	10	5000	2000	3000	2000	6000	29143	29136	1	1	61001	1000	1000	0	2000	4	2000	0	0	2002	4	0	0	4	12867	9239	6859	3085	5	46	19808	3073	3818	15	35	37	28366	16371	13374	14962	2000	3000	29300	29266	29245	29220	29258

Count: 8

Code:

  ld3r { v0.2d, v1.2d, v2.2d }, [x6]
  ld3r { v0.2d, v1.2d, v2.2d }, [x6]
  ld3r { v0.2d, v1.2d, v2.2d }, [x6]
  ld3r { v0.2d, v1.2d, v2.2d }, [x6]
  ld3r { v0.2d, v1.2d, v2.2d }, [x6]
  ld3r { v0.2d, v1.2d, v2.2d }, [x6]
  ld3r { v0.2d, v1.2d, v2.2d }, [x6]
  ld3r { v0.2d, v1.2d, v2.2d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	80068	600	1	1	1	0	0	0	0	58	1	0	0	80026	2	5	5	0	25	400157	100	240057	160000	100	240000	160000	500	800853	2880000	1	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	0	160032	0	3	160000	6	1	32	0	0	5109	1	17	1	1	80038	0	14	0	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	599	0	0	0	0	0	0	0	0	1	0	0	80026	0	12	12	0	25	400157	100	240063	160000	100	240000	160000	500	800377	2881978	1	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	0	160032	0	0	160032	6	0	0	0	0	5109	1	17	1	1	80038	0	10	14	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	599	0	0	0	0	0	0	0	42	0	0	0	80026	2	12	12	0	25	400163	100	240057	160000	100	240000	160000	500	800853	2880000	1	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	53	0	160032	1	0	160000	6	0	0	40	0	5109	1	17	1	1	80038	0	10	14	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	599	0	0	0	0	0	0	0	0	0	0	2	80026	2	12	12	0	25	400157	100	240057	160000	100	240000	160000	500	800853	2883329	1	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	53	0	160032	0	0	160032	0	1	36	40	0	5109	1	17	1	1	80038	0	0	0	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	599	0	0	0	0	0	0	0	42	0	0	0	80026	2	12	12	0	25	400163	100	240057	160000	100	240000	160000	500	800000	2880000	0	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	53	0	160318	43	36	160032	6	0	0	35	0	5109	1	17	1	1	80124	0	10	10	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	599	0	0	0	0	0	0	0	42	0	0	0	80026	2	12	12	0	25	400163	100	240000	160000	100	240000	160000	500	800853	2881968	0	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	53	0	160032	2	36	160032	6	1	0	40	0	5109	1	17	1	1	80038	0	14	10	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	599	0	0	0	0	0	0	0	42	1	0	2	80026	2	0	12	0	25	400100	100	240063	160000	100	240000	160000	500	800376	2882692	0	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	0	160032	0	36	160000	6	0	32	35	0	5109	1	17	1	1	80038	1	10	10	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	599	0	0	0	0	0	0	0	42	0	0	2	80026	2	12	12	0	25	400100	100	240063	160000	100	240000	160000	500	800000	2880000	0	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	0	160032	0	36	160060	6	0	32	40	0	5109	1	17	1	1	80038	0	14	0	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	600	0	0	0	0	0	0	0	0	0	0	2	80026	2	12	12	0	25	400163	100	240063	160000	100	240000	160000	500	800853	2880000	0	80022	80041	80695	7	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	0	160032	0	36	160032	6	1	0	40	0	5109	1	17	1	1	80038	1	0	10	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	600	0	0	0	0	0	0	0	0	0	0	0	80026	2	12	0	0	25	400157	100	240000	160000	100	240000	160000	500	800377	2880000	0	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	160000	35	0	160032	2	36	160036	0	1	32	40	0	5109	1	17	1	1	80104	0	14	10	160000	240000	100	80042	80042	80042	80042	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	df	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	80056	600	0	0	0	0	0	0	0	30	0	0	0	0	1	80026	2	12	12	0	25	400010	10	240000	160000	10	240000	160000	50	800219	2881253	1	80022	80041	80041	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	1	10	160000	0	27	0	160024	0	0	24	160024	6	1	24	27	0	0	5035	3	5	17	5	5	3	80038	1	0	6	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	599	0	0	0	0	0	0	0	30	0	0	0	0	0	80026	2	12	12	0	25	400010	10	240045	160000	10	240000	160000	50	800219	2881199	1	80022	80041	80041	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	0	160024	0	0	24	160000	6	0	0	27	0	0	5022	3	4	17	4	4	3	80038	1	0	6	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	600	0	0	0	0	0	0	0	0	0	1	0	0	0	80026	2	12	12	0	25	400010	10	240000	160000	10	240000	160000	50	800222	2881212	1	80022	80041	80041	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	0	160023	0	0	24	160024	6	0	24	27	0	0	5022	3	5	17	6	6	3	80038	1	6	6	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	600	0	0	0	0	0	0	0	0	0	0	0	0	0	80026	2	12	12	0	25	400010	10	240000	160000	10	240000	160000	50	800219	2881199	1	80022	80041	80041	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	0	160000	0	0	0	160024	0	0	0	0	0	0	5022	3	4	17	4	5	3	80038	1	6	6	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	600	0	0	0	0	0	0	0	30	0	1	0	0	0	80026	0	12	12	0	25	400056	10	240046	160000	10	240000	160000	50	800219	2880000	1	80022	80041	80041	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	0	160024	0	0	24	160000	0	1	24	27	0	0	5022	3	4	17	4	4	3	80038	1	0	6	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	600	0	0	0	0	0	0	0	30	0	1	0	0	0	80026	2	12	12	0	25	400056	10	240046	160000	10	240000	160000	50	800219	2881212	1	80022	80041	80041	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	0	160024	0	0	24	160024	6	1	24	27	0	0	5022	3	6	17	4	5	3	80038	1	6	6	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	599	0	0	0	0	0	0	0	60	0	1	0	0	0	80026	2	0	12	0	25	400055	10	240045	160000	10	240000	160000	50	800218	2881210	1	80022	80041	80041	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	0	160024	0	0	24	160024	6	1	24	27	0	0	5022	3	4	17	4	4	3	80038	0	6	6	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	599	0	0	0	0	0	0	0	0	0	1	0	0	0	80026	2	12	12	0	25	400056	10	240000	160000	10	240000	160000	50	800219	2881208	1	80022	80041	80041	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	0	160024	0	0	24	160024	6	1	0	27	0	0	5022	3	4	17	4	4	3	80038	1	0	6	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	600	0	0	0	0	0	0	0	30	0	1	0	0	0	80026	2	12	12	0	25	400056	10	240046	160000	10	240000	160000	50	800219	2881212	1	80022	80041	80041	0	3	23	400010	20	160092	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	1	10	160000	0	27	0	160024	0	0	24	160024	6	1	24	27	0	0	5022	3	6	17	4	4	3	80038	1	6	6	160000	240000	10	80042	80047	80042	80042	80042
400024	80041	599	0	0	0	0	0	0	0	30	0	0	0	0	0	80026	0	12	12	0	25	400056	10	240046	160000	10	240000	160000	50	800000	2881212	1	80022	80041	80041	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	0	160024	0	0	0	160024	6	1	24	27	0	0	5022	3	4	17	4	4	3	80038	1	0	6	160000	240000	10	80042	80042	80042	80042	80042

LD3R (2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations