Firestorm: LD3R (2S) measurements

Code:

  ld3r { v0.2s, v1.2s, v2.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.006

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	0e	0f	18	1e	22	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
64005	28239	215	14	13	1	0	2	11	0	4964	27898	0	0	0	16389	4010	3006	1000	3000	1000	5000	35728	2	22908	27943	28487	3	10	4000	1000	3000	1000	3000	28670	28143	1	1	61001	1000	1000	0	1000	0	1000	0	0	1000	1	2	3	13363	10519	7245	3239	7	42	19127	3187	3813	13	42	39	27977	13970	12007	13407	1000	3000	28442	28161	27935	28006	28011
64004	28655	211	11	11	0	0	0	4	0	5209	27888	0	1	1	15904	4009	3006	1000	3000	1000	5000	35752	6	22953	28407	28101	3	10	4000	1000	3000	1000	3000	28496	27966	1	1	61001	1000	1000	0	1000	0	1000	0	1	1000	2	1	2	14126	10255	7215	3493	10	29	19670	3457	3816	10	36	30	27749	15482	12175	12792	1000	3000	28035	28050	28106	28088	28071
64004	28584	211	9	11	0	0	0	0	1	4857	27887	1	0	0	15941	4000	3009	1000	3000	1000	5000	35712	10	22918	28125	28068	3	10	4000	1000	3000	1000	3000	28062	28232	1	1	61001	1000	1000	0	1000	2	1000	0	1	1000	2	2	0	14082	10379	7272	3180	7	39	19496	3588	3817	5	33	29	27996	13752	11944	12947	1000	3000	28086	28076	28648	28189	28058
64004	28251	214	11	12	0	0	0	2	0	5239	27918	0	1	1	15931	4009	3006	1000	3000	1000	5000	35725	4	22845	28164	28007	3	10	4000	1000	3000	1000	3000	28191	28031	1	1	61001	1000	1000	0	1000	2	1001	0	0	1000	2	3	3	14047	10499	7203	3402	9	35	19586	3187	3809	10	35	33	27767	14257	12112	12704	1000	3000	28505	28206	28195	28122	28110
64004	28137	210	9	17	0	0	0	0	0	5166	27992	1	1	0	16331	4006	3009	1000	3000	1000	5000	35624	6	22865	28189	28197	3	10	4000	1000	3000	1000	3000	28605	28097	1	1	61001	1000	1000	0	1000	2	1001	0	0	1000	2	0	0	13997	10760	7278	3431	6	32	19163	3467	3811	5	36	38	28004	14568	12967	12766	1000	3000	28202	28493	28399	28655	28203
64004	28077	211	11	10	0	0	0	4	1	4866	27991	0	0	1	15989	4006	3006	1000	3000	1000	5000	35724	2	22914	28098	28253	3	10	4000	1000	3000	1000	3000	28494	28561	1	1	61001	1000	1000	0	1000	2	1000	0	0	1000	1	1	0	13373	9505	7226	3363	10	36	18988	3519	3812	8	27	32	27761	14509	12771	12862	1000	3000	28027	28013	28041	28058	28473
64004	28133	210	12	9	0	0	0	3	0	5203	28214	1	1	0	15902	4006	3006	1000	3000	1000	5000	35718	5	22907	28125	28066	3	10	4000	1000	3000	1000	3000	28427	28608	1	1	61001	1000	1000	0	1000	2	1001	0	2	1000	0	1	0	13866	9432	7207	3493	7	36	19271	3247	3815	15	33	36	27808	14314	12230	12812	1000	3000	28245	28096	28049	28065	27996
64004	28175	211	15	14	0	0	0	3	0	4772	28339	1	0	0	16293	4000	3009	1000	3000	1000	5000	35618	6	22911	28178	28194	3	10	4000	1000	3000	1000	3000	28111	28579	1	1	61001	1000	1000	0	1000	0	1000	0	0	1000	2	0	3	14211	9525	6913	3455	11	36	19035	3498	3809	11	35	37	27970	15135	12083	13854	1000	3000	28165	28054	28068	28176	28030
64004	28506	210	12	13	0	0	0	0	1	4877	27876	0	1	1	15919	4006	3009	1000	3000	1000	5000	35691	2	22938	28407	28546	3	10	4000	1000	3000	1000	3000	28083	28032	1	1	61001	1000	1000	0	1000	2	1000	0	0	1000	2	2	0	13983	9527	7145	3267	9	34	19026	3462	3812	10	36	35	27675	14314	13290	14172	1000	3000	28139	28015	28508	28535	28119
64004	28150	214	13	14	1	1	0	7	0	5254	28180	0	1	0	16319	4006	3006	1000	3000	1000	5000	35705	2	22895	28482	28175	3	10	4000	1000	3000	1000	3000	28528	27928	1	1	61001	1000	1000	0	1000	2	1000	0	0	1001	2	1	2	13149	9664	6994	3468	6	41	19769	3452	3814	12	35	34	27797	14137	12105	13052	1000	3000	28532	28092	28158	28108	28513

Count: 8

Code:

  ld3r { v0.2s, v1.2s, v2.2s }, [x6]
  ld3r { v0.2s, v1.2s, v2.2s }, [x6]
  ld3r { v0.2s, v1.2s, v2.2s }, [x6]
  ld3r { v0.2s, v1.2s, v2.2s }, [x6]
  ld3r { v0.2s, v1.2s, v2.2s }, [x6]
  ld3r { v0.2s, v1.2s, v2.2s }, [x6]
  ld3r { v0.2s, v1.2s, v2.2s }, [x6]
  ld3r { v0.2s, v1.2s, v2.2s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320205	80067	599	0	0	0	1	0	0	0	19	0	1	0	0	80026	1	6	6	26	320198	100	240092	80006	100	240024	80008	500	400094	2884170	0	80022	80042	80041	6	12	320132	200	80008	240024	200	80008	240024	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80010	9	0	80033	0	1	31	80002	6	1	30	0	7	1	1	1	1	5116	1	16	1	1	80038	0	10	10	80000	240000	100	80042	80042	80043	80042	80042
320204	80041	599	0	0	0	1	0	0	0	0	0	1	0	0	80027	1	6	0	26	320201	100	240095	80006	100	240024	80008	500	400038	2884170	0	80022	80041	80041	6	12	320132	200	80008	240024	200	80008	240024	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80009	9	28	80032	0	0	31	80025	6	1	29	28	7	1	1	1	1	5116	1	16	1	1	80038	0	13	13	80000	240000	100	80043	80043	80043	80042	80043
320204	80041	599	1	0	1	0	0	0	0	36	0	0	0	1	80026	1	6	6	25	320135	100	240029	80006	100	240024	80008	500	400092	2880409	0	80022	80041	80041	7	12	320132	200	80008	240024	200	80008	240024	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80009	8	28	80032	0	1	31	80025	6	1	31	28	7	0	1	1	1	5116	1	16	1	1	80038	0	0	13	80000	240000	100	80043	80042	80043	80042	80042
320204	80041	599	1	1	0	0	0	0	0	6	0	0	0	1	80027	1	6	6	25	320194	100	240027	80006	100	240096	80008	500	400086	2880409	0	80022	80041	80041	6	12	320132	200	80008	240024	200	80008	240024	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80010	7	28	80034	0	1	32	80026	6	1	30	27	7	2	1	1	1	5116	1	16	1	1	80038	0	13	13	80000	240000	100	80042	80042	80042	80043	80042
320204	80041	599	1	1	0	0	0	0	0	37	0	0	0	1	80026	0	6	6	25	320186	100	240018	80000	100	240000	80000	500	400054	2883981	0	80022	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80007	7	0	80008	0	2	30	80023	6	1	6	27	7	2	0	0	0	5109	2	17	2	2	80038	1	13	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	1	1	0	0	0	0	0	243	572	1	0	0	80026	1	6	6	25	320183	100	240020	80000	100	240000	80000	500	400046	2883981	0	80022	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80008	8	28	80031	0	0	31	80023	6	0	29	27	7	1	0	0	0	5109	2	17	2	2	80038	1	0	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	1	0	0	0	0	0	0	7	0	0	0	0	80026	0	6	6	25	320183	100	240086	80000	100	240000	80000	500	400046	2880202	0	80022	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80014	1	0	14	80000	6	1	14	18	0	0	0	0	0	5109	2	17	2	2	80038	1	10	10	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	600	0	0	0	0	0	0	0	19	0	0	0	0	80026	1	6	6	25	320154	100	240000	80000	100	240000	80032	500	400009	2881693	0	80022	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80000	0	0	0	80014	6	0	0	18	0	0	0	0	0	5109	2	17	2	2	80038	0	13	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	1	1	0	0	0	0	0	6	0	0	1	1	80026	1	6	6	25	320186	100	240018	80000	100	240000	80000	500	400054	2880220	0	80022	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80007	7	28	80029	0	0	30	80023	6	0	30	0	7	0	0	0	0	5109	2	17	2	2	80038	1	13	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	600	1	1	0	1	0	0	0	35	0	0	1	1	80026	1	6	6	25	320186	100	240079	80000	100	240000	80000	500	400054	2880220	0	80022	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80007	7	28	80029	0	0	30	80023	0	0	29	27	7	1	0	0	0	5109	2	17	2	2	80038	1	13	13	80000	240000	100	80042	80042	80042	80042	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	80055	599	0	0	0	0	0	0	0	20	0	1	0	80026	1	6	6	0	0	25	320064	10	240054	80000	10	240000	80000	50	400018	2881693	1	80022	80041	80041	0	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80014	0	0	14	80014	6	0	14	18	0	5019	4	17	0	8	1	5	3	80038	1	0	10	10	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	1	0	0	0	0	0	20	0	1	0	80026	1	6	6	0	0	25	320064	10	240054	80000	10	240000	80000	50	400000	2881693	1	80022	80041	80041	0	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80014	0	0	14	80014	6	1	14	18	0	5019	4	17	0	6	0	3	6	80038	0	0	10	10	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	20	0	0	0	80026	1	6	6	0	0	25	320010	10	240054	80000	10	240000	80000	50	400016	2880000	1	80022	80041	80041	0	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80031	1	0	13	80014	6	1	14	18	0	5019	2	17	0	6	0	4	2	80038	0	0	10	10	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	20	0	1	0	80026	1	6	6	0	0	25	320010	10	240000	80000	10	240000	80000	50	400018	2881693	1	80022	80041	80041	0	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80014	0	0	14	80014	6	1	14	18	0	5019	4	17	0	6	0	6	2	80038	1	0	10	10	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	20	0	0	0	80026	1	6	6	0	0	25	320010	10	240054	80000	10	240000	80000	50	400009	2881739	0	80022	80041	80041	0	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80014	0	0	13	80014	6	1	13	18	0	5019	4	17	0	6	0	4	4	80038	0	0	10	10	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	0	0	0	0	80026	1	6	0	0	0	25	320064	10	240054	80000	10	240000	80000	50	400011	2881693	1	80022	80041	80041	0	0	3	23	320010	20	80000	240000	20	80000	240000	80093	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80013	0	0	14	80013	6	0	14	0	0	5019	4	17	0	6	0	4	5	80038	1	0	10	10	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	0	0	0	0	80026	1	6	6	0	0	25	320064	10	240054	80000	10	240000	80000	50	400011	2881693	0	80022	80041	80041	0	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80014	0	0	14	80014	6	0	0	18	0	5019	2	17	0	7	0	4	3	80038	1	0	10	10	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	42	0	0	0	80026	1	6	6	0	0	25	320010	10	240054	80000	10	240000	80000	50	400018	2881693	1	80022	80041	80041	0	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80013	0	0	14	80013	6	1	14	18	0	5019	4	17	0	6	0	4	2	80038	0	0	10	10	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	600	0	0	0	0	0	0	0	20	0	1	0	80026	1	6	6	0	0	25	320064	10	240054	80000	10	240000	80000	50	400000	2881693	1	80022	80041	80041	0	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80000	0	0	14	80013	6	1	14	0	0	5019	4	17	0	6	0	5	4	80038	1	0	0	10	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	620	0	0	0	0	0	0	0	28	0	0	0	80026	1	6	6	0	0	25	320064	10	240054	80000	10	240000	80000	50	400011	2881693	0	80022	80041	80041	0	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80013	0	0	0	80014	0	1	13	18	0	5019	2	17	0	7	0	2	4	80038	0	0	0	10	80000	240000	10	80042	80042	80042	80042	80042

LD3R (2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations