Firestorm: LD3R (4H) measurements

Code:

  ld3r { v0.4h, v1.4h, v2.4h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.012

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.012

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	19	1e	22	24	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
64005	28701	215	1	17	1	16	0	0	0	0	4	0	0	5370	27959	0	0	16014	4009	3009	1000	3000	1000	5000	35727	3	22850	28495	28131	3	10	4000	1000	3000	1000	3000	28425	28049	1	1	61001	1000	1000	0	1003	3	2	1002	0	2	1	1001	2	1	3	1	1	13291	10468	7272	3501	7	60	19568	3399	3813	13	44	36	27802	15160	12517	12707	1000	3000	28068	28566	28116	28271	28105
64004	28153	215	1	15	0	14	1	0	0	0	4	0	0	5247	27963	0	0	15783	4012	3012	1000	3000	1000	5000	35722	0	22879	28004	28063	3	10	4000	1000	3000	1000	3000	28385	28569	1	1	61001	1000	1000	0	1003	1	2	1002	0	1	1	1001	2	1	3	1	0	14172	10576	7330	3541	9	37	19754	3370	3822	16	42	42	27822	13950	12959	13729	1000	3000	28108	28088	27981	28532	28322
64004	28534	214	1	13	1	14	0	0	0	0	4	0	0	5345	27945	1	1	15877	4009	3009	1000	3000	1000	5000	35760	5	22849	28491	28129	3	10	4000	1000	3000	1000	3000	28025	27955	1	1	61001	1000	1000	0	1003	3	2	1004	0	2	2	1001	2	1	3	1	0	13483	10420	7031	3436	8	40	19297	3420	3822	16	38	44	27774	14713	12090	12832	1000	3000	28048	28035	28024	28418	28527
64004	28138	211	1	14	1	15	1	0	0	0	3	1	0	5102	27872	1	0	15962	4012	3012	1000	3000	1000	5000	35751	6	22909	28442	28510	3	10	4000	1000	3000	1000	3000	28002	28083	1	1	61001	1000	1000	0	1002	1	3	1003	0	1	1	1001	2	2	3	1	0	14143	10082	7336	3508	6	38	19327	3456	3818	13	43	43	27817	13805	12113	12949	1000	3000	28480	28051	28070	28451	28124
64004	28354	214	1	10	0	15	0	0	0	0	4	0	0	5217	27977	1	1	15983	4012	3012	1000	3000	1000	5000	35757	2	22850	28628	28664	3	10	4000	1000	3000	1000	3000	28114	28195	1	1	61001	1000	1000	0	1003	3	3	1004	0	0	2	1001	2	2	3	1	2	14248	10574	7213	3550	8	37	19346	3430	3822	14	50	39	27981	13861	12237	12545	1000	3000	28032	28007	28282	28616	28255
64004	28241	211	1	7	0	10	1	0	0	0	4	0	0	4895	27893	0	0	15822	4012	3012	1000	3000	1000	5000	35757	9	22894	28001	28284	3	10	4000	1000	3000	1000	3000	28367	28052	1	1	61001	1000	1000	0	1002	1	2	1003	0	2	1	1000	2	1	3	1	2	13504	10335	7291	3499	7	35	19214	3483	3812	12	44	46	27871	14141	12131	12841	1000	3000	28555	28583	28553	28120	28020
64004	28250	210	1	14	1	15	0	1	1	0	4	0	0	5272	28373	1	0	16507	4009	3012	1000	3000	1000	5000	35735	4	22860	28489	28128	3	10	4000	1000	3000	1000	3000	28446	28542	2	1	61001	1000	1000	0	1001	1	2	1002	0	0	2	1001	2	2	2	1	0	13964	10532	7287	3417	9	38	18992	3302	3818	10	45	49	28119	14120	12181	13798	1000	3000	28682	28220	28631	28206	28050
64004	28395	211	1	14	1	12	1	0	0	0	4	1	0	5202	27944	0	0	16002	4009	3012	1000	3000	1000	5000	35732	6	22840	28005	28553	3	10	4000	1000	3000	1000	3000	28467	28384	1	1	61001	1000	1000	0	1002	2	3	1001	0	1	1	1001	2	2	2	1	1	14048	10448	7281	3474	6	35	19169	3369	3820	15	41	39	27808	14055	12291	12890	1000	3000	28150	28148	28588	28090	28193
64004	28048	213	1	12	1	12	1	0	0	0	4	1	0	5120	27938	0	1	15981	4009	3012	1000	3000	1000	5000	35745	8	22853	28005	28062	3	10	4000	1000	3000	1000	3000	28251	28126	1	1	61001	1000	1000	0	1003	2	2	1002	0	0	2	1001	2	2	3	1	2	14321	10415	7314	3408	4	37	19254	3470	3822	14	40	41	27933	13878	12140	12937	1000	3000	28069	28515	28015	28413	28674
64004	28174	214	1	11	1	7	0	1	1	0	4	1	0	5312	27842	0	0	16318	4009	3009	1000	3000	1000	5000	35752	9	22876	28047	28126	3	10	4000	1000	3000	1000	3000	28217	27999	1	1	61001	1000	1000	1	1003	2	2	1003	0	1	1	1000	2	1	2	1	2	14035	10394	7304	3472	8	45	19715	3345	3818	9	42	36	27783	13916	12250	12690	1000	3000	28213	28479	28122	28475	28097

Count: 8

Code:

  ld3r { v0.4h, v1.4h, v2.4h }, [x6]
  ld3r { v0.4h, v1.4h, v2.4h }, [x6]
  ld3r { v0.4h, v1.4h, v2.4h }, [x6]
  ld3r { v0.4h, v1.4h, v2.4h }, [x6]
  ld3r { v0.4h, v1.4h, v2.4h }, [x6]
  ld3r { v0.4h, v1.4h, v2.4h }, [x6]
  ld3r { v0.4h, v1.4h, v2.4h }, [x6]
  ld3r { v0.4h, v1.4h, v2.4h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	09	0e	0f	1e	22	23	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320205	80067	600	0	1	0	0	23	0	0	80026	0	6	6	25	320163	100	240054	80000	100	240000	80000	500	400522	2881798	1	80022	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80014	0	14	80018	6	1	0	0	0	5109	1	17	1	1	80038	0	13	10	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	0	0	1	0	20	0	0	80026	1	0	6	25	320163	100	240054	80000	100	240000	80000	500	400836	2881881	1	80022	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80018	0	18	80000	6	0	14	18	0	5109	1	17	1	1	80038	1	0	10	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	0	0	0	0	20	1	0	80026	1	6	6	25	320163	100	240063	80000	100	240000	80000	500	400727	2883494	1	80022	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80018	0	13	80000	0	1	13	0	0	5109	1	17	1	1	80038	0	13	10	80000	240000	100	80093	80042	80042	80042	80042
320204	80041	600	0	0	0	0	0	1	0	80026	0	6	6	25	320154	100	240063	80000	100	240000	80000	500	400859	2883679	1	80022	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80017	1	14	80000	0	0	0	22	0	5109	1	17	1	1	80038	0	0	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	0	0	1	0	23	0	0	80026	1	6	0	25	320100	100	240063	80000	100	240000	80000	500	400699	2884025	1	80022	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80000	0	14	80000	0	1	18	22	0	5109	1	17	1	1	80038	1	13	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	600	0	0	0	0	23	1	0	80026	1	6	0	25	320154	100	240063	80000	100	240000	80032	500	400301	2884008	1	80022	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80017	0	13	80014	0	1	17	22	0	5109	1	17	1	1	80038	0	13	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	600	0	0	0	0	0	0	0	80026	1	0	6	25	320163	100	240063	80000	100	240000	80000	500	400872	2880252	1	80022	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	22	80017	0	18	80000	6	0	18	22	0	5109	1	17	1	1	80038	1	13	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	600	0	0	1	1	24	0	0	80026	1	0	6	25	320163	100	240054	80000	100	240000	80000	500	400797	2883965	1	80022	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80017	0	14	80013	6	1	17	22	0	5109	1	17	1	1	80038	1	10	0	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	600	0	0	0	0	0	0	0	80026	1	6	0	25	320154	100	240000	80000	100	240000	80000	500	400864	2883760	1	80022	80041	80041	3	37	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80018	0	18	80018	6	0	0	22	0	5109	1	17	1	1	80038	0	0	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	600	0	0	1	0	23	1	0	80026	1	6	6	25	320100	100	240063	80000	100	240000	80000	500	400661	2881871	1	80022	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80000	0	14	80000	6	0	14	22	0	5109	1	17	1	1	80038	1	13	10	80000	240000	100	80042	80042	80042	80042	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	80054	600	0	0	0	0	0	0	0	0	36	0	1	0	0	1	80026	0	6	6	0	0	46	320107	10	240408	80100	10	240300	80000	50	400011	2881692	0	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	27	80014	0	0	18	80017	6	1	7	28	6	0	0	0	5019	0	12	17	12	15	80038	1	13	13	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	1	0	0	0	20	0	0	0	0	0	80026	0	0	6	0	0	25	320073	10	240063	80000	10	240000	80000	50	400022	2882341	0	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	27	80014	0	0	18	80000	6	1	13	18	0	0	0	0	5019	0	14	17	13	13	80038	1	0	10	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	0	24	0	1	0	0	0	80026	1	0	6	0	0	66	320073	10	240063	80000	10	240000	80000	50	400024	2882341	0	80022	80041	80041	0	3	23	320010	20	80000	240075	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	28	80014	0	0	21	80014	6	1	17	0	0	0	0	0	5019	0	15	17	17	15	80038	1	0	10	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	0	24	0	0	0	0	0	80026	0	6	6	0	0	25	320064	10	240000	80000	10	240000	80000	50	400011	2881693	0	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80000	0	0	0	80017	6	1	13	22	0	0	0	0	5019	0	15	17	13	10	80038	0	13	13	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	600	0	0	0	0	0	0	0	0	24	0	1	0	0	0	80026	0	0	6	0	0	25	320073	10	240000	80000	10	240000	80032	50	400022	2881693	0	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	28	80013	0	0	20	80013	6	1	17	22	0	0	0	0	5019	0	10	17	14	14	80038	0	13	0	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	0	0	0	1	0	0	0	80026	1	0	6	0	0	25	320064	10	240054	80000	10	240000	80000	50	400018	2881693	1	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	28	80018	0	0	18	80018	6	1	0	0	0	0	0	0	5019	0	10	17	14	14	80038	0	13	10	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	0	0	0	0	0	0	0	80026	1	0	6	0	0	25	320064	10	240062	80000	10	240000	80000	50	400000	2880000	0	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	28	80014	0	0	13	80018	6	1	14	0	0	0	0	0	5019	0	13	17	14	16	80038	1	0	0	80000	240000	10	80042	80095	80042	80042	80042
320024	80041	600	0	0	0	0	0	0	0	0	20	0	0	0	0	0	80026	0	6	6	0	0	107	320063	10	240000	80000	10	240000	80000	50	400038	2880009	0	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	28	80085	0	0	17	80000	6	0	17	0	0	0	0	0	5019	0	12	17	14	15	80038	0	13	10	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	0	24	0	0	0	0	0	80026	1	6	6	0	0	25	320073	10	240063	80000	10	240000	80000	50	400024	2882341	0	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	28	80017	0	0	0	80017	6	0	13	0	0	0	0	0	5019	6	16	17	15	15	80038	0	13	0	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	0	24	0	0	0	0	0	80026	1	6	0	0	0	25	320072	10	240054	80000	10	240075	80000	50	404568	2889910	0	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	27	80014	0	0	18	80014	0	0	13	22	0	0	0	0	5019	0	13	17	12	15	80038	1	13	13	80000	240000	10	80042	80042	80042	80042	80042

LD3R (4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations