Firestorm: LD3R (4S) measurements

Code:

  ld3r { v0.4s, v1.4s, v2.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.006

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	0e	0f	1e	1f	22	23	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
64005	28322	213	3	2	1	1	2	0	1	0	5049	27858	1	1	1	15839	4006	3006	1000	3000	1000	5002	35690	4	22891	28319	28089	3	10	4000	1000	3000	1000	3000	28434	28366	1	1	61001	1000	1000	0	1000	3	1001	0	0	1000	2	1	2	1	13474	10436	7166	3467	0	58	19182	3358	3815	9	45	41	28037	13621	12922	13111	1000	3000	28110	28073	28340	28156	28079
64004	28090	213	0	0	1	0	9	0	1	0	5094	28052	0	0	1	16535	4000	3000	1000	3000	1000	5000	35710	0	22829	28334	28654	3	10	4000	1000	3000	1000	3000	28205	28408	1	1	61001	1000	1000	1	1000	0	1000	1	5	1001	1	2	2	0	13070	9411	7039	3214	0	39	19666	3298	3816	13	38	45	27967	15644	13283	14154	1000	3000	28623	28733	28617	28738	28775
64004	28765	223	0	0	0	0	2	0	0	0	5257	27920	0	0	0	16284	4006	3009	1000	3000	1000	5000	35694	5	22879	28329	28108	3	49	4000	1000	3000	1000	3003	29238	29073	1	1	61001	1000	1000	0	1000	2	1000	0	1	1000	2	0	2	0	12893	9183	6888	3053	0	38	20201	3088	3816	11	44	38	28309	16414	14000	15068	1000	3000	29240	29228	29290	29252	29274
64004	29284	220	0	0	0	0	3	0	0	1	4567	28753	0	0	0	17076	4006	3009	1000	3000	1000	5000	35713	6	22836	29142	29143	3	10	4000	1000	3000	1000	3000	29091	29226	1	1	61001	1000	1000	0	1000	2	1000	0	0	1000	2	0	0	0	12867	9237	6836	3104	0	41	20294	3087	3815	7	43	42	28303	16461	13724	15069	1000	3000	29268	29234	29234	29218	29265
64004	29264	219	2	0	0	0	3	0	0	0	4572	28765	0	0	0	17091	4006	3006	1000	3000	1000	5000	35681	4	22819	29116	29256	3	10	4000	1000	3000	1000	3000	29156	29119	1	1	61001	1000	1000	0	1000	2	1000	0	0	1000	2	0	0	0	12749	9105	6833	3106	0	42	20294	3066	3815	6	44	48	28271	16404	13894	15033	1000	3000	29240	29192	29178	29181	29283
64004	29256	218	0	0	0	0	3	0	0	0	4524	28806	0	0	1	17159	4006	3006	1000	3000	1000	5000	35679	2	22845	29084	29262	3	10	4000	1000	3000	1000	3000	29107	29147	1	1	61001	1000	1000	0	1000	0	1000	0	0	1000	0	0	2	0	12954	9111	6852	3071	0	39	20197	3006	3814	6	45	45	28351	16379	13809	14840	1000	3000	29245	29192	29185	29222	29290
64004	29212	219	0	0	0	0	0	0	0	1	4567	28791	0	1	0	17024	4006	3006	1000	3000	1000	5000	35695	5	22834	29023	29279	3	10	4000	1000	3000	1000	3000	29106	29169	1	1	61001	1000	1000	0	1000	2	1000	0	0	1001	2	0	3	0	12939	9133	6911	3083	0	42	20153	3066	3816	9	40	43	28345	16442	13836	14989	1000	3000	29179	29253	29177	29171	29233
64004	29162	219	1	0	0	0	6	0	0	0	4627	28804	0	0	0	16958	4006	3006	1000	3000	1000	5000	35740	6	22760	29049	29178	3	10	4000	1000	3000	1000	3000	29074	29084	1	1	61001	1000	1000	0	1000	2	1000	0	1	1000	0	0	2	0	12768	9400	6891	3154	0	46	20170	3100	3814	8	43	42	28339	16537	13801	14947	1000	3000	29304	29232	29228	29188	29284
64004	29169	218	0	0	0	0	3	0	0	1	4570	28884	0	1	0	17063	4006	3006	1000	3000	1000	5000	35717	5	22843	29073	29224	3	10	4000	1000	3000	1000	3000	29100	29156	1	1	61001	1000	1000	0	1000	2	1000	0	0	1000	2	0	2	0	12994	9181	6922	3037	0	46	20253	3108	3809	9	43	46	28344	16076	13838	15029	1000	3000	29138	29167	29341	29315	29303
64004	29198	219	0	0	0	1	0	0	0	1	4520	28817	0	0	0	16996	4006	3009	1000	3000	1000	5000	35617	5	22805	29091	29291	3	10	4000	1000	3000	1000	3000	29147	29093	1	1	61001	1000	1000	0	1000	0	1000	0	0	1000	0	0	2	0	12821	9129	6875	3066	0	46	20230	3041	3812	7	36	43	28383	16308	13904	15029	1000	3000	29287	29346	29315	29185	29215

Count: 8

Code:

  ld3r { v0.4s, v1.4s, v2.4s }, [x6]
  ld3r { v0.4s, v1.4s, v2.4s }, [x6]
  ld3r { v0.4s, v1.4s, v2.4s }, [x6]
  ld3r { v0.4s, v1.4s, v2.4s }, [x6]
  ld3r { v0.4s, v1.4s, v2.4s }, [x6]
  ld3r { v0.4s, v1.4s, v2.4s }, [x6]
  ld3r { v0.4s, v1.4s, v2.4s }, [x6]
  ld3r { v0.4s, v1.4s, v2.4s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	22	23	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320205	80067	599	0	0	1	0	0	0	0	0	1	0	0	80026	1	6	0	0	0	25	320154	100	240000	80000	100	240000	80000	500	400009	2881693	1	2	80022	0	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	18	80013	0	0	14	80013	6	1	14	18	0	0	5109	2	1	17	1	1	80038	0	10	10	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	1	0	0	1	0	0	0	36	1	0	1	80026	1	6	0	0	0	25	320163	100	240000	80000	100	240000	80000	500	400018	2880000	1	2	80022	0	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	18	80018	0	0	14	80018	6	1	14	18	0	0	5109	2	1	17	1	1	80038	1	0	10	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	600	0	0	0	0	0	0	0	19	1	0	0	80026	0	6	0	0	0	25	320154	100	240054	80000	100	240000	80000	500	400000	2881693	1	0	80022	0	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80007	6	28	80007	0	2	7	80024	6	1	30	28	7	0	5129	2	1	17	1	1	80038	1	0	13	80000	240000	100	80042	80042	80042	80094	80042
320204	80041	599	1	0	0	0	0	0	0	36	1	0	0	80026	1	6	0	0	0	25	320183	100	240086	80000	100	240000	80000	500	400046	2880220	1	2	80022	0	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80008	7	27	80031	0	1	30	80000	0	1	31	0	7	0	5109	2	1	17	1	1	80038	1	0	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	1	1	0	0	0	0	0	37	0	0	1	80026	0	6	6	0	0	25	320179	100	240079	80000	100	240000	80000	500	400055	2883981	1	2	80022	0	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80007	6	28	80031	0	0	30	80000	6	1	7	0	6	0	5109	2	1	17	1	1	80038	1	13	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	1	0	0	0	0	0	0	37	0	0	1	80026	1	6	0	0	0	25	320186	100	240018	80000	100	240000	80000	500	400054	2883981	1	2	80022	0	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80007	7	28	80029	0	0	38	80023	0	1	30	27	7	1	5109	2	1	17	1	1	80038	0	13	0	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	1	0	0	1	0	0	0	36	1	0	1	80026	1	6	0	0	0	25	320118	100	240083	80000	100	240000	80000	500	400046	2883981	1	2	80022	3	80041	80041	7	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80008	6	28	80009	10	1	9	80024	6	1	29	27	7	0	5109	2	1	17	1	1	80038	0	13	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	600	1	0	0	0	0	0	0	6	1	0	1	80026	0	0	6	0	0	25	320179	100	240020	80000	100	240000	80000	500	400048	2883915	1	2	80022	0	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80009	7	28	80031	0	2	31	80023	6	1	31	28	7	1	5109	2	1	17	1	1	80038	0	13	0	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	1	1	0	0	0	0	0	36	1	0	1	80026	0	6	6	0	0	25	320120	100	240086	80000	100	240000	80000	500	400046	2883981	1	2	80022	0	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80008	7	27	80007	0	1	6	80000	0	1	30	27	7	1	5109	2	1	17	1	1	80038	0	13	0	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	600	1	1	0	0	0	0	0	37	0	0	1	80026	1	6	0	0	0	25	320183	100	240086	80000	100	240000	80000	500	400047	2883981	1	2	80022	0	80041	80041	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80007	6	0	80007	0	1	30	80024	6	0	31	28	6	1	5109	2	1	17	1	1	80038	0	13	0	80000	240000	100	80042	80042	80042	80042	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	80054	600	0	0	0	0	0	0	0	7	0	1	0	0	0	80026	1	6	0	0	0	25	320089	10	240020	80000	10	240000	80000	50	400003	2883981	0	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	18	80018	0	0	17	80000	6	0	0	0	0	0	0	5019	3	17	3	2	80038	1	0	0	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	600	0	0	0	0	0	0	0	545	0	1	0	0	0	80026	1	6	6	0	0	25	320010	10	240000	80000	10	240000	80000	50	400000	2880000	1	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	0	80018	1	0	18	80000	6	1	13	22	0	0	0	5019	3	17	4	4	80038	0	0	10	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	600	0	0	0	0	0	0	0	20	0	1	0	0	0	80026	1	6	0	0	0	25	320010	10	240063	80000	10	240000	80000	50	400022	2882341	0	80022	80041	80041	0	3	70	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80014	0	0	18	80017	6	0	13	18	0	0	0	5019	4	17	3	3	80038	0	13	13	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	24	0	0	0	0	0	80026	0	6	0	0	0	25	320073	10	240054	80000	10	240000	80000	50	400022	2880000	0	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	18	80000	0	0	33	80000	0	1	0	0	0	0	0	5019	4	17	4	3	80038	0	13	0	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	600	0	0	0	0	0	0	0	24	0	1	0	0	0	80026	1	6	6	0	0	25	320030	10	240086	80000	10	240000	80000	50	400054	2884005	1	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	0	80000	0	0	0	80013	6	0	13	0	0	0	1	5019	4	17	3	4	80038	1	0	13	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	600	0	0	0	0	0	0	0	20	0	1	0	0	0	80026	1	6	6	0	0	25	320064	10	240063	80000	10	240000	80000	50	400029	2881693	1	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	22	80018	0	0	18	80018	6	1	0	0	0	0	0	5019	4	17	4	4	80038	1	13	0	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	57	0	0	0	0	0	80026	1	0	0	0	0	44	320073	10	240063	80050	10	240000	80000	50	400058	2881757	1	80022	80041	80041	0	3	47	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	18	80014	4	0	30	80018	6	1	14	22	0	0	0	5019	5	17	3	5	80038	0	13	13	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	600	0	0	0	0	0	0	0	24	0	1	0	0	0	80026	1	6	0	0	0	25	320073	10	240000	80000	10	240000	80000	50	400021	2880015	1	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	18	80000	1	0	17	80017	0	1	0	18	0	0	0	5019	3	17	4	3	80038	0	13	13	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	600	0	0	0	0	0	0	0	24	0	0	0	0	0	80026	0	6	6	0	0	25	320073	10	240063	80000	10	240000	80000	50	400022	2880000	1	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	18	80000	0	0	17	80000	6	0	14	22	0	0	0	5019	2	17	3	2	80038	1	13	0	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	600	1	1	0	0	0	0	0	35	0	1	0	0	0	80026	1	0	6	0	0	25	320028	10	240083	80000	10	240000	80000	50	400003	2880220	1	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	0	80000	0	0	13	80018	0	0	14	22	0	0	0	5019	4	17	3	4	80038	1	13	0	80000	240000	10	80042	80042	80042	80042	80042

LD3R (4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations