Firestorm: LD3R (8B) measurements

Code:

  ld3r { v0.8b, v1.8b, v2.8b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.006

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5e	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
64005	28622	213	3	0	6	0	1	1	0	0	0	7	0	0	5011	27981	0	0	1	16149	4006	3006	1000	3000	1000	5000	35690	0	6	22864	28444	28270	3	10	4000	1000	3000	1000	3000	28427	28161	1	1	61001	1000	1000	0	1000	0	2	1001	0	0	0	3	1001	2	2	3	1	2	14012	10158	7292	3341	0	50	19290	3410	3810	8	47	40	27939	14062	12148	12827	1000	3000	28456	28159	28119	28033	28300
64004	28073	211	2	1	1	0	0	0	0	0	0	2	0	0	5145	27923	1	1	0	15917	4006	3000	1000	3000	1000	5000	35634	0	8	22833	28257	28418	3	10	4000	1000	3000	1000	3000	28080	28333	1	1	61001	1000	1000	0	1002	3	0	1003	0	0	2	1	1000	0	1	0	0	0	13657	9857	7263	3295	0	40	19470	3309	3818	7	39	45	27812	14256	12839	13643	1000	3000	28138	28178	28153	28156	28435
64004	28057	211	0	0	0	1	0	0	1	1	1	3	1	0	5276	28041	0	1	0	16284	4009	3012	1000	3000	1000	5000	35747	0	8	22839	28156	28512	3	10	4000	1000	3000	1000	3000	28270	27988	1	1	61001	1000	1000	0	1000	0	2	1003	0	1	0	1	1000	0	2	3	1	1	13592	10514	7116	3190	0	41	19364	3415	3812	12	41	44	27918	14657	12577	13285	1000	3000	28192	28406	28306	28366	28360
64004	28184	210	0	0	0	0	0	0	0	0	0	2	1	0	5163	27955	0	1	1	15966	4009	3006	1000	3000	1000	5000	35694	0	5	22877	28379	28241	3	10	4000	1000	3000	1000	3000	28155	28164	2	1	61001	1000	1000	0	1000	0	2	1001	0	0	0	3	1000	2	2	2	1	0	13618	10434	7308	3296	0	43	19121	3426	3811	9	46	36	27816	14124	12417	13794	1000	3000	28423	28344	28371	28168	28379
64004	28238	211	0	0	0	0	0	0	0	0	0	2	1	0	5265	27844	1	1	0	15883	4006	3006	1000	3000	1000	5000	35688	0	1	22850	28115	28198	3	10	4000	1000	3000	1000	3000	28255	28231	1	1	61001	1000	1000	0	1000	0	0	1001	0	1	0	2	1001	1	1	2	0	0	14117	10396	7311	3542	0	47	19307	3472	3812	9	40	48	27937	14270	12059	13483	1000	3000	28288	28102	28154	28322	28091
64004	28266	211	0	0	0	0	0	0	0	0	0	0	1	0	4851	28021	1	0	1	15956	4006	3000	1000	3000	1000	5000	35709	0	3	22919	28096	28370	3	10	4000	1000	3000	1000	3000	28248	28416	1	1	61001	1000	1000	0	1000	0	2	1000	0	0	0	1	1001	1	1	0	0	0	13684	10520	7108	3312	0	43	19546	3353	3808	10	42	43	27760	14034	12287	12991	1000	3000	28417	28302	28453	28518	28454
64004	28353	210	1	0	0	0	0	0	0	0	0	0	1	0	5229	27972	0	0	1	15945	4012	3000	1000	3000	1000	5000	35750	0	5	22833	28056	28024	3	10	4000	1000	3000	1000	3000	28343	28076	1	1	61001	1000	1000	0	1000	0	3	1003	0	0	0	0	1000	2	2	2	1	2	13788	10467	7258	3491	0	44	19391	3298	3814	13	44	43	27850	15273	12082	14008	1000	3000	28065	28333	28108	27996	28089
64004	28132	212	0	1	0	0	0	0	0	0	0	0	0	0	5116	28069	1	1	1	16097	4000	3000	1000	3000	1000	5000	35621	0	2	22902	28032	28090	3	10	4000	1000	3000	1000	3000	28445	28432	1	1	61001	1000	1000	0	1000	0	0	1002	0	0	0	1	1001	1	1	2	0	0	13530	9813	7091	3435	0	40	19201	3478	3808	12	44	45	27898	14856	12538	13230	1000	3000	28115	28196	28454	28416	28174
64004	28216	210	0	0	0	0	0	0	0	0	0	7	0	0	5187	28119	0	1	1	16050	4006	3006	1000	3000	1000	5000	35682	0	4	22857	28042	28106	3	10	4000	1000	3000	1000	3000	28369	28377	1	1	61001	1000	1000	0	1000	0	3	1001	0	0	0	1	1000	1	1	0	0	0	13988	10456	7307	3498	0	45	19245	3390	3815	12	38	41	27893	14015	12395	12841	1000	3000	28475	28275	28290	28612	28388
64004	28059	211	0	0	0	0	0	0	0	0	0	2	0	0	5252	27934	1	1	1	16017	4006	3006	1000	3000	1000	5000	35634	0	1	22832	28047	28288	3	10	4000	1000	3000	1000	3000	28320	28100	1	1	61001	1000	1000	1	1000	0	2	1001	0	0	0	3	1003	1	1	2	0	0	14010	10448	7217	3355	0	47	19150	3481	3812	6	41	39	27929	14094	12774	13544	1000	3000	28086	28062	28456	28084	28124

Count: 8

Code:

  ld3r { v0.8b, v1.8b, v2.8b }, [x6]
  ld3r { v0.8b, v1.8b, v2.8b }, [x6]
  ld3r { v0.8b, v1.8b, v2.8b }, [x6]
  ld3r { v0.8b, v1.8b, v2.8b }, [x6]
  ld3r { v0.8b, v1.8b, v2.8b }, [x6]
  ld3r { v0.8b, v1.8b, v2.8b }, [x6]
  ld3r { v0.8b, v1.8b, v2.8b }, [x6]
  ld3r { v0.8b, v1.8b, v2.8b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320205	80067	599	1	1	1	0	0	35	0	1	0	1	80026	1	6	6	0	25	320186	100	240088	80000	100	240000	80000	500	400003	2883981	1	80022	80041	80041	0	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80007	6	28	80029	0	2	29	80000	6	1	31	28	7	1	0	5109	2	17	2	2	80038	0	13	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	600	1	1	0	1	1	45	0	1	0	1	80026	1	6	6	0	25	320186	100	240079	80000	100	240000	80000	500	400047	2883981	0	80022	80041	80041	0	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80009	8	28	80031	0	0	31	80000	6	1	29	28	6	2	0	5109	2	17	2	2	80038	0	13	0	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	1	0	1	0	0	35	0	1	0	1	80026	1	6	6	0	25	320179	100	240083	80000	100	240000	80000	500	400081	2883981	0	80022	80041	80041	0	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80006	7	28	80030	0	0	30	80023	6	1	31	28	6	1	0	5143	2	17	2	2	80038	0	0	0	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	600	1	0	0	0	0	35	0	1	0	1	80026	1	0	6	0	25	320185	100	240079	80000	100	240000	80000	500	400048	2883981	0	80022	80041	80041	0	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80008	7	27	80007	0	0	6	80024	6	1	30	0	7	1	0	5109	2	17	2	2	80038	1	13	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	600	1	1	0	0	0	36	0	0	0	1	80026	1	6	6	0	51	320188	100	240079	80000	100	240000	80000	500	400106	2880251	0	80022	80041	80041	0	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80008	8	28	80030	0	2	31	80023	6	0	29	27	7	0	0	5109	2	17	2	2	80038	1	13	0	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	1	1	1	0	0	35	0	1	0	0	80026	0	6	6	0	25	320186	100	240018	80000	100	240000	80000	500	400054	2883981	0	80022	80041	80041	0	3	23	320324	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80014	0	0	14	80014	0	1	13	0	0	0	0	5109	2	17	2	2	80038	0	13	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	1	1	1	0	0	36	0	0	0	0	80026	1	6	6	0	25	320183	100	240086	80000	100	240000	80000	500	400046	2883981	1	80022	80041	80041	0	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80007	7	0	80030	0	2	10	80023	6	0	31	28	7	2	0	5109	2	17	2	2	80038	1	0	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	600	1	1	0	0	0	35	0	0	0	1	80026	1	6	6	0	25	320183	100	240085	80000	100	240000	80000	500	400046	2880202	1	80022	80041	80041	0	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80007	7	27	80031	0	1	29	80000	6	1	30	27	7	0	0	5109	2	17	2	2	80038	1	13	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	600	1	1	1	0	0	6	0	1	0	1	80026	0	6	6	0	25	320183	100	240140	80000	100	240000	80000	500	400054	2880220	1	80022	80041	80041	0	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80006	6	28	80029	0	1	29	80024	6	0	31	28	6	2	0	5109	2	17	2	2	80038	0	10	10	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	1	0	0	0	0	442	88	1	0	1	80026	1	6	6	0	25	320183	100	240086	80000	100	240000	80000	500	400046	2883981	1	80022	80041	80041	0	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80008	7	28	80031	0	1	29	80024	6	1	30	27	7	0	0	5109	2	17	2	2	80038	1	13	13	80000	240000	100	80042	80042	80042	80042	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	80054	600	0	0	1	0	0	0	1	0	0	1042	0	1	0	0	80026	6	6	0	0	0	25	320090	10	240086	80000	10	240000	80000	50	400127	2883677	0	1	80022	0	80041	80041	0	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	10	80000	0	32	80010	0	0	0	28	80010	6	0	28	0	0	0	5019	14	17	7	18	80038	1	13	0	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	0	0	806	0	1	0	0	80026	6	6	11	0	0	25	320093	10	240018	80000	10	240000	80000	50	400042	2883677	0	1	80022	0	80041	80041	0	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	10	80000	0	32	80028	0	0	0	10	80028	6	1	10	0	0	0	5019	8	17	17	6	80038	0	10	0	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	600	0	0	0	0	0	0	0	0	0	866	0	1	0	0	80026	6	0	11	0	0	25	320028	10	240027	80000	10	240000	80000	50	400022	2883677	0	1	80022	0	80041	80041	0	0	3	23	320010	20	80000	240000	20	80033	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	10	80000	0	32	80028	0	0	0	10	80028	6	1	28	0	0	0	5019	17	17	6	17	80038	0	0	10	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	0	0	430	0	0	0	0	80026	1	0	11	0	0	25	320064	10	240083	80000	10	240000	80000	50	400000	2883677	0	1	80022	0	80041	80041	0	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	80028	0	0	0	9	80006	0	1	10	0	0	0	5019	14	17	6	17	80038	0	10	10	80000	240000	10	80042	80042	80202	80110	80042
320024	80041	599	0	0	0	0	0	0	0	0	0	543	0	0	0	0	80026	6	6	11	0	0	25	320091	10	240080	80000	10	240000	80000	50	400045	2880234	0	1	80022	0	80041	80041	0	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	10	80000	0	22	80028	0	0	0	6	80017	6	1	6	0	0	0	5019	8	17	17	21	80038	1	10	10	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	0	0	114	0	1	0	0	80026	6	6	0	0	0	25	320037	10	240081	80000	10	240000	80000	50	400045	2880383	0	1	80022	0	80041	80041	0	0	26	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	80028	0	2	0	31	80010	6	1	28	27	0	0	5019	6	17	6	17	80038	1	10	10	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	600	0	0	0	0	0	1	0	0	0	392	0	0	0	0	80026	6	6	0	0	0	25	320073	10	240018	80000	10	240000	80000	50	400048	2883677	0	1	80022	0	80041	80041	0	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	10	80000	0	32	80028	0	0	0	28	80028	6	1	14	27	0	0	5019	8	17	8	17	80038	1	10	0	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	0	0	889	0	0	0	0	80026	9	6	11	0	0	25	320028	10	240027	80000	10	240000	80000	50	400045	2883677	0	1	80022	0	80041	80041	0	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	80010	0	0	0	28	80028	0	0	28	27	0	0	5019	17	17	17	17	80038	1	10	0	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	1	0	0	864	0	1	0	0	80026	6	6	0	0	0	25	320037	10	240054	80000	10	240000	80000	50	400068	2883725	0	1	80022	0	80041	80041	0	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	80028	0	0	0	6	80010	6	0	28	0	0	0	5019	17	17	17	7	80038	1	10	10	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	600	0	0	0	0	0	0	0	0	0	403	0	1	0	0	80026	10	6	11	0	0	25	320028	10	240027	80000	10	240000	80000	50	400003	2883677	0	1	80022	0	80041	80041	0	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	10	80000	0	32	80025	0	0	0	18	80010	6	1	18	27	0	0	5019	18	17	17	17	80038	0	0	10	80000	240000	10	80042	80042	80042	80042	80042

LD3R (8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations