Firestorm: LD3R (8H) measurements

Code:

  ld3r { v0.8h, v1.8h, v2.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.009

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.009

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
64005	28764	213	1	31	0	22	1	0	1	0	0	3	1	0	4884	28202	0	1	0	16367	4012	3009	1000	3000	1000	5000	35629	4	22858	28352	28506	3	10	4000	1000	3000	1000	3000	28335	28465	1	1	61001	1000	1000	0	1002	1	2	1001	0	0	1	1000	2	1	2	1	1	13580	9905	7104	3312	11	76	19628	3259	3817	24	60	59	28015	14547	12653	13433	1000	3000	28612	28674	28536	28625	28501
64004	28602	213	1	26	1	23	0	1	1	0	0	4	0	0	4968	28165	0	0	0	16403	4003	3003	1000	3000	1000	5000	35624	5	22883	28359	28436	3	10	4000	1000	3000	1000	3000	28379	28301	1	1	61001	1000	1000	0	1001	2	2	1003	1	1	2	1000	2	1	0	1	1	13527	9842	7054	3291	14	65	19391	3243	3820	20	60	62	27997	14541	12576	13648	1000	3000	28527	28478	28416	28525	28453
64004	28525	213	1	26	1	24	1	0	0	0	0	2	1	0	4964	28170	0	0	0	16248	4009	3012	1000	3000	1000	5000	35735	5	22886	28347	28490	3	10	4000	1000	3000	1000	3000	28522	28382	1	1	61001	1000	1000	0	1001	1	2	1002	0	1	2	1001	0	1	2	1	0	13412	10089	7098	3263	8	57	19464	3285	3817	20	65	60	28090	15014	12855	13500	1000	3000	28547	28393	28544	28531	28486
64004	28428	213	1	31	1	25	0	0	0	0	0	1	1	0	4858	28107	0	1	1	16428	4009	3009	1000	3000	1000	5000	35697	6	22917	28333	28466	3	10	4000	1000	3000	1000	3000	28381	28496	1	1	61001	1000	1000	0	1002	1	2	1002	1	1	1	1000	2	1	2	1	0	13955	10097	7070	3283	13	63	19582	3241	3814	26	65	62	27963	14530	12387	13618	1000	3000	28666	28547	28560	28440	28405
64004	28519	214	1	24	1	28	1	0	0	0	0	3	1	0	5016	28172	0	0	0	16231	4009	3009	1000	3000	1000	5000	35625	10	22824	28262	28543	3	10	4000	1000	3000	1000	3000	28435	28426	1	1	61001	1000	1000	0	1002	1	0	1002	0	1	1	1000	2	1	2	1	1	13612	9834	7120	3251	10	62	19500	3298	3816	26	67	64	27954	14689	12578	13784	1000	3000	28517	28454	28375	28500	28530
64004	28773	213	1	29	0	29	1	0	0	0	0	3	1	0	4884	28149	0	0	1	16272	4009	3003	1000	3000	1000	5000	35800	4	22832	28373	28443	3	10	4000	1000	3000	1000	3000	28421	28418	1	1	61001	1000	1000	0	1002	2	0	1002	0	2	1	1001	0	1	0	1	1	13618	9870	7083	3309	8	59	19554	3190	3810	20	66	66	27957	14579	12646	13727	1000	3000	28631	28456	28573	28627	28419
64004	28497	213	1	25	0	27	0	0	0	0	0	3	1	0	4890	28234	0	1	0	16271	4009	3003	1000	3000	1000	5000	35644	4	22903	28435	28497	3	10	4000	1000	3000	1000	3000	28190	28298	1	1	61001	1000	1000	0	1001	2	3	1001	1	0	1	1000	0	1	0	1	1	13866	9936	7137	3370	10	64	19505	3325	3816	27	57	63	28024	14768	12604	13500	1000	3000	28586	28444	28482	28379	28462
64004	28665	214	1	25	1	31	0	0	0	0	0	4	0	0	5183	28242	0	0	0	16464	4012	3009	1000	3000	1000	5000	35717	5	22848	28424	28551	3	10	4000	1000	3000	1000	3000	28292	28334	1	1	61001	1000	1000	0	1001	2	2	1003	0	0	4	1000	0	1	3	1	0	13719	9858	7042	3312	9	70	19523	3294	3811	21	66	59	28066	14662	12922	13549	1000	3000	28671	28630	28572	28531	28460
64004	28483	216	1	22	2	28	1	0	0	3	3	331	0	0	5007	28173	0	0	0	16288	4009	3009	1000	3000	1000	5000	35734	10	22868	28219	28458	3	10	4000	1000	3000	1000	3000	28357	28382	1	1	61001	1000	1000	0	1001	2	2	1002	0	1	1	1000	2	2	2	1	1	13573	9828	7052	3409	10	71	19344	3399	3811	21	65	69	27946	14842	12852	13727	1000	3000	28817	28506	28679	28550	28524
64004	28555	212	1	24	1	25	1	1	1	0	0	1	0	0	4872	28111	0	0	0	16235	4009	3003	1000	3000	1000	5000	35723	6	22856	28317	28430	3	10	4000	1000	3000	1000	3000	28279	28282	1	1	61001	1000	1000	0	1002	2	2	1001	0	0	2	1001	2	1	2	1	1	13694	9669	7157	3345	13	59	19396	3298	3815	30	62	64	28112	14990	12637	13571	1000	3000	28609	28632	28370	28359	28461

Count: 8

Code:

  ld3r { v0.8h, v1.8h, v2.8h }, [x6]
  ld3r { v0.8h, v1.8h, v2.8h }, [x6]
  ld3r { v0.8h, v1.8h, v2.8h }, [x6]
  ld3r { v0.8h, v1.8h, v2.8h }, [x6]
  ld3r { v0.8h, v1.8h, v2.8h }, [x6]
  ld3r { v0.8h, v1.8h, v2.8h }, [x6]
  ld3r { v0.8h, v1.8h, v2.8h }, [x6]
  ld3r { v0.8h, v1.8h, v2.8h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	18	19	1e	22	23	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320205	80067	600	1	0	0	0	0	24	0	0	80026	1	6	6	25	320154	100	240000	80000	100	240000	80000	500	400024	2881693	0	80022	80041	80041	0	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80000	18	80014	1	0	13	80014	6	1	0	22	0	0	5109	1	17	1	1	80038	0	13	0	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	0	0	0	0	0	0	1	0	80026	0	0	6	25	320100	100	240062	80000	100	240000	80000	500	400148	2881693	0	80022	80041	80041	0	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80018	0	0	14	80018	0	1	0	22	0	0	5109	1	17	1	1	80038	1	0	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	0	0	0	0	0	20	1	0	80026	1	6	0	25	320163	100	240063	80000	100	240000	80000	500	400018	2881693	0	80022	80041	80041	0	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80000	0	0	18	80017	6	0	13	22	0	0	5109	1	17	1	1	80038	1	13	10	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	0	0	0	0	0	47	0	0	80026	1	6	6	25	320163	100	240063	80000	100	240000	80000	500	400018	2881693	0	80022	80041	80041	0	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80017	0	0	0	80017	6	1	13	22	0	0	5109	1	17	1	1	80038	0	10	11	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	0	0	0	0	0	0	0	0	80026	1	0	0	25	320100	100	240000	80000	100	240000	80000	500	400009	2880000	0	80022	80041	80041	0	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80000	1	0	0	80017	6	1	13	18	0	0	5109	1	17	1	1	80038	0	10	10	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	0	0	0	0	0	24	0	0	80026	1	6	0	25	320100	100	240000	80000	100	240000	80000	500	400029	2881693	0	80022	80041	80041	0	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80031	0	0	18	80017	0	0	24	0	7	2	5109	1	17	1	1	80038	1	10	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	0	0	0	0	0	19	0	0	80026	0	6	6	25	320163	100	240000	80000	100	240000	80000	500	400029	2880000	0	80022	80041	80041	0	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80018	0	0	18	80000	6	1	14	22	0	0	5109	1	17	1	1	80038	1	13	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	600	0	0	0	0	0	19	1	0	80026	1	0	6	25	320100	100	240054	80000	100	240000	80000	500	400029	2882736	0	80022	80041	80041	0	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80000	0	0	18	80000	6	1	13	22	0	0	5109	1	17	1	1	80038	1	0	0	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	600	0	0	0	0	0	62	0	0	80026	1	6	6	25	320163	100	240063	80000	100	240000	80000	500	400021	2882341	0	80022	80041	80041	0	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	2	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80018	0	0	13	80000	6	1	0	22	0	0	5109	1	17	1	1	80038	1	13	13	80000	240000	100	80042	80042	80042	80042	80042
320204	80041	599	0	0	0	0	0	0	0	0	80026	1	6	0	25	320154	100	240063	80000	100	240000	80032	500	400033	2880297	1	80022	80041	80041	0	3	23	320100	200	80000	240000	200	80000	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80000	0	0	14	80000	6	1	0	22	6	0	5109	1	17	1	1	80038	0	13	0	80000	240000	100	80042	80042	80042	80042	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	80067	600	0	1	1	0	0	1	1	0	0	0	32	0	1	0	0	1	80026	0	6	6	0	0	25	320082	10	240067	80000	10	240000	80000	50	400003	2882839	0	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	15	80000	0	1	0	10	80011	6	0	10	15	0	0	0	5019	16	17	0	10	7	80038	1	0	6	0	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	600	0	0	0	0	0	0	1	0	0	0	17	0	1	0	0	0	80026	1	0	6	0	0	25	320010	10	240000	80000	10	240000	80000	50	400008	2880961	0	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	15	80011	0	0	0	11	80011	6	0	10	15	0	0	0	5019	5	17	0	9	8	80038	0	0	6	0	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	600	0	0	0	0	0	0	0	0	0	0	17	0	1	0	0	0	80026	1	6	6	0	0	25	320052	10	240000	80000	10	240000	80000	50	400000	2880961	0	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	15	80000	0	0	0	0	80000	0	0	11	15	0	0	0	5019	7	17	0	7	10	80038	1	0	6	6	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	0	0	0	17	0	1	0	0	0	80026	1	6	6	0	0	25	320052	10	240042	80000	10	240000	80000	50	400000	2880964	1	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80009	8	24	80026	0	0	1	7	80000	6	1	26	24	6	2	0	5019	8	17	0	5	8	80038	0	0	9	9	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	1	0	1	0	0	0	0	0	0	32	0	1	0	0	0	80026	1	6	6	0	0	25	320081	10	240020	80000	10	240000	80000	50	400033	2882839	1	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80008	8	0	80027	0	0	0	26	80000	0	1	25	15	0	0	0	5019	7	17	0	5	8	80038	1	0	9	6	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	0	0	0	17	0	1	0	0	0	80026	1	6	0	0	0	25	320010	10	240042	80000	10	240000	80000	50	400008	2880964	1	80022	80041	80041	0	3	23	320138	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80011	0	0	0	10	80011	6	0	0	15	0	0	0	5019	8	17	0	9	7	80038	1	0	6	6	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	0	0	0	17	0	1	0	0	0	80026	0	0	6	0	0	25	320052	10	240042	80000	10	240000	80000	50	400008	2880000	1	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	15	80011	0	0	0	10	80000	6	0	11	15	0	0	0	5019	8	17	0	9	5	80038	1	0	6	6	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	0	0	0	0	0	0	0	0	0	16	0	1	0	0	0	80026	1	6	0	0	0	25	320010	10	240042	80000	10	240000	80000	50	400011	2880961	1	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80011	0	0	0	11	80011	6	0	11	23	7	1	0	5019	10	17	0	11	9	80038	1	0	9	0	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	600	0	1	0	1	0	0	0	0	0	0	17	0	1	0	0	0	80026	0	0	6	0	0	25	320052	10	240042	80000	10	240000	80000	50	400007	2880961	1	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80006	7	24	80027	0	0	1	26	80018	6	1	26	23	7	1	0	5019	7	17	0	5	8	80038	0	0	9	9	80000	240000	10	80042	80042	80042	80042	80042
320024	80041	599	0	1	0	1	0	1	0	0	0	0	16	0	1	0	0	0	80026	1	6	6	0	0	25	320010	10	240044	80000	10	240000	80000	50	400002	2880964	0	80022	80041	80041	0	3	23	320010	20	80000	240000	20	80000	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	15	80010	0	0	0	11	80000	6	0	10	15	0	0	0	5019	7	17	0	10	9	80038	1	0	6	6	80000	240000	10	80042	80042	80042	80042	80042

LD3R (8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations