Firestorm: LD3R (post-index, 16B) measurements

Code:

  ld3r { v0.16b, v1.16b, v2.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.012

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.012

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
64005	29023	232	1	0	3	0	0	3	0	0	0	0	0	3	0	0	0	4668	28439	1	0	0	16817	5006	1000	3006	1000	1000	3000	1000	5000	5000	35717	5	0	0	22826	28622	28745	3	10	5000	1000	3000	2000	3000	28720	28695	1	1	61001	1000	1000	0	1000	0	3	1000	0	0	1	1001	2	1	3	0	0	0	13201	9475	7019	3151	0	42	19724	3225	3803	11	38	47	28249	1000	15253	12847	13662	1000	3000	1000	28674	28759	28781	28618	28624
64004	28817	231	0	0	3	0	0	2	0	0	0	0	0	4	0	0	0	4736	28333	0	1	0	16800	5009	1000	3006	1000	1000	3000	1000	5000	5000	35743	9	0	0	22857	28705	28863	3	10	5000	1000	3000	2000	3000	28730	28686	1	1	61001	1000	1000	0	1000	0	3	1001	0	0	1	1001	2	1	3	0	0	0	13046	9497	6900	3063	0	51	19745	3274	3808	17	44	39	28131	1000	15490	12639	13710	1000	3000	1000	28898	29056	28901	28965	28990
64004	28804	231	0	0	1	0	0	1	0	0	0	0	0	4	0	0	0	4733	28523	0	1	1	16618	5009	1000	3009	1000	1000	3000	1000	5000	5000	35681	16	0	7	22783	28656	28729	3	10	5000	1000	3000	2000	3000	28685	28623	1	1	61001	1000	1000	0	1000	0	2	1000	0	0	0	1001	2	1	3	0	0	0	13125	9205	6954	3166	0	46	19735	3178	3805	13	43	51	28125	1000	15801	12716	13749	1000	3000	1000	28654	28740	28682	28866	28634
64004	28623	230	2	0	3	0	0	3	0	0	0	1	0	136	0	0	0	4769	28552	0	0	0	16878	5009	1000	3009	1000	1000	3000	1000	5000	5000	35731	15	0	0	22812	28736	29111	3	10	5000	1000	3000	2000	3000	29012	28888	1	1	61001	1000	1000	0	1000	0	3	1001	0	0	1	1002	2	1	2	0	0	0	13131	9293	6890	3093	2	45	20054	3332	3810	18	43	47	28404	1001	15577	12937	13737	1000	3000	1000	29026	29107	29062	29071	29010
64004	29112	233	0	0	2	0	0	1	0	0	0	0	0	4	0	0	0	4657	28650	1	1	0	16848	5009	1000	3006	1000	1000	3000	1000	5000	5042	35685	15	0	0	22840	28865	29211	3	10	5000	1000	3000	2000	3000	28818	28963	1	1	61001	1000	1000	0	1004	0	3	1001	0	2	1	1001	2	0	2	0	0	906	13189	9625	6902	3167	2	44	19844	3174	3807	12	45	39	28258	1000	15924	12969	13788	1000	3000	1000	28782	28837	28871	28807	28809
64004	28890	231	0	0	3	0	0	3	0	0	0	0	0	3	0	0	0	4731	28552	1	0	1	16580	5006	1000	3003	1001	1000	3000	1000	5000	5006	35740	12	0	0	22769	28864	28948	3	10	5000	1000	3000	2000	3000	28755	28848	1	1	61001	1000	1000	0	1000	0	3	1000	0	0	3	1000	2	2	3	0	0	0	13032	9154	6862	3129	1	44	19760	3242	3805	14	44	45	28378	1001	15602	12719	13851	1000	3000	1000	28777	28806	28865	28803	28897
64004	28927	232	0	0	3	0	0	3	0	0	0	0	1	4	0	0	0	4651	28526	0	1	1	16675	5006	1000	3009	1000	1000	3000	1000	5000	5000	35666	13	0	8	22792	28699	28882	3	10	5000	1000	3000	2000	3000	28786	28825	1	1	61001	1000	1000	0	1000	0	2	1001	0	0	455	1001	2	1	3	0	0	0	13041	9426	6922	3249	1	42	19778	3214	3800	14	48	47	28217	1000	15604	12732	13909	1000	3000	1000	28849	28777	28888	28875	28797
64004	28850	232	0	0	2	0	1	2	0	0	0	0	0	3	0	0	0	4808	28448	0	1	1	16663	5009	1001	3009	1000	1000	3000	1000	5000	5001	35693	16	0	0	22808	28806	28845	3	27	5005	1000	3003	2000	3000	28706	28749	2	1	61001	1000	1000	0	1000	0	3	1001	0	0	1	1000	2	1	3	0	0	0	13154	9250	6800	3140	1	42	20300	3301	3801	19	47	45	28735	1000	16106	13088	14565	1000	3000	1000	28847	28813	28866	28843	28873
64004	28900	234	0	0	2	0	1	2	0	0	0	0	0	4	0	0	0	4633	28399	1	0	1	16569	5006	1000	3009	1000	1001	3000	1000	5000	5000	35674	6	0	0	22793	28766	28794	3	10	5000	1000	3000	2000	3000	29131	28857	1	1	61001	1000	1000	0	1000	0	2	1001	0	0	386	1001	2	3	2	0	0	0	13006	9229	6970	3123	1	50	19801	3161	3807	14	46	43	28169	1000	15380	12664	13770	1000	3000	1000	28787	28851	28761	28874	28684
64004	28702	231	0	0	4	0	0	3	0	0	0	0	0	6	0	0	0	4636	28450	1	1	0	16490	5009	1000	3006	1001	1000	3000	1000	5000	5000	35675	15	1	0	22819	28619	28847	3	10	5000	1000	3000	2000	3000	28636	28860	2	1	61001	1000	1000	0	1002	0	3	1000	0	0	1	1001	2	3	3	0	0	0	13227	9651	6941	3081	0	50	19831	3299	3801	20	43	43	28219	1000	15606	12543	13813	1000	3000	1000	28707	28912	28710	28818	28713

Count: 8

Code:

  ld3r { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3r { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3r { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3r { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3r { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3r { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3r { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3r { v0.16b, v1.16b, v2.16b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320205	80068	621	0	0	1	1	0	0	28	0	0	0	0	80027	1	0	6	0	0	25	400159	80100	240059	80000	80100	240000	80000	480499	480023	3121555	1	80023	80042	80042	0	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	18	80013	0	0	0	17	80013	6	1	14	0	0	5109	1	17	1	1	80039	1	80000	14	10	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	620	0	0	1	0	0	0	21	0	0	0	0	80027	1	6	6	0	0	25	400159	80100	240059	80000	80100	240000	80000	480499	479998	3121493	0	80023	80042	80042	0	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80014	0	0	0	17	80000	6	1	15	18	0	5109	1	17	1	2	80039	0	80000	13	12	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	620	0	0	0	0	0	0	32	0	0	0	0	80027	1	6	6	0	0	25	400151	80100	240051	80000	80100	240000	80000	480499	480021	3119994	0	80023	80042	80042	0	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80014	0	0	0	14	80014	6	1	14	18	0	5109	1	17	1	1	80039	0	80000	10	10	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	621	0	0	0	0	0	0	21	0	0	0	0	80027	1	0	6	0	0	25	400159	80100	240059	80000	80100	240000	80000	480499	481636	3120039	0	80023	80042	80042	7	0	3	24	400300	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	18	80015	0	0	4	14	80014	6	1	14	20	0	5109	1	17	1	1	80039	1	80000	13	13	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	621	0	0	0	0	0	0	22	0	0	0	0	80027	1	6	6	0	3	25	400100	80100	240059	80000	80100	240000	80000	480499	480014	3121493	0	80023	80042	80042	0	0	3	24	400100	200	80000	240000	200	160000	240120	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80014	0	1	0	19	80016	6	1	14	20	0	5109	1	17	1	1	80039	1	80000	13	10	80000	240000	80100	80043	80043	80043	80043	80118
320204	80042	620	0	0	0	0	0	0	0	0	0	0	0	80027	0	6	6	0	0	25	400151	80100	240059	80000	80100	240000	80000	480499	480015	3121493	0	80023	80042	80042	0	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80014	0	0	0	14	80014	6	1	14	0	0	5109	1	17	1	1	80039	0	80000	13	10	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	620	0	0	0	0	0	0	45	0	0	0	0	80027	1	6	6	0	0	25	400159	80100	240059	80000	80100	240000	80000	480499	480011	3121695	0	80023	80042	80042	0	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80016	0	1	0	18	80015	6	1	14	20	0	5109	1	17	1	1	80039	1	80000	10	10	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	621	0	0	0	0	0	0	0	0	0	0	0	80027	1	6	0	0	0	25	400151	80100	240059	80000	80100	240000	80000	480499	480016	3121493	0	80023	80042	80042	0	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	18	80016	0	0	0	14	80014	6	1	13	0	0	5109	1	17	1	1	80039	0	80000	13	13	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	620	0	0	0	0	0	0	23	0	0	0	0	80027	1	6	6	0	0	25	400159	80100	240051	80000	80100	240000	80000	480499	480015	3121550	0	80023	80042	80042	0	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	18	80014	0	2	0	13	80014	6	1	18	0	0	5109	1	17	1	1	80039	1	80000	13	13	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	621	0	0	1	0	0	0	19	0	0	0	0	80027	1	6	6	0	0	25	400100	80100	240000	80000	80100	240141	80000	480499	481631	3121493	0	80023	80042	80042	0	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80016	0	0	0	14	80016	6	1	15	18	0	5109	1	17	1	1	80039	0	80000	10	13	80000	240000	80100	80043	80043	80043	80043	80043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	80056	621	0	0	0	1	0	0	0	31	0	0	0	80027	1	6	0	0	0	25	400058	80010	240048	80000	80010	240000	80000	480049	480025	3120852	0	80023	0	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80000	0	0	51	80000	6	0	10	0	0	5019	3	17	2	2	80039	0	80000	9	6	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	0	0	0	0	0	0	0	19	0	0	0	80027	1	0	0	0	0	25	400010	80010	240048	80000	80010	240000	80000	480049	480011	3120917	0	80023	0	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80012	1	0	154	80010	6	1	0	17	0	5019	3	17	2	2	80039	1	80000	9	0	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	621	0	0	0	0	1	0	0	18	0	0	0	80027	1	6	6	0	0	25	400010	80010	240048	80000	80010	240000	80000	480049	480007	3119994	0	80023	0	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80010	0	0	18	80010	6	1	12	17	0	5019	2	17	2	2	80039	1	80000	0	6	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	0	0	0	0	0	0	0	18	0	0	0	80027	1	6	6	0	0	25	400057	80010	240048	80000	80010	240000	80000	480049	480273	3125382	0	80023	0	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	13	80009	1	0	21	80010	0	1	0	18	0	5019	2	17	2	2	80039	0	80000	9	9	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	621	0	0	0	0	1	0	0	0	0	0	0	80027	1	6	6	0	0	25	400058	80010	240048	80000	80010	240000	80000	480049	480022	3120054	0	80023	0	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	13	80010	1	0	151	80009	5	0	9	17	0	5019	2	17	2	3	80039	0	80000	9	6	80000	240000	80010	80043	80043	80043	80043	80043
320024	80344	620	0	0	0	0	0	0	0	19	0	0	0	80027	1	6	6	0	0	25	400048	80010	240048	80000	80010	240000	80000	480049	480007	3120852	0	80023	0	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	13	80012	1	0	18	80010	6	0	0	17	0	5019	2	17	2	2	80039	1	80000	9	9	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	621	0	0	0	0	0	0	0	18	0	0	0	80027	0	6	6	0	0	25	400058	80010	240048	80000	80010	240000	80000	480049	480007	3119994	0	80023	0	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	13	80013	1	0	133	80009	6	1	10	17	0	5019	2	17	2	2	80039	1	80000	9	9	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	0	0	0	0	0	0	0	19	0	0	0	80027	1	6	6	0	0	25	400058	80010	240057	80000	80010	240000	80000	480049	480007	3120852	0	80023	0	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	13	80013	0	0	184	80010	6	0	13	13	0	5019	2	17	2	2	80039	1	80000	9	6	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	0	0	0	0	0	0	0	30	0	0	0	80027	1	6	6	0	0	25	400058	80010	240038	80000	80010	240000	80000	480049	480015	3120851	0	80023	0	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	17	80013	0	0	193	80010	6	1	9	17	0	5019	2	17	2	2	80039	0	80000	8	6	80000	240000	80010	80043	80043	80043	80043	80114
320024	80042	620	0	0	0	0	0	0	0	19	0	0	0	80027	1	6	6	0	0	25	400058	80010	240048	80000	80010	240000	80000	480049	479998	3120852	0	80023	0	80192	80118	14	14	77	400010	20	80080	240120	20	160080	240000	80042	80193	3	1	80021	10	9	10	10	80000	80000	0	10	80074	0	0	80089	1	2	699	80084	0	1	9	17	2	5032	4	170	4	2	80985	0	80600	9	9	80000	240000	80010	80120	80194	80195	80119	80194

LD3R (post-index, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations