Firestorm: LD3R (post-index, 1D) measurements

Code:

  ld3r { v0.1d, v1.1d, v2.1d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 6.009

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 3.009

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
65005	28803	224	4	1	2	1	1	3	0	1	1	0	0	7	0	1	0	4639	28366	2	2	16548	6012	1000	3012	2000	1000	3000	2000	5000	10000	35684	11	1	8	22956	28599	28771	3	10	6000	2000	3000	3000	6000	28709	28832	1	1	61001	1000	1000	0	2003	3	4	2002	0	1	1	2	2000	4	2	0	2	1	0	13184	9372	6919	3031	1	54	19657	3184	3816	21	65	62	28193	1000	15693	13094	14809	2000	3000	1000	28891	28868	28786	28804	28777
65004	28728	223	0	1	2	0	1	2	1	0	0	0	0	33	0	0	0	4670	28451	0	0	16473	6003	1000	3009	2000	1000	3000	2000	5000	10000	35640	6	1	0	22892	28731	28852	3	10	6000	2000	3000	3000	6000	28793	28686	1	1	61001	1000	1000	0	2003	3	4	2002	0	0	1	2	2000	4	2	4	2	1	0	13211	9489	6937	3145	0	62	19657	3242	3820	20	52	57	28279	1000	15622	12723	14063	2000	3000	1000	28854	28812	28900	28860	28796
65004	28955	222	0	0	1	0	1	2	1	0	0	0	0	6	0	0	0	4611	28425	0	0	16587	6009	1000	3009	2000	1000	3000	2002	5000	10000	35704	1	1	0	22929	28676	28929	3	10	6000	2000	3000	3000	6000	28710	28732	1	1	61001	1000	1000	0	2003	0	0	2002	1	0	1	2	2000	0	2	4	2	0	0	13112	9135	6944	3114	1	63	19711	3296	3825	21	55	70	28271	1000	15660	12649	14030	2000	3000	1000	28864	28856	28852	28851	28678
65004	28892	223	0	1	2	0	0	1	1	0	0	0	0	6	0	0	0	4767	28538	0	0	16585	6009	1000	3009	2000	1000	3000	2000	5000	10000	35702	7	0	0	22941	28627	28511	3	10	6000	2000	3000	3000	6000	28626	28550	1	1	61001	1000	1000	1	2003	2	4	2002	1	0	1	5	2002	4	2	4	2	0	0	13288	9518	6947	3200	0	62	19532	3291	3823	24	59	63	28255	1000	15632	12746	13816	2000	3000	1000	28622	28723	28758	28698	28710
65004	28850	224	0	1	1	1	1	0	0	0	0	0	0	6	0	0	0	4772	28504	0	0	16389	6009	1000	3009	2000	1000	3000	2000	5000	10000	35706	8	0	0	22969	28638	28851	3	10	6000	2000	3000	3000	6000	28676	28549	1	1	61001	1000	1000	0	2004	3	4	2002	0	0	1	2	2002	4	2	4	2	2	0	13254	9330	6889	3170	1	61	19480	3188	3821	24	62	65	28150	1000	15470	12742	13552	2000	3000	1000	28815	28804	28928	28849	28863
65004	28826	224	0	1	2	0	1	1	1	0	0	0	0	54	352	0	0	4829	28517	0	0	16283	6009	1000	3009	2000	1000	3000	2000	5000	10000	35740	4	0	0	22944	28545	28688	3	10	6000	2000	3000	3000	6000	28807	28515	1	1	61001	1000	1000	0	2003	2	0	2004	0	0	1	2	2000	4	2	0	2	1	0	13236	9613	7061	3179	0	57	19734	3304	3819	23	65	68	28272	1000	15452	12375	13889	2000	3000	1000	28633	28715	28781	28880	28805
65004	28673	222	0	0	1	1	1	1	1	0	0	0	0	27	0	0	0	4776	28393	0	0	16378	6009	1000	3009	2000	1000	3000	2000	5000	10000	35611	12	0	8	22932	28784	28867	3	10	6000	2000	3000	3000	6000	28539	28551	1	1	61001	1000	1000	0	2003	0	4	2004	0	1	1	2	2000	4	2	4	2	1	0	13330	9333	6977	3167	0	71	19664	3153	3821	26	66	59	28257	1000	15768	12775	13797	2000	3000	1000	28665	28811	28787	28712	28755
65004	28794	223	0	1	2	1	0	1	1	0	0	0	1	444	0	1	0	4703	28484	0	0	16524	6009	1000	3009	2000	1000	3000	2000	5000	10000	35746	4	0	0	22928	28685	28766	3	10	6000	2000	3000	3000	6000	28681	28758	1	1	61001	1000	1000	0	2002	4	4	2003	1	0	3	2	2000	4	2	4	2	2	216	13103	9275	6949	3205	0	69	19730	3187	3825	23	62	68	28246	1000	15316	12718	13624	2000	3000	1000	28997	29018	29001	28949	28968
65004	28642	222	0	1	1	1	0	3	0	0	0	0	0	6	0	0	0	5069	27953	0	0	15899	6003	1000	3009	2000	1000	3000	2000	5000	10000	35721	7	0	0	22927	28346	28329	3	10	6000	2000	3000	3000	6000	28310	28106	1	1	61001	1000	1000	0	2003	3	4	2003	0	1	0	8	2000	4	2	4	2	1	0	13724	10300	7170	3397	0	58	19173	3394	3829	20	56	63	27866	1000	14089	12153	12816	2000	3000	1000	28328	28460	28130	28321	28404
65004	28363	213	0	1	2	0	0	2	1	0	0	0	0	267	0	1	0	5159	28082	0	0	16171	6003	1000	3009	2000	1000	3000	2000	5000	10000	35721	4	0	0	22967	28274	28368	3	10	6000	2000	3000	3000	6000	28242	28186	1	1	61001	1000	1000	0	2003	3	0	2003	0	0	2	2	2000	4	2	0	2	0	0	13839	10073	7234	3400	0	60	19189	3417	3824	24	60	57	27880	1000	14624	11969	12998	2000	3000	1000	28405	28265	28290	28277	28365

Count: 8

Code:

  ld3r { v0.1d, v1.1d, v2.1d }, [x6], x8
  ld3r { v0.1d, v1.1d, v2.1d }, [x6], x8
  ld3r { v0.1d, v1.1d, v2.1d }, [x6], x8
  ld3r { v0.1d, v1.1d, v2.1d }, [x6], x8
  ld3r { v0.1d, v1.1d, v2.1d }, [x6], x8
  ld3r { v0.1d, v1.1d, v2.1d }, [x6], x8
  ld3r { v0.1d, v1.1d, v2.1d }, [x6], x8
  ld3r { v0.1d, v1.1d, v2.1d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	80070	620	1	0	0	1	0	0	0	0	23	0	1	0	2	80027	2	15	15	0	25	480169	80100	240044	160000	80100	240000	160000	480499	959996	3121073	80023	80042	80042	0	0	3	24	480100	200	160000	240000	200	240162	480000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	0	160030	0	0	0	90	160030	6	1	0	0	0	0	0	5109	1	17	1	1	80039	1	80000	10	6	160000	240000	80100	80043	80043	80043	80043	80043
400204	80042	621	0	0	0	0	0	0	0	0	35	0	0	0	1	80027	0	12	0	0	25	480155	80100	240054	160000	80100	240000	160000	480499	963347	3121065	80023	80042	80042	0	0	3	24	480100	200	160000	240000	200	240000	480000	80127	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	0	160000	0	0	2	57	160036	6	1	47	40	10	0	0	5109	1	17	1	1	80039	0	80000	9	9	160000	240000	80100	80043	80043	80043	80043	80043
400204	80042	620	1	0	0	0	0	0	0	0	54	0	0	0	2	80027	2	15	15	0	25	480169	80100	240054	160000	80100	240000	160000	480499	960223	3121073	80023	80042	80042	0	0	3	24	480100	200	160000	240000	200	240000	480000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	0	160022	0	0	0	696	160000	6	1	22	33	0	0	0	5109	1	17	1	1	80039	0	80000	0	10	160000	240000	80100	80156	80043	80043	80043	80043
400204	80042	620	1	0	0	0	0	0	0	0	76	0	0	1	2	80027	3	15	0	0	25	480172	80100	240210	160000	80100	240000	160000	480499	960338	3121065	80023	80154	80042	0	0	3	24	480100	200	160000	240000	200	240000	480000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	25	160030	0	95	0	21	160030	6	1	29	33	0	0	0	5109	1	17	1	1	80039	0	80000	0	10	160000	240000	80100	80043	80043	80043	80043	80043
400204	80042	621	0	0	0	0	0	0	0	0	27	0	0	0	1	80027	2	12	12	0	25	480155	80100	240042	160000	80100	240000	160000	480499	960328	3121073	80023	80042	80042	0	0	3	24	480100	200	160000	240000	200	240000	480000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	0	160000	0	0	0	25	160000	6	1	21	33	0	0	0	5109	1	17	1	1	80039	1	80000	10	10	160000	240000	80100	80043	80043	80043	80043	80043
400204	80042	621	0	0	0	0	0	0	0	0	12	0	0	0	1	80027	2	12	12	0	25	480154	80154	240510	160216	80262	240486	160324	481466	971293	3144502	80349	80341	80339	76	0	42	214	480748	200	160216	240486	200	240486	480972	80420	80415	4	1	80201	100	99	100	100	80000	80000	0	100	160104	0	0	160336	1	0	0	1788	160000	0	0	22	33	0	0	0	5109	1	25	1	1	80039	1	80000	10	6	160000	240000	80100	80043	80043	80043	80043	80043
400204	80042	620	0	0	0	0	0	1	0	0	35	88	0	0	1	80027	2	12	12	0	25	480155	80100	240054	160000	80100	240000	160000	480499	960338	3120106	80023	80042	80042	0	0	33	24	480100	200	160000	240000	200	240000	480000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	25	160030	0	0	0	697	160030	6	1	22	33	0	0	0	5109	1	17	1	1	80132	1	80000	10	6	160000	240000	80100	80043	80043	80156	80043	80043
400204	80042	620	0	0	0	0	0	0	0	0	36	0	0	0	1	80027	2	12	12	0	25	480100	80100	240054	160000	80100	240000	160108	480499	959996	3120079	80023	80042	80042	23	0	3	24	480100	200	160000	240000	200	240000	480000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	25	160029	0	0	0	30	160029	0	0	30	33	0	0	0	5109	1	17	1	1	80039	0	80000	10	10	160000	240000	80100	80043	80043	80043	80043	80043
400204	80042	620	0	0	0	0	0	0	0	0	48	0	0	0	1	80027	0	12	12	0	25	480155	80100	240054	160000	80100	240000	160000	480499	960338	3121065	80023	80042	80042	0	7	16	24	480100	200	160000	240000	200	240000	480000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	25	160134	0	2	0	36	160020	6	1	29	33	0	0	0	5109	1	17	1	1	80039	0	80000	0	6	160000	240000	80100	80043	80043	80043	80043	80043
400204	80042	620	0	0	0	0	0	1	0	0	36	0	0	0	0	80027	0	12	0	0	25	480100	80100	240055	160000	80100	240000	160000	480499	960328	3121073	80023	80042	80042	0	0	3	24	480100	200	160000	240000	200	240000	480000	80042	80042	2	1	80201	100	99	100	100	80000	80000	0	100	160000	0	25	160029	0	0	3	33	160029	6	1	30	33	0	0	0	5109	1	17	1	1	80039	1	80000	12	6	160000	240000	80100	80043	80043	80043	80043	80043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	80055	620	0	0	0	0	0	0	0	54	0	1	0	2	80027	2	12	12	0	25	480073	80010	240063	160000	80010	240000	160000	480049	960724	3123203	0	0	80023	0	80042	80042	0	3	24	480010	20	160000	240000	20	240000	480000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	33	160037	1	0	40	160000	0	1	30	0	0	5019	0	0	9	17	9	8	80039	0	80000	14	10	160000	240000	80010	80043	80043	80043	80043	80043
400024	80042	620	0	0	0	0	0	0	0	43	0	1	0	2	80027	2	12	12	0	25	480010	80010	240000	160000	80010	240000	160000	480049	960649	3121857	0	0	80023	0	80042	80042	0	3	24	480010	20	160000	240000	20	240000	480000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	33	160037	0	0	38	160029	6	1	37	41	0	5019	0	0	8	25	8	9	80039	0	80000	14	14	160000	240000	80010	80043	80043	80043	80043	80043
400024	80042	620	0	0	0	0	0	0	0	43	88	1	0	2	80027	2	12	12	0	25	480073	80010	240000	160000	80010	240000	160000	480049	960649	3123335	0	0	80023	0	80042	80042	0	3	24	480010	20	160000	240000	20	240000	480000	80042	80154	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	0	160037	0	0	40	160037	6	1	30	41	0	5019	0	0	9	17	8	9	80039	0	80000	15	14	160000	240000	80010	80043	80043	80043	80043	80043
400024	80042	621	0	0	0	0	0	0	0	43	0	1	0	2	80027	2	12	12	0	25	480073	80010	240063	160000	80010	240000	160000	480049	960703	3121763	0	0	80023	0	80042	80042	0	3	24	480010	20	160124	240000	20	240000	480000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	33	160037	0	0	37	160037	6	1	37	41	0	5019	0	0	9	17	9	9	80039	0	80000	14	10	160000	240000	80010	80043	80043	80043	80043	80043
400024	80042	621	0	0	0	0	0	0	0	55	0	0	0	2	83195	2	12	12	0	25	480010	80010	240063	160000	80010	240000	160108	480049	960659	3121827	0	0	80023	0	80042	80042	0	3	24	480010	20	160000	240000	20	240000	480000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160102	0	41	160037	1	0	37	160037	6	1	0	0	0	5019	0	0	5	17	9	9	80039	0	80000	0	10	160000	240000	80010	80300	80043	80043	80043	80043
400024	80042	622	0	0	0	0	0	0	0	43	0	0	0	2	80027	2	0	12	0	25	480073	80010	240054	160000	80010	240000	160000	480049	960650	3121763	0	0	80023	0	80042	80042	0	3	24	480010	20	160000	240000	20	240000	480000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	41	160000	0	0	29	160000	6	1	29	41	0	5019	0	0	10	17	9	9	80039	0	80000	15	0	160000	240000	80010	80043	80043	80043	80043	80043
400024	80042	620	0	0	0	0	0	0	0	43	0	1	0	2	80027	2	12	12	0	25	480064	80010	240063	160000	80010	240000	160000	480049	960852	3121776	0	0	80023	0	80042	80042	0	3	24	480010	20	160000	240000	20	240000	480000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	41	160000	2	0	741	160037	6	0	37	41	0	5019	0	0	5	17	9	11	80039	0	80054	17	14	160000	240000	80010	80043	80043	80043	80043	80043
400024	80042	620	0	0	0	0	0	0	0	0	0	0	0	2	80027	2	12	12	0	25	480073	80010	240063	160000	80010	240000	160000	480049	960650	3121781	0	0	80023	0	80042	80042	0	3	25	480010	20	160000	240000	20	240000	480000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	0	160030	0	0	30	160030	0	0	0	0	0	5019	0	0	9	17	9	9	80039	0	80000	0	14	160000	240000	80010	80043	80043	80043	80043	80043
400024	80042	620	0	0	0	0	0	0	0	43	0	0	1	0	80027	2	0	0	0	25	480073	80010	240063	160000	80010	240000	160000	480049	959999	3121776	0	0	80023	0	80042	80042	0	3	24	480010	20	160000	240000	20	240000	480000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	33	160037	0	0	29	160030	6	1	37	41	0	5019	0	0	9	17	8	8	80039	0	80000	14	10	160000	240000	80010	80043	80043	80043	80043	80043
400024	80042	620	0	0	0	0	0	0	0	55	0	0	0	2	80027	2	0	12	0	25	480010	80010	240063	160000	80010	240000	160000	480049	959996	3119994	0	0	80023	0	80042	80042	0	3	24	480010	20	160000	240000	20	240000	480648	82541	82782	26	1	80021	10	9	10	10	80000	80000	0	10	160104	0	41	160037	0	0	37	160037	6	1	39	41	0	5019	0	0	9	17	9	8	80039	0	80000	14	16	160000	240000	80010	80043	80043	80043	80043	80043

LD3R (post-index, 1D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations