Firestorm: LD3R (post-index, 2S) measurements

Code:

  ld3r { v0.2s, v1.2s, v2.2s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.006

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5e	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	df	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
64005	29423	237	3	2	0	1	1	0	1	0	0	0	13	0	1	0	4615	28813	0	0	0	17254	5006	1000	3009	1000	1000	3000	1000	5000	5000	35691	0	11	0	0	22816	29168	29516	3	10	5000	1000	3000	2000	3000	29254	29330	1	1	61001	1000	1000	0	1000	0	3	1000	0	0	0	1000	2	0	3	0	0	13238	9344	6992	3197	0	58	20348	3283	3822	16	55	58	0	28613	1000	16079	13187	14475	1000	3000	1000	29341	29428	29522	29426	29302
64004	29399	236	0	1	0	0	0	0	0	0	0	0	2	0	0	0	4655	28850	0	0	0	17257	5006	1000	3000	1000	1000	3000	1000	5000	5000	35682	0	0	0	0	22877	29204	29410	3	10	5000	1000	3000	2000	3000	29337	29202	1	1	61001	1000	1000	0	1000	0	0	1000	0	0	0	1000	2	0	0	0	0	13468	9403	6915	3137	0	59	20535	3226	3811	13	59	66	0	28590	1000	16083	13335	14550	1000	3000	1000	29488	29386	29298	29543	29458
64004	29411	235	0	1	0	0	0	0	0	0	0	0	2	0	1	0	4828	28945	1	0	0	17204	5009	1000	3006	1000	1000	3000	1000	5000	5000	35626	0	3	0	0	22837	29233	29399	3	10	5000	1000	3000	2000	3000	29411	29263	1	1	61001	1000	1000	0	1000	0	2	1001	0	0	3	1000	2	0	2	0	0	13106	9424	6961	3118	0	57	20443	3351	3814	16	62	51	0	28773	1000	16137	13383	14466	1000	3000	1000	29396	29344	29364	29487	29523
64004	29572	236	1	1	0	0	0	0	0	0	0	0	3	0	1	0	4618	29002	0	0	0	17307	5006	1000	3000	1000	1000	3000	1000	5000	5000	35695	0	3	0	0	22799	29217	29439	3	10	5000	1000	3000	2000	3000	29348	29304	1	1	61001	1000	1000	1	1000	0	2	1000	2	0	6	1000	2	0	2	0	0	13312	9317	6940	3145	0	59	20490	3348	3815	22	60	56	0	28602	1000	16320	13515	14375	1000	3000	1000	29427	29447	29471	29441	29425
64004	29353	236	0	0	0	0	1	0	0	0	0	0	2	0	0	0	4672	28938	0	0	0	17292	5000	1000	3000	1000	1000	3000	1000	5000	5000	35605	0	3	0	0	22789	29185	29497	3	10	5000	1000	3000	2000	3000	29197	29360	1	1	61001	1000	1000	0	1000	0	2	1000	0	0	0	1001	0	0	0	0	0	13112	9255	6942	3121	0	65	20629	3243	3814	17	58	59	0	28697	1000	16027	13435	14499	1000	3000	1000	29533	29524	29643	29500	29441
64004	29398	236	0	0	0	0	1	0	0	0	0	0	11	0	0	0	4708	28916	0	0	0	16998	5006	1000	3000	1000	1000	3000	1000	5000	5002	35695	0	5	0	0	22801	29335	29628	3	10	5000	1000	3000	2000	3000	29290	29258	1	1	61001	1000	1000	1	1000	0	2	1000	0	0	0	1000	2	0	0	0	0	13217	9258	6982	3171	0	56	20358	3244	3815	17	63	52	0	28649	1000	16185	13456	14385	1000	3000	1000	29373	29370	29368	29366	29440
64004	29497	236	0	1	0	0	1	0	0	0	0	0	9	0	0	0	4671	28901	0	0	0	17158	5006	1000	3006	1000	1000	3000	1000	5000	5000	35706	0	6	0	0	22867	29202	29416	3	10	5000	1000	3000	2000	3000	29335	29313	1	1	61001	1000	1000	0	1000	0	0	1000	0	0	0	1000	2	0	0	0	0	13337	9278	6977	3160	1	69	20476	3249	3815	13	54	55	0	28728	1000	16321	13188	14486	1000	3000	1000	29462	29477	29398	29399	29545
64004	29490	237	0	0	0	0	1	0	0	0	0	0	3	0	0	0	4558	28859	0	0	0	17347	5006	1000	3006	1000	1000	3000	1000	5000	5000	35688	0	4	0	0	22825	29217	29503	6	10	5000	1000	3000	2000	3000	29152	29245	1	1	61001	1000	1000	1	1000	0	0	1000	1	0	1	1000	0	0	0	0	0	13320	9279	6976	3190	0	55	20342	3206	3814	15	59	64	0	28573	1000	16293	13395	14603	1000	3000	1000	29275	29466	29428	29429	29427
64004	29509	237	0	0	0	0	1	0	0	0	0	0	0	0	0	0	4761	28994	0	0	0	17209	5006	1000	3006	1000	1000	3000	1000	5000	5000	35606	0	0	0	0	22761	29191	29391	3	10	5000	1000	3000	2000	3000	29425	29141	1	1	61001	1000	1000	0	1000	0	2	1000	0	0	0	1000	2	0	2	0	0	13195	9470	6924	3261	0	58	20421	3294	3814	10	61	58	0	28650	1000	16078	13457	14517	1000	3000	1000	29412	29457	29525	29339	29481
64004	29394	237	0	0	0	0	0	0	0	0	0	0	2	0	0	0	4764	28990	0	0	0	17162	5006	1000	3006	1000	1000	3000	1000	5000	5000	35687	0	4	0	0	22829	29231	29476	3	10	5000	1000	3000	2000	3000	29277	29270	1	1	61001	1000	1000	0	1003	0	2	1000	0	0	0	1000	2	0	0	0	0	13092	9399	6926	3160	0	55	20356	3260	3818	16	56	56	0	28645	1000	16205	13435	14376	1000	3000	1000	29440	29486	29060	29465	29391

Count: 8

Code:

  ld3r { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld3r { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld3r { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld3r { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld3r { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld3r { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld3r { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld3r { v0.2s, v1.2s, v2.2s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320205	80069	621	1	1	1	0	1	1	1	0	0	0	31	0	0	0	1	80097	1	6	6	0	0	25	400163	80100	240075	80000	80100	240000	80000	480499	480031	3132807	0	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80006	6	22	80026	0	0	0	25	80018	6	1	25	23	5	0	0	5111	5	25	2	5	3	80039	1	80000	0	0	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	620	1	1	0	1	1	1	0	1	0	0	162	0	0	0	1	80027	1	6	0	0	3	25	400164	80100	240075	80000	80100	240000	80000	480499	480031	3122599	0	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240120	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80006	6	22	80024	0	0	0	25	80019	6	1	24	22	6	0	0	5111	5	17	1	5	4	80102	1	80000	9	9	80000	240000	80100	80043	80043	80043	80118	80043
320204	80042	621	1	1	0	0	1	1	0	0	0	0	29	0	0	0	2	80027	1	6	6	0	0	25	400175	80100	240064	80000	80100	240000	80000	480499	481647	3132805	0	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80006	6	23	80024	0	0	1	27	80018	6	1	25	23	5	0	0	5111	3	17	2	5	5	80039	1	80000	9	9	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	621	1	1	1	1	1	1	1	0	0	0	29	0	0	0	1	80103	1	6	6	0	0	25	400175	80100	240064	80040	80100	240000	80000	480499	480034	3122536	0	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80005	6	23	80025	0	0	1	28	80018	6	1	25	23	5	0	0	5111	5	17	1	5	3	80039	1	80000	9	9	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	620	1	1	2	0	1	0	0	0	0	0	161	0	0	0	1	80027	1	0	6	0	0	25	400164	80100	240063	80000	80100	240000	80000	480499	479998	3122536	0	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80005	6	23	80024	0	0	0	24	80018	6	1	25	23	5	0	0	5111	5	17	1	5	5	80039	1	80000	9	10	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	622	1	1	1	0	1	0	1	1	0	0	30	0	0	0	1	80027	1	6	6	0	0	25	400164	80100	240075	80000	80100	240000	80000	480737	480023	3122536	0	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80005	6	23	80007	0	0	0	24	80018	0	1	23	23	6	0	1	5111	4	17	2	3	5	80039	0	80000	10	9	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	620	1	1	0	1	1	0	0	0	0	0	5	0	0	0	2	80027	1	6	6	0	0	48	400163	80100	240080	80000	80100	240000	80000	480499	480023	3122536	0	80023	80042	80042	0	3	24	400100	200	80000	240120	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80006	7	22	80025	0	1	1	27	80020	6	1	25	23	5	1	0	5111	3	17	1	5	4	80039	1	80000	0	9	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	621	1	1	0	0	1	0	0	0	0	0	163	0	0	0	1	80027	1	6	6	11	0	25	400163	80100	240075	80000	80100	240000	80000	480499	480023	3122536	0	80023	80042	80042	0	10	24	400100	200	80000	240120	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80007	6	22	80024	0	3	0	584	80019	6	1	23	23	6	0	0	5111	5	17	1	5	5	80039	0	80000	9	9	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	620	1	1	0	0	1	1	0	0	0	0	29	0	0	0	1	80027	1	6	6	0	0	25	400169	80140	240189	80000	80100	240000	80000	480499	480023	3122536	0	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240120	80042	80042	2	1	80201	100	99	100	100	80000	80000	0	100	80007	6	22	80024	0	0	0	26	80000	6	1	24	22	6	0	0	5111	4	17	1	3	4	80039	1	80000	9	9	80000	240000	80100	80043	80043	80043	80043	80118
320204	80042	620	1	1	1	0	1	0	0	0	0	0	163	0	0	0	1	80027	1	6	6	0	0	25	400164	80100	240018	80000	80100	240000	80000	480499	480023	3122591	0	80023	80042	80042	0	3	52	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80007	6	23	80027	0	1	1	25	80020	0	1	27	22	6	0	0	5111	5	17	1	5	5	80039	1	80000	9	9	80000	240000	80100	80043	80043	80043	80043	80118

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	80056	620	1	1	0	1	1	0	0	40	0	0	0	0	80027	1	6	6	0	0	25	400073	80010	240064	80000	80010	240000	80000	480049	480073	3122748	80078	0	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80007	5	22	80025	0	0	0	26	80019	6	1	24	22	6	0	0	5019	1	17	1	1	80039	1	80000	9	9	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	1	0	1	1	1	0	0	41	0	0	0	1	80027	1	6	6	0	0	25	400085	80010	240064	80000	80010	240000	80000	480049	480032	3122536	80023	0	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80006	7	23	80024	0	0	0	585	80018	6	1	24	22	6	0	1	5019	1	17	1	1	80124	0	80000	9	0	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	1	0	0	1	1	0	0	31	0	0	0	2	80027	1	6	6	0	0	25	400073	80010	240063	80000	80010	240000	80000	480287	480023	3122536	80023	0	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80006	6	0	80023	0	0	0	27	80018	6	1	25	23	5	0	0	5019	1	17	1	1	80039	1	80000	9	9	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	1	1	0	1	1	0	0	162	0	0	0	1	80027	1	6	6	11	0	25	400073	80010	240075	80000	80010	240000	80000	480049	480046	3120140	80023	0	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80005	5	22	80024	0	0	1	23	80018	6	1	25	23	5	1	0	5019	1	17	1	1	80039	1	80000	10	9	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	1	1	1	1	1	0	0	38	0	1	0	1	80027	1	0	0	0	0	25	400074	80010	240018	80000	80010	240000	80000	480049	480034	3122481	80023	0	80042	80042	0	3	50	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80007	5	23	80025	0	0	0	42	80000	0	0	24	22	6	0	0	5019	1	17	1	1	80039	1	80000	0	9	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	1	0	0	1	1	0	0	29	0	0	0	1	80027	1	6	0	0	0	25	400074	80010	240132	80000	80010	240000	80000	480049	480023	3122536	80023	0	80117	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80006	6	23	80025	0	0	1	25	80000	6	0	24	22	6	0	0	5019	1	17	1	1	80039	0	80000	9	9	80000	240000	80010	80043	80043	80043	80116	80043
320024	80042	620	1	1	0	1	1	0	0	6	0	0	0	0	80027	0	0	0	0	0	25	400085	80010	240080	80000	80010	240000	80000	480049	480023	3122536	80023	0	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80006	5	22	80025	0	1	0	25	80018	6	1	25	23	5	1	0	5019	1	17	1	1	80039	1	80000	9	9	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	621	1	0	1	1	1	0	0	29	0	0	0	1	80027	1	6	6	0	0	25	400085	80010	240069	80000	80010	240000	80000	480049	480034	3122592	80023	0	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80007	6	24	80027	0	0	0	26	80018	6	1	23	23	6	1	0	5019	1	17	1	1	80039	1	80000	9	9	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	621	1	0	0	1	0	0	0	29	0	0	0	1	80027	1	6	6	0	0	25	400074	80010	240064	80000	80010	240000	80000	480049	480042	3122536	80023	0	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80005	6	0	80023	0	0	0	24	80018	6	1	25	23	5	1	0	5019	1	17	1	1	80039	1	80000	9	9	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	621	1	0	0	1	1	0	0	18	0	0	0	1	80027	1	6	6	0	0	25	400074	80010	240063	80000	80010	240000	80000	480049	480006	3120301	80023	0	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80005	5	23	80025	0	0	0	23	81073	6	1	23	0	6	1	0	5019	1	17	1	1	80039	1	80000	16	9	80000	240000	80010	80043	80043	80043	80043	80043

LD3R (post-index, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations