Firestorm: LD3R (post-index, 4H) measurements

Code:

  ld3r { v0.4h, v1.4h, v2.4h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.006

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	ldst x64 uop (b1)	b5	bb	l1d cache miss ld nonspec (bf)	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
64005	28639	223	3	2	0	0	0	0	0	0	0	3	0	0	0	0	4749	28379	0	0	0	16490	5009	1000	3006	1000	1000	3000	1000	5000	5002	35708	1	0	0	22830	28598	28642	3	10	5000	1000	3000	2000	3000	28676	28562	1	1	61001	1000	1000	0	1000	0	1000	0	76	1001	0	0	1	0	0	13395	9592	6977	3175	0	49	19701	3121	3808	13	48	47	28154	0	1000	15688	12390	13648	1000	3000	1000	28518	28641	28576	28619	28671
64004	28625	224	0	1	0	0	0	0	0	0	0	0	0	0	0	0	4795	28271	0	1	0	16421	5009	1000	3006	1000	1000	3000	1000	5000	5001	35681	0	0	0	22869	28463	28730	3	10	5000	1000	3000	2000	3000	28602	28538	1	1	61001	1000	1000	0	1000	3	1001	0	10	1000	0	2	3	0	0	13372	9506	6970	3198	0	49	19638	3127	3816	16	53	57	28147	0	1000	15301	12469	13697	1000	3000	1000	28669	28620	28670	28790	28812
64004	28658	222	0	0	0	0	0	0	0	0	0	3	0	0	0	0	4700	28355	0	0	0	16555	5009	1000	3006	1000	1000	3000	1000	5000	5000	35682	5	0	0	22833	28472	28588	3	10	5000	1000	3000	2000	3000	28620	28565	1	1	61001	1000	1000	0	1000	0	1001	0	159	1001	0	2	1	3	0	13123	9688	6990	3255	0	48	19650	3166	3816	14	47	59	28040	0	1000	15351	12601	13532	1000	3000	1000	28620	28698	28709	28537	28605
64004	28753	223	0	1	0	0	0	0	0	0	0	0	0	0	0	0	4802	28220	0	0	0	16522	5000	1000	3006	1000	1000	3000	1000	5000	5000	35632	5	0	0	22796	28561	28748	3	10	5000	1000	3000	2000	3000	28573	28580	1	1	61001	1000	1000	0	1000	2	1001	0	12	1001	0	0	0	0	0	13208	9535	7040	3203	1	47	19747	3201	3812	12	50	59	28111	0	1000	15509	12422	13805	1000	3000	1000	28802	28604	28706	28751	28737
64004	28644	222	0	0	0	0	0	0	0	0	0	2	0	0	0	0	4748	28373	0	1	0	16558	5006	1000	3009	1000	1000	3000	1000	5000	5000	35692	2	0	0	22820	28515	28702	3	10	5000	1000	3000	2000	3000	28577	28614	1	1	61001	1000	1000	0	1000	2	1002	0	9	1000	0	2	2	2	0	13364	9645	7019	3249	0	48	19650	3184	3809	17	52	50	28139	0	1000	15405	12650	13523	1000	3000	1000	28616	28711	28803	28694	28705
64004	28699	223	0	2	0	0	0	0	0	0	0	0	0	0	0	0	4764	28282	1	0	0	16533	5006	1000	3006	1000	1000	3000	1000	5000	5000	35711	0	0	0	22845	28615	28685	3	10	5000	1000	3000	2000	3000	28495	28590	1	1	61001	1000	1000	0	1000	2	1000	0	16	1000	0	2	0	2	0	13407	9769	6986	3192	0	52	19656	3117	3817	20	50	48	28135	0	1000	15243	12412	13614	1000	3000	1000	28746	28649	28631	28787	28676
64004	28671	222	1	0	0	1	0	0	0	0	0	2	0	0	0	0	4784	28348	0	0	0	16421	5006	1000	3006	1000	1000	3000	1000	5000	5010	35653	0	0	0	22818	28744	28738	3	10	5000	1000	3000	2000	3000	28753	28683	1	1	61001	1000	1000	0	1000	2	1000	0	66	1000	0	0	2	2	0	13439	9637	7066	3240	0	50	19715	3238	3816	20	45	47	28192	0	1000	15277	12638	13720	1000	3000	1000	28663	28756	28296	28714	28704
64004	28766	223	0	1	0	1	0	0	0	0	0	2	0	0	0	0	4842	28444	1	1	0	16542	5006	1000	3012	1000	1000	3000	1000	5000	5000	35707	1	0	0	22834	28594	28729	3	10	5000	1000	3000	2000	3000	28662	28567	1	1	61001	1000	1000	0	1000	2	1000	0	92	1001	0	1	2	2	0	13199	9661	7056	3186	1	52	19707	3164	3814	15	49	46	28163	0	1000	15413	12561	13656	1000	3000	1000	28621	28724	28658	28745	28710
64004	28718	222	0	1	0	0	0	0	0	0	0	2	0	0	0	0	4892	28352	0	0	0	16573	5000	1000	3009	1000	1000	3000	1000	5000	5000	35671	0	0	0	22816	28464	28629	3	10	5000	1000	3000	2000	3000	28698	28515	1	1	61001	1000	1000	0	1000	0	1000	0	132	1002	0	2	1	2	0	13325	9413	6995	3173	0	52	19718	3149	3814	14	49	43	28142	0	1000	15432	12729	13656	1000	3000	1000	28686	28725	28553	28836	28721
64004	28806	222	0	2	0	0	0	0	0	0	0	4	0	0	0	0	4761	28323	0	0	0	16529	5006	1000	3000	1000	1000	3000	1000	5000	5001	35731	0	0	0	22884	28493	28807	3	10	5000	1000	3000	2000	3000	28590	28649	1	1	61001	1000	1000	0	1000	0	1000	0	9	1000	0	2	0	2	0	13390	9372	7078	3154	0	53	19815	3186	3816	15	45	46	28161	0	1000	15363	12572	13770	1000	3000	1000	28670	28675	28750	28646	28728

Count: 8

Code:

  ld3r { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld3r { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld3r { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld3r { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld3r { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld3r { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld3r { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld3r { v0.4h, v1.4h, v2.4h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320205	80069	643	0	0	0	0	0	0	0	22	0	0	0	0	80027	1	6	6	0	0	25	400148	80100	240038	80000	80100	240000	80000	480499	480005	3120857	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	13	80010	26	0	555	80014	6	0	10	17	0	0	0	0	5109	1	17	2	1	80039	0	80000	9	6	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	642	0	0	0	0	0	1	1	34	0	0	0	0	80027	1	6	6	0	0	25	400138	80100	240000	80000	80100	240000	80000	480499	479999	3120932	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	2	1	80201	100	99	100	100	80000	80000	1	100	80000	0	13	80010	15	0	11	80010	5	0	9	17	0	0	0	0	5109	1	17	2	1	80039	1	80000	9	6	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	643	0	0	0	0	1	0	0	22	0	0	0	0	80027	1	6	6	0	0	25	400138	80140	240162	80040	80140	240120	80040	480975	481634	3131244	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	13	80009	53	0	19	80010	0	1	0	17	0	0	0	0	5109	1	17	1	2	80039	1	80000	0	6	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	642	0	0	0	1	0	0	0	21	0	0	0	0	80027	0	6	6	0	0	25	400148	80100	240042	80000	80100	240000	80000	480499	480006	3120865	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80009	52	0	13	80000	6	1	10	17	0	0	0	0	5109	2	17	1	2	80039	1	80000	9	9	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	643	0	0	0	0	0	0	0	36	0	0	0	0	80027	1	6	6	0	0	25	400100	80100	240038	80000	80100	240000	80000	480499	480020	3120963	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	13	80010	4	0	12	80013	5	1	9	18	0	0	0	0	5109	1	17	1	1	80039	0	80000	9	9	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	643	1	0	0	1	0	0	0	2514	2024	0	0	0	80404	1	6	6	45	12	93	400876	80262	240618	80200	80260	240600	80160	481451	488115	3172138	80333	80272	80419	28	26	133	401100	200	80160	240600	200	160400	240600	80421	80345	4	1	80201	100	99	100	100	80000	80000	0	100	80157	0	13	80158	47	0	2242	80185	5	1	10	17	0	0	0	0	5171	2	43	2	3	80291	0	80200	12	7	80000	240000	80100	80421	80347	80270	80270	80346
320204	80343	645	0	1	0	0	1	0	0	24	0	0	0	0	80027	1	0	6	0	0	25	400148	80100	240048	80000	80100	240000	80000	480499	480020	3120923	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	17	80009	5	0	10	80013	5	0	11	18	0	0	0	0	5109	2	17	1	1	80039	0	80000	9	6	80000	240000	80100	80043	80043	80043	80043	80344
320204	80042	644	0	0	0	0	0	0	0	34	0	0	1	0	80027	1	6	6	0	0	25	400138	80100	240048	80040	80100	240000	80000	480499	480016	3120861	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240120	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	2	13	80009	30	2	13	80010	6	1	9	0	0	0	0	0	5109	2	17	2	2	80102	1	80000	6	6	80000	240000	80100	80043	80043	80119	80043	80119
320204	80042	643	0	0	0	1	1	0	0	31	0	0	0	0	80027	1	6	0	0	0	25	400148	80100	240038	80000	80100	240000	80040	480499	480000	3120872	80023	80042	80042	7	3	24	400300	200	80000	240000	200	160080	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	2	17	80010	34	0	13	80000	6	1	10	17	0	0	0	0	5122	1	17	2	1	80039	1	80000	9	10	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	643	0	0	0	0	0	0	0	30	0	0	1	0	80027	1	0	6	0	0	25	400148	80100	240048	80000	80100	240000	80000	480499	480014	3128825	80023	80042	80042	0	3	24	400100	200	80040	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	13	80050	61	0	10	80000	6	0	13	17	0	0	0	0	5121	1	17	2	2	80039	1	80000	9	7	80000	240000	80100	80043	80043	80043	80043	80043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	80055	620	0	0	0	0	0	0	0	0	29	0	0	0	0	0	80027	1	0	6	0	0	25	400074	80010	240063	80000	80050	240000	80000	480049	480022	3122536	1	0	80023	80042	80117	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80006	5	23	80024	0	0	24	80018	6	1	25	23	5	0	0	0	5019	0	0	3	17	6	6	80039	1	80000	9	9	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	1	0	0	0	0	0	0	0	30	0	0	0	0	0	80027	1	6	6	0	0	25	400085	80010	240064	80000	80010	240000	80000	480049	480023	3122536	0	0	80023	80042	80042	0	8	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80007	6	22	80062	0	0	5	80018	6	1	23	22	6	1	0	0	5019	0	0	6	17	3	6	80039	1	80000	6	6	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	1	1	1	1	0	0	0	0	174	0	0	0	0	0	80027	1	6	6	0	0	25	400058	80010	240063	80000	80010	240000	80000	480049	480014	3119994	1	0	80023	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	17	80025	0	0	16	80010	6	1	6	23	5	0	0	0	5019	0	0	5	17	4	4	80039	1	80000	9	9	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	1	0	1	1	0	0	0	0	31	0	0	0	0	0	80027	1	6	6	0	0	25	400058	80010	240038	80000	80010	240000	80000	480049	480022	3122536	1	0	80085	80042	80042	0	3	24	400010	20	80000	240000	20	160080	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	6	17	80013	1	0	13	80012	6	1	24	0	0	0	0	0	5019	0	0	6	17	5	5	80039	1	80000	6	0	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	0	0	0	0	0	0	0	0	31	0	0	0	1	0	80027	1	0	6	0	0	25	400010	80010	240015	80000	80010	240000	80000	480049	479998	3119994	1	0	80023	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	17	80024	1	0	0	80012	5	1	10	13	0	0	0	0	5019	0	0	6	17	5	3	80039	0	80000	9	6	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	621	0	0	1	0	0	0	0	0	16	0	0	0	0	0	80027	0	6	6	0	0	25	400073	80010	240075	80000	80010	240000	80000	480049	480034	3122599	0	0	80023	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80006	6	0	80024	0	0	24	80018	6	1	24	23	0	0	0	0	5019	0	0	3	17	6	6	80039	1	80000	6	6	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	0	0	0	0	1	1	0	0	19	0	0	0	1	0	80027	1	6	6	0	0	25	400048	80010	240038	80000	80010	240000	80000	480049	479998	3120852	0	0	80023	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	17	80000	0	0	13	80000	6	0	10	13	0	0	0	0	5019	0	0	6	17	7	5	80039	0	80000	6	6	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	0	0	0	0	0	0	0	0	19	0	0	0	0	0	80027	1	6	6	0	0	25	400010	80010	240042	80000	80010	240000	80000	480049	480005	3120852	0	0	80023	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80000	0	0	13	80013	5	0	0	0	0	0	0	0	5019	0	0	4	17	4	6	80039	0	80000	0	0	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	0	0	0	0	0	0	0	0	18	0	0	0	0	0	80027	1	6	6	0	0	25	400010	80010	240048	80000	80010	240000	80000	480049	480006	3120852	0	0	80023	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80000	0	0	0	80013	0	0	13	0	0	0	0	0	5019	0	0	9	17	4	4	80039	1	80000	9	6	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	0	0	0	0	0	0	1	0	283	88	0	0	1	0	80027	0	6	6	11	3	46	400252	80090	240114	80080	80050	240240	80040	480287	483253	3130243	0	0	80085	80119	80118	7	10	51	400210	20	80000	240000	20	160080	240120	80042	80118	2	1	80021	10	9	10	10	80000	80000	1	10	80000	0	13	80013	0	2	1120	80013	0	1	10	0	0	0	0	0	5044	0	0	9	25	5	7	80102	1	80000	9	6	80000	240000	80010	80043	80120	80043	80119	80118

LD3R (post-index, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations