Firestorm: LD3R (post-index, 4S) measurements

Code:

  ld3r { v0.4s, v1.4s, v2.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.009

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.009

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	91	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
64005	28762	223	1	11	0	1	13	1	0	0	0	0	4	0	0	0	0	4791	28328	0	1	0	16438	5012	1000	3003	1000	1000	3000	1000	5000	5000	35693	6	22784	28545	28783	3	10	5000	1000	3000	0	2000	3000	28593	28562	1	1	61001	0	1000	1000	1	1002	3	3	1004	0	0	2	2	1001	0	2	3	1	0	0	13208	9463	6914	3158	6	46	19951	3152	3813	17	44	44	28195	1000	15388	12735	13868	1000	3000	1000	28686	28530	28673	28673	28536
64004	28741	222	1	19	1	1	16	1	0	0	0	0	5	0	0	0	0	4793	28256	0	1	0	16352	5012	1000	3012	1000	1000	3000	1000	5000	5000	35693	8	22846	28550	28639	3	30	5000	1000	3000	0	2000	3000	28443	28655	1	1	61001	0	1000	1000	0	1003	4	3	1002	0	0	1	2	1002	2	1	2	1	1	0	13374	9568	6993	3197	5	50	19682	3299	3819	10	44	47	28223	1000	15500	12785	13596	1000	3000	1000	28724	28696	28467	28662	28695
64004	28376	223	1	15	1	1	16	0	0	0	0	0	4	0	0	0	0	4712	28307	0	1	1	16423	5012	1000	3003	1000	1000	3000	1000	5000	5041	35718	5	22826	28573	28636	3	10	5000	1000	3000	0	2000	3000	28542	28469	1	1	61001	1	1000	1000	0	1001	2	3	1002	0	0	1	2	1000	2	2	3	1	1	0	13175	9425	6956	3323	5	42	19705	3187	3806	12	45	47	28061	1000	15054	12718	13627	1000	3000	1000	28668	28760	28734	28630	28603
64004	28667	223	1	18	1	0	11	0	0	0	0	0	4	0	0	0	0	4844	28321	0	0	1	16447	5012	1000	3012	1000	1000	3000	1000	5000	5000	35735	5	22864	28508	28652	3	10	5000	1000	3000	0	2002	3000	28500	28565	1	1	61001	0	1000	1000	0	1002	2	2	1003	0	0	1	4	1000	2	1	2	1	1	0	13262	9549	6959	3121	7	45	19600	3239	3815	11	43	46	28171	1000	15312	12727	13641	1000	3000	1000	28619	28744	28628	28717	28673
64004	28605	222	1	12	1	1	13	1	0	0	0	0	27	0	0	0	0	4768	28295	0	0	0	16431	5009	1000	3003	1000	1000	3000	1000	5000	5000	35661	8	22878	28617	28695	3	10	5000	1000	3000	0	2000	3000	28737	28634	1	1	61001	0	1000	1000	1	1002	1	3	1002	0	0	2	1	1000	2	2	2	1	1	0	13149	9522	6966	3158	6	49	19706	3202	3819	16	41	42	28122	1000	15624	12668	13466	1000	3000	1000	28731	28700	28747	28724	28652
64004	28652	222	1	17	1	1	12	1	0	0	0	0	4	0	0	0	0	4801	28360	0	0	0	16517	5012	1000	3003	1000	1000	3000	1000	5000	5000	35626	10	22882	28614	28658	3	10	5000	1000	3000	0	2000	3000	28556	28610	1	1	61001	0	1000	1000	0	1001	1	3	1002	0	7	1	1	1001	0	1	3	1	0	0	13424	9301	6986	3281	7	39	19547	3207	3812	16	42	48	28257	1000	15301	12686	13592	1000	3000	1000	28591	28571	28539	28532	28718
64004	28749	223	1	14	1	1	19	1	1	0	0	0	1	0	0	0	0	4606	28352	0	1	1	16447	5012	1000	3012	1000	1000	3000	1000	5000	5000	35752	0	22793	28514	28556	3	10	5000	1000	3000	0	2000	3000	28588	28540	1	1	61001	0	1000	1000	0	1001	2	0	1001	0	0	0	2	1001	2	1	0	1	1	0	13357	9715	7016	3225	7	50	19587	3222	3823	13	47	46	28084	1000	15444	12441	13611	1000	3000	1000	28643	28473	28622	28677	28660
64004	28557	222	1	14	1	1	17	1	0	0	0	0	3	0	0	0	0	4755	28302	0	0	1	16551	5012	1000	3012	1000	1000	3000	1000	5000	5005	35715	2	22798	28529	28638	3	10	5000	1000	3000	0	2000	3000	28597	28573	1	1	61001	0	1000	1000	1	1002	1	0	1004	0	0	0	2	1000	0	1	3	1	0	186	13598	9568	6972	3152	7	49	19643	3134	3812	17	39	47	28165	1000	15488	12505	13586	1000	3000	1000	28598	28705	28699	28713	28618
64004	28747	221	1	15	1	0	19	0	0	0	0	0	4	0	0	0	0	4837	28401	0	1	1	16410	5012	1000	3009	1000	1000	3000	1000	5000	5000	35712	9	22783	28459	28611	3	10	5005	1000	3000	0	2000	3000	28695	28564	1	1	61001	0	1000	1000	1	1003	3	0	1003	0	0	1	2	1001	2	2	3	1	0	0	13384	9719	6956	3166	9	41	19636	3189	3813	16	49	45	28085	1000	15476	12682	13843	1000	3000	1000	28563	28563	28714	28639	28650
64004	28657	222	1	16	0	1	16	1	0	0	0	0	1	0	0	0	0	4730	28301	1	1	1	16430	5012	1000	3003	1000	1000	3000	1000	5000	5000	35734	9	22868	28405	28558	3	10	5000	1000	3000	0	2000	3000	28682	28608	1	1	61001	0	1000	1000	1	1002	2	2	1001	0	0	1	2	1001	2	2	3	1	1	0	13188	9700	6907	3185	6	40	19587	3199	3808	13	44	43	28276	1000	15540	12596	13477	1000	3000	1000	28589	28611	28661	28525	28595

Count: 8

Code:

  ld3r { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld3r { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld3r { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld3r { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld3r { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld3r { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld3r { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld3r { v0.4s, v1.4s, v2.4s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	24	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320205	80056	620	0	0	0	1	0	0	0	34	0	0	1	80027	1	6	6	0	0	25	400175	80106	240065	80004	80108	240024	80008	480538	480057	3121682	0	80023	80043	80042	0	6	13	400140	200	80008	240024	200	160016	240024	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80001	0	18	80016	0	15	80001	0	1	0	20	0	1	1	1	5118	4	16	4	4	80039	1	80006	0	0	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	620	0	0	0	1	0	0	0	19	0	0	1	80027	1	6	6	0	0	25	400100	80100	240050	80000	80100	240000	80000	480499	480015	3121493	0	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80016	0	681	80016	6	1	16	20	0	0	0	0	5111	5	17	5	5	80039	0	80000	13	13	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	643	0	1	0	0	0	0	0	22	0	0	1	80027	1	0	6	0	0	25	400148	80100	240048	80000	80100	240000	80000	480499	480019	3120852	0	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	13	80013	1	18	80013	6	1	13	17	0	0	0	0	5111	5	17	5	5	80039	1	80000	9	6	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	621	0	0	0	0	1	0	0	18	0	0	1	80027	1	6	0	0	0	25	400148	80100	240048	80000	80100	240000	80000	480499	480014	3120913	0	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	13	80012	0	13	80013	6	1	0	17	0	0	0	0	5111	5	17	4	5	80039	1	80000	9	0	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	620	0	0	0	0	0	0	0	0	0	0	1	80027	0	6	6	0	0	25	400148	80100	240048	80000	80100	240000	80000	480499	480006	3120931	0	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	13	80012	0	18	80013	0	0	13	17	0	0	0	0	5111	4	17	5	3	80039	0	80000	9	0	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	620	0	0	0	0	0	0	0	18	0	0	1	80027	1	6	0	0	0	25	400148	80100	240048	80000	80100	240000	80000	480499	480006	3120909	0	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	13	80012	1	15	80013	6	1	9	17	0	0	0	0	5111	6	17	6	5	80039	1	80000	9	6	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	620	0	0	0	0	0	0	0	16	0	0	1	80027	1	0	6	0	0	25	400100	80100	240038	80000	80100	240000	80000	480499	480015	3120852	0	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	17	80012	1	12	80013	0	1	10	17	0	0	0	0	5111	5	17	3	5	80039	1	80000	9	9	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	620	0	0	0	0	0	0	0	15	0	0	1	80027	1	6	6	0	0	25	400148	80100	240048	80000	80100	240000	80000	480499	480006	3120910	0	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	13	80000	1	12	80015	6	1	0	0	0	0	0	0	5111	4	17	5	5	80039	0	80000	0	9	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	621	0	0	0	0	0	0	0	28	0	0	1	80027	1	6	6	0	0	25	400148	80100	240038	80000	80100	240000	80000	480499	479998	3119994	0	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	13	80012	0	12	80013	6	1	9	17	0	0	0	0	5111	5	17	6	5	80039	0	80000	9	0	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	621	0	0	0	1	0	0	0	168	0	0	1	80027	1	0	6	0	3	25	400138	80140	240048	80000	80100	240120	80000	480499	480011	3131124	0	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80117	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	0	80050	1	13	80013	6	1	10	0	2	0	0	0	5111	5	25	4	5	80039	1	80040	9	9	80000	240000	80100	80043	80043	80043	80118	80043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	24	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d0	d2	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	80055	621	0	0	0	0	0	0	0	22	0	0	0	80027	1	6	6	0	0	25	400068	80010	240051	80000	80010	240000	80000	480049	480023	3120067	0	80023	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	18	80016	0	0	15	80000	6	1	14	0	0	5019	0	0	3	17	0	0	0	3	3	80039	1	80000	10	13	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	0	0	0	0	0	0	0	22	0	0	0	80027	1	6	6	0	0	25	400061	80010	240000	80000	80010	240000	80000	480049	480037	3121898	0	80023	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80016	0	0	15	80016	6	1	14	20	0	5019	0	0	3	17	0	0	0	3	3	80039	1	80000	13	13	80000	240000	80010	80043	80043	80115	80043	80043
320024	80042	620	0	0	0	0	0	0	0	22	0	0	0	80027	1	6	6	0	0	25	400069	80010	240059	80000	80010	240000	80000	480049	480015	3121493	0	80023	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80015	1	0	0	80000	6	1	14	0	0	5019	0	0	3	17	0	0	0	3	3	80039	0	80000	0	10	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	0	0	0	0	0	0	0	32	0	0	0	80027	1	6	6	0	0	25	400069	80010	240059	80000	80010	240000	80000	480049	480265	3121493	0	80023	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80016	0	0	3	80000	6	1	15	20	0	5019	0	0	3	17	0	0	0	3	3	80039	0	80000	13	13	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	636	0	0	0	0	0	0	0	22	0	1	0	80027	1	6	6	0	0	25	400069	80010	240051	80000	80010	240000	80000	480049	480015	3121493	0	80023	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80014	0	0	13	80000	0	1	16	20	0	5019	0	3	3	17	0	0	0	4	3	80039	0	80000	13	13	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	0	0	0	0	0	0	0	21	0	0	0	80027	0	6	6	0	0	25	400069	80010	240059	80000	80010	240000	80000	480049	480021	3121898	0	80023	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80000	0	0	18	80016	6	0	14	20	0	5019	0	0	2	17	0	0	0	3	3	80039	1	80000	33	13	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	0	0	0	1	0	0	0	21	0	0	0	80027	1	6	0	0	0	25	400069	80010	240000	80000	80010	240000	80000	480049	479998	3119994	0	80023	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80014	0	0	13	80015	6	1	0	20	0	5019	0	0	3	17	0	0	0	2	3	80039	1	80000	10	13	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	621	0	0	0	0	0	0	0	0	0	0	0	80027	0	6	0	0	0	25	400068	80010	240059	80000	80010	240000	80000	480049	480015	3121493	0	80023	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80115	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	20	80000	1	0	0	80014	6	1	14	20	0	5019	0	0	2	17	0	0	0	3	3	80039	1	80000	10	13	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	0	0	0	0	0	0	0	0	0	0	0	80331	1	6	6	0	0	25	400061	80010	240051	80000	80010	240000	80000	480049	480019	3121493	0	80023	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	20	80015	0	0	22	80016	6	1	14	18	0	5019	0	0	3	17	0	0	0	2	3	80039	1	80000	13	13	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	0	0	0	0	0	0	0	45	0	0	0	80027	1	0	0	0	0	25	400069	80010	240058	80000	80010	240000	80000	480049	480015	3121555	0	80023	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	20	80015	1	0	37	80016	6	1	0	0	0	5019	0	0	4	17	0	0	0	3	3	80039	1	80000	13	10	80000	240000	80010	80043	80043	80043	80043	80043

LD3R (post-index, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations