Firestorm: LD3R (post-index, 8B) measurements

Code:

  ld3r { v0.8b, v1.8b, v2.8b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.009

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.009

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5e	5f	61	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
64005	28781	224	1	2	0	0	1	1	1	1	0	0	3	0	0	0	0	4778	28362	1	0	16519	5009	1000	3003	1000	1000	3000	1000	5000	5000	35704	0	14	0	22875	0	28586	28693	3	10	5000	1000	3000	2000	3000	28624	28516	1	1	61001	1000	1000	0	1002	3	3	1003	0	0	2	4	1000	2	1	2	1	1	0	13238	9503	6968	3212	1	58	19553	3190	3820	27	57	55	28046	1000	14895	12808	13631	1000	3000	1000	28715	28660	28761	28708	28743
64004	28694	222	1	1	1	1	1	0	1	1	0	0	3	0	1	0	0	4694	28285	0	0	16555	5009	1000	3003	1000	1000	3000	1000	5000	5000	35628	0	21	0	22861	0	28497	28649	3	10	5000	1000	3000	2000	3000	28519	28460	1	1	61001	1000	1000	0	1002	2	2	1003	0	0	0	1	1000	0	1	2	1	2	0	13244	9507	6952	3180	0	60	19654	3216	3817	27	59	63	28054	1000	15473	12394	13651	1000	3000	1000	28651	28683	28715	28587	28580
64004	28606	223	1	2	1	1	0	1	1	1	0	0	3	0	0	0	0	4681	28261	0	0	16509	5009	1000	3012	1000	1000	3000	1000	5000	5000	35764	0	14	8	22844	0	28554	28701	3	10	5000	1000	3000	2000	3000	28635	28548	1	1	61001	1000	1000	0	1002	1	2	1002	0	0	1	1	1000	2	1	0	1	1	0	13301	9584	6964	3151	0	60	19708	3192	3817	26	65	60	27994	1000	15541	12566	13364	1000	3000	1000	28652	28695	28603	28731	28669
64004	28715	232	1	1	0	0	1	1	1	1	0	0	3	0	0	0	0	4757	28394	0	0	16532	5009	1000	3009	1000	1000	3000	1000	5000	5000	35705	0	20	0	22848	0	28534	28725	3	10	5000	1000	3000	2000	3000	28586	28533	1	1	61001	1000	1000	0	1003	0	0	1002	0	0	2	1	1000	2	1	2	1	2	0	13142	9647	6950	3264	0	55	19718	3205	3828	20	64	56	28102	1000	15438	12634	13774	1000	3000	1000	28635	28668	28764	28774	28699
64004	28748	223	1	1	1	1	2	1	1	0	0	0	1	0	0	0	0	4984	28255	0	0	16586	5009	1000	3009	1000	1000	3000	1000	5000	5000	35634	0	14	0	22865	0	28666	28752	3	10	5000	1000	3000	2000	3000	28539	28618	1	1	61001	1000	1000	1	1003	3	0	1002	0	0	1	0	1000	0	1	2	1	1	0	13281	9451	7004	3198	0	59	19640	3228	3837	24	66	64	28227	1000	15271	12716	14020	1000	3000	1000	28645	28643	28695	28889	28623
64004	28657	223	1	1	1	1	2	1	0	0	0	0	13	0	0	0	0	4850	28241	0	0	16405	5003	1000	3009	1000	1000	3000	1000	5000	5000	35713	0	5	0	22850	0	28581	28597	3	10	5000	1000	3000	2000	3000	28532	28716	1	1	61001	1000	1000	0	1002	2	0	1002	0	0	1	1	1000	2	1	3	1	0	0	13379	9690	6907	3184	0	61	19693	3168	3828	22	59	64	28129	1000	15429	12507	13496	1000	3000	1000	28698	28641	28618	28624	28616
64004	28675	222	1	2	1	1	2	1	1	0	0	0	3	0	0	0	0	4798	28396	0	0	16528	5003	1000	3003	1000	1000	3000	1000	5000	5000	35709	0	14	8	22885	0	28384	28696	3	10	5000	1000	3000	2000	3000	28502	28603	1	1	61001	1000	1000	0	1002	2	2	1003	0	0	0	1	1000	2	1	0	1	1	0	13404	9559	6958	3293	0	58	19641	3171	3826	18	54	61	28160	1000	15365	12661	13635	1000	3000	1000	28670	28681	28660	28716	28591
64004	28748	223	1	2	1	1	0	1	1	0	0	0	1	0	0	0	0	4810	28422	0	0	16531	5009	1000	3003	1000	1000	3000	1000	5000	5000	35632	0	5	0	22893	0	28604	28698	3	10	5000	1000	3000	2000	3000	28655	28552	1	1	61001	1000	1000	0	1002	2	2	1002	0	0	1	1	1000	2	1	0	1	1	0	13311	9471	7059	3205	0	56	19765	3185	3829	24	66	59	28224	1000	15233	12703	13776	1000	3000	1000	28705	28758	28717	28701	28750
64004	28683	222	1	0	1	1	1	0	1	1	0	0	15	0	1	0	0	4748	28310	0	0	16471	5009	1000	3009	1000	1000	3000	1000	5000	5000	35706	0	7	9	22849	0	28620	28670	3	10	5000	1000	3000	2000	3000	28553	28743	1	1	61001	1000	1000	0	1001	1	2	1002	0	0	1	4	1000	2	1	0	1	0	0	13405	9732	7018	3127	0	61	19651	3174	3824	17	55	55	28210	1000	15392	12750	13589	1000	3000	1000	28721	28616	28660	28691	28686
64004	28648	223	1	1	1	1	0	1	1	1	0	0	1	0	0	0	0	4851	28422	0	0	16597	5003	1000	3009	1000	1000	3000	1000	5000	5000	35710	0	1	9	22864	0	28577	28736	3	10	5000	1000	3000	2000	3000	28655	28605	1	1	61001	1000	1000	0	1000	2	2	1003	0	0	1	1	1000	2	1	0	1	1	0	13532	9515	7010	3174	0	58	19557	3181	3825	14	63	65	28160	1000	15514	12768	13471	1000	3000	1000	28737	28784	28571	28763	28733

Count: 8

Code:

  ld3r { v0.8b, v1.8b, v2.8b }, [x6], x8
  ld3r { v0.8b, v1.8b, v2.8b }, [x6], x8
  ld3r { v0.8b, v1.8b, v2.8b }, [x6], x8
  ld3r { v0.8b, v1.8b, v2.8b }, [x6], x8
  ld3r { v0.8b, v1.8b, v2.8b }, [x6], x8
  ld3r { v0.8b, v1.8b, v2.8b }, [x6], x8
  ld3r { v0.8b, v1.8b, v2.8b }, [x6], x8
  ld3r { v0.8b, v1.8b, v2.8b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320205	80069	621	0	0	0	0	0	0	0	0	0	0	1	0	0	80027	1	6	6	0	9	25	400150	80100	240051	80000	80100	240000	80000	480499	479998	3121493	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80111	0	18	80014	0	0	16	80014	6	1	13	18	0	0	5109	1	17	1	1	80039	0	80000	13	0	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	620	0	0	0	0	1	1	0	0	0	0	1	0	0	80027	1	6	6	0	0	25	400159	80100	240051	80000	80100	240000	80000	480499	479998	3121493	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80015	0	0	14	80014	6	1	0	18	0	0	5109	1	17	1	1	80039	0	80000	10	13	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	621	1	0	0	0	0	0	0	0	34	0	1	0	0	80027	1	6	6	0	0	25	400159	80100	240051	80000	80100	240000	80000	480499	480011	3121555	80023	80042	80042	0	3	24	400100	200	80040	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80013	0	0	15	80014	6	1	14	18	0	0	5109	1	17	1	1	80039	1	80000	10	10	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	621	0	0	0	0	0	0	0	0	29	0	0	0	0	80027	1	6	6	0	0	59	400151	80100	240051	80000	80100	240000	80000	480499	480007	3119994	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80014	1	0	13	80014	6	1	14	20	0	0	5109	1	17	1	1	80039	1	80000	10	10	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	620	0	0	0	0	0	0	0	0	30	0	0	0	0	80027	1	6	6	0	0	25	400151	80100	240051	80000	80100	240000	80000	480499	480011	3121493	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80018	1	0	14	80014	6	1	0	20	0	0	5109	1	17	1	1	80039	0	80000	10	10	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	620	0	0	0	0	0	0	0	0	19	0	0	0	0	80027	1	0	6	0	0	25	400151	80100	240051	80000	80100	240000	80000	480499	480011	3121493	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80014	2	0	16	80013	6	1	13	18	0	0	5109	1	17	1	1	80039	0	80000	10	10	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	620	0	0	0	0	0	0	0	0	0	0	0	0	0	80027	0	6	6	0	0	25	400159	80140	240051	80000	80100	240000	80000	480499	480015	3119994	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80118	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80013	1	0	14	80000	6	0	16	20	0	0	5109	1	17	1	1	80039	1	80000	13	10	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	620	0	0	0	0	0	0	0	0	0	0	0	0	0	80027	1	6	6	0	0	25	400151	80100	240059	80000	80100	240000	80000	480499	481632	3121493	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80037	0	18	80014	0	0	17	80013	0	1	14	18	0	0	5121	1	17	1	1	80039	1	80000	13	10	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	621	0	0	0	0	1	1	1	0	34	0	0	0	0	80027	1	6	6	0	0	25	400159	80100	240059	80000	80100	240000	80000	480499	480019	3121493	80023	80042	80042	0	3	52	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80052	0	0	17	80014	6	1	16	20	0	0	5109	1	17	0	1	80038	1	80000	13	13	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	620	0	0	0	0	0	0	0	0	20	0	0	0	0	80027	1	6	6	0	0	25	400159	80100	240000	80000	80100	240000	80000	480499	480007	3121547	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80016	0	0	14	80000	6	1	14	20	0	0	5109	1	17	1	1	80039	0	80000	13	10	80000	240000	80100	80043	80043	80043	80043	80043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	80055	621	0	0	1	0	1	0	0	0	43	0	1	0	0	1	80027	10	6	6	0	0	25	400097	80010	240037	80000	80010	240000	80000	480287	480011	3120766	80023	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	1	10	80006	6	35	80024	0	2	1	37	80014	6	1	25	27	0	0	0	5019	8	17	13	6	80039	0	80000	9	9	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	621	1	0	0	0	0	0	0	0	31	0	0	0	0	0	80027	10	6	15	0	0	25	400095	80010	240038	80000	80010	240000	80000	480049	480063	3120979	80023	80342	80042	0	3	24	400010	20	80000	240120	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	25	80020	0	0	0	571	80010	6	1	25	0	0	0	0	5019	13	17	13	13	80039	0	80000	6	6	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	1	0	0	0	0	0	0	0	42	0	0	0	0	0	80027	9	7	0	0	0	25	400048	80010	240084	80040	80010	240000	80000	480049	480005	3122592	80023	80116	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80006	5	36	80038	0	0	1	16	80031	6	1	23	0	0	0	0	5019	14	17	13	8	80039	0	80000	6	0	80000	240000	80010	80043	80043	80043	80043	80119
320025	80042	620	0	0	0	0	0	0	0	0	30	0	0	0	0	0	80027	1	6	15	0	0	25	400058	80010	240038	80000	80010	240000	80000	480049	481648	3120851	80023	80042	80042	7	3	52	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80006	6	25	80072	0	2	0	22	80032	6	1	10	28	6	0	0	5019	9	17	13	6	80039	1	80000	6	6	80000	240000	80010	80043	80043	80043	80043	80043
320024	80116	620	0	0	0	0	0	0	0	0	20	0	0	0	0	0	80027	1	6	10	0	0	25	400074	80010	240072	80000	80010	240000	80000	480049	480022	3120852	80023	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80006	5	17	80020	0	0	0	20	80022	6	0	10	23	6	0	0	5019	13	17	13	8	80039	1	80000	6	6	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	0	0	0	0	0	1	0	0	19	0	0	0	0	0	80027	10	0	6	0	0	25	400053	80050	240015	80000	80010	240000	80000	480049	480006	3121286	80023	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	2	1	80021	10	9	10	10	80000	80000	0	10	80000	6	23	80005	0	1	0	9	80020	6	1	20	23	6	1	1	5019	14	17	13	6	80039	0	80000	6	6	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	621	0	0	0	0	0	0	0	0	5	0	0	0	0	0	80027	1	6	10	0	0	25	400097	80010	240087	80000	80010	240000	80000	480287	480023	3122342	80051	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80037	0	35	80020	0	0	0	20	80021	5	1	13	27	0	0	0	5019	11	17	13	13	80039	0	80000	6	0	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	1	0	0	0	0	0	1	0	28	0	1	0	0	0	80027	1	0	6	0	0	25	400080	80010	240075	80000	80010	240000	80000	480049	480006	3122342	80023	80042	80042	0	3	49	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	36	80059	0	1	0	13	80022	6	1	24	0	0	0	0	5019	13	17	13	13	80039	1	80000	6	6	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	1	0	0	0	0	0	0	0	28	0	0	0	0	0	80027	5	6	0	0	0	25	400082	80010	240038	80000	80010	240000	80000	480049	480027	3122342	80023	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80022	10	9	10	10	80000	80000	0	10	80000	0	26	80024	0	0	0	22	80010	6	1	5	22	0	0	0	5019	13	17	13	12	80039	0	80000	6	6	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	1	0	0	0	0	0	0	0	26	0	0	0	0	0	80027	1	6	6	0	0	25	400058	80010	240070	80000	80010	240000	80000	480049	479998	3122342	80023	80042	80042	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	26	80015	0	0	0	11	80005	6	1	5	23	0	0	0	5019	12	17	13	13	80039	1	80000	9	6	80000	240000	80010	80043	80043	80043	80043	80043

LD3R (post-index, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations