Firestorm: LD3R (post-index, 8H) measurements

Code:

  ld3r { v0.8h, v1.8h, v2.8h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.006

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
64005	29753	239	2	0	2	0	0	3	0	1	1	0	0	4	0	0	0	4716	29002	0	1	1	17425	5009	1000	3009	1000	1000	3000	1000	5000	5000	35718	10	0	0	22894	29252	29609	3	10	5000	1000	3000	2000	3003	29440	29365	1	1	61001	1000	1000	0	1000	2	0	1000	0	0	1	1000	0	1	3	0	0	0	13171	9308	6900	3111	1	36	20610	3378	3812	23	36	37	28849	1000	16242	13368	14457	1000	3000	1000	29655	29701	29736	29514	29552
64004	29539	238	0	0	0	0	0	3	0	1	1	0	0	4	0	0	0	4660	29035	0	0	1	17511	5009	1000	3009	1000	1001	3000	1000	5000	5000	35781	8	0	0	22852	29441	29590	3	10	5000	1000	3000	2000	3000	29452	29355	1	1	61001	1000	1000	0	1000	0	3	1002	1	0	3	1000	0	0	0	0	0	0	13105	9338	6892	3170	0	35	20529	3418	3804	21	37	38	28855	1000	16218	13625	14732	1000	3000	1000	29681	29617	29564	29621	29601
64004	29639	238	0	0	3	1	0	1	0	0	0	0	0	8	88	0	0	4647	29017	0	0	1	17389	5009	1000	3000	1000	1000	3000	1000	5000	5000	35787	10	0	0	22826	29422	29628	3	10	5000	1000	3000	2000	3000	29416	29479	1	1	61001	1000	1000	0	1003	0	0	1001	0	0	2	1000	3	0	0	0	0	0	13154	9456	6901	3130	1	35	20648	3346	3811	26	35	36	28812	1000	16441	13228	14509	1000	3000	1000	29575	29591	29576	29622	29485
64004	29476	238	0	0	3	2	0	0	0	0	0	1	0	1	0	0	0	4757	29058	0	0	0	17391	5009	1000	3009	1000	1000	3000	1000	5000	5000	35747	6	0	9	22791	29546	29682	3	10	5000	1000	3000	2000	3000	29487	29575	1	1	61001	1000	1000	0	1002	3	0	1000	3	0	3	1000	2	0	3	1	0	0	13304	9351	6968	3194	1	40	20602	3387	3813	25	37	35	28821	1000	16454	13332	14599	1000	3000	1000	29648	29735	29653	29563	29684
64004	29603	239	0	0	2	0	0	1	0	0	0	0	0	5	0	0	0	4629	29058	0	0	0	17461	5009	1000	3000	1000	1000	3000	1000	5000	5000	35789	5	0	0	22878	29345	29612	3	10	5000	1000	3000	2000	3000	29414	29562	1	1	61001	1000	1000	0	1003	2	0	1001	0	1	6	1000	0	0	0	1	3	0	13120	9341	6980	3186	2	40	20684	3273	3808	25	34	34	28808	1000	16643	13534	14563	1000	3000	1000	29636	29639	29633	29650	29660
64004	29549	238	0	0	2	1	0	3	0	0	0	0	1	148	0	0	0	4664	29067	0	0	0	17426	5009	1000	3006	1000	1000	3000	1000	5000	5000	35718	5	0	0	22883	29429	29610	3	10	5000	1000	3000	2000	3000	29502	29499	1	1	61001	1000	1000	0	1000	2	3	1000	0	0	3	1000	0	1	2	0	0	0	13225	9381	6958	3135	0	35	20649	3243	3816	28	31	30	28742	1000	16462	13696	14570	1000	3000	1000	29568	29717	29511	29517	29608
64004	29654	238	0	0	3	0	0	2	1	0	0	0	0	11	0	0	0	4667	29017	0	0	0	17406	5006	1000	3012	1000	1000	3000	1000	5000	5000	35643	9	0	0	22908	30227	30870	3	10	5000	1000	3000	2000	3000	29301	29387	1	1	61001	1000	1000	0	1000	0	2	1000	0	0	432	1000	2	1	2	0	2	0	13123	9463	6929	3233	0	36	20468	3270	3814	26	36	37	28662	1000	16203	13442	14545	1000	3000	1000	29339	29467	29473	29420	29309
64004	29489	236	0	1	1	0	0	1	0	1	1	0	0	1	0	0	0	4762	28814	0	0	0	17246	5009	1000	3009	1000	1000	3000	1000	5000	5000	35725	1	0	0	22828	29132	29391	3	10	5000	1000	3000	2000	3000	29271	29274	1	1	61001	1000	1000	0	1000	0	0	1000	0	0	406	1000	2	1	3	0	0	0	13200	9610	7002	3092	0	37	20435	3278	3817	20	31	37	28664	1000	16160	13364	14324	1000	3000	1000	29338	29384	29396	29434	29628
64004	29461	238	0	1	2	0	0	3	0	1	1	0	0	1	0	0	0	4656	28905	0	0	0	17295	5000	1000	3006	1000	1000	3000	1000	5000	5000	35692	4	0	0	22829	29277	29492	3	30	5000	1000	3003	2000	3000	29331	29239	1	1	61001	1000	1000	0	1000	0	3	1000	0	0	0	1000	2	1	2	0	0	0	13298	9397	6965	3180	1	40	20431	3273	3814	24	30	40	28565	1000	16306	13665	14507	1000	3000	1000	29472	29416	29523	29422	29408
64004	29618	237	0	0	1	0	0	2	0	6	0	0	0	3	0	0	0	4572	28874	0	0	0	17310	5006	1001	3006	1000	1000	3000	1000	5000	5000	35638	1	0	0	22872	29256	29475	3	10	5005	1000	3000	2000	3000	29313	29318	1	1	61001	1000	1000	0	1000	0	3	1000	0	0	0	1000	2	0	2	0	0	0	13295	9536	6982	3164	2	37	20511	3226	3814	21	34	37	28574	1000	16391	13204	14300	1000	3000	1000	29398	29486	29499	29456	29513

Count: 8

Code:

  ld3r { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld3r { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld3r { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld3r { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld3r { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld3r { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld3r { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld3r { v0.8h, v1.8h, v2.8h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320205	80069	621	0	0	0	0	0	1	61	0	0	0	80027	5	6	0	0	0	25	400148	80100	240015	80000	80100	240240	80000	480499	480006	3120178	80085	80118	80119	7	9	52	400300	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	13	80010	0	1	8	80005	6	0	10	0	0	5109	1	25	1	1	80039	0	80000	6	6	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	620	0	1	1	1	0	0	28	0	1	2	80027	5	6	10	0	0	25	400173	80140	240070	80000	80100	240000	80000	480499	480027	3122342	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80118	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	13	80013	0	0	12	80009	0	0	10	13	0	5109	1	17	1	1	80039	1	80000	6	6	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	620	0	0	0	0	0	0	35	0	0	0	80027	5	6	10	0	0	25	400170	80100	240015	80000	80100	240000	80000	480499	480023	3122342	80023	80042	80042	0	8	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80022	0	0	23	80022	5	0	9	22	0	5109	2	17	1	1	80039	0	80000	6	6	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	620	0	0	0	0	0	0	140	0	1	0	80027	5	6	10	0	0	25	400170	80100	240070	80000	80100	240000	80000	480499	480006	3120172	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	25	80009	0	0	575	80005	6	0	21	21	0	5109	1	17	1	1	80039	1	80000	0	6	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	620	0	0	0	0	0	0	26	0	1	0	80027	5	0	10	0	0	25	400170	80100	240186	80000	80100	240000	80000	480499	480035	3122342	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80118	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80021	0	1	21	80020	6	1	21	0	0	5109	1	17	1	1	80039	0	80000	6	6	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	621	0	0	0	1	0	0	16	0	1	0	80027	5	0	10	0	0	25	400121	80100	240070	80000	80100	240000	80000	480737	480027	3122342	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	4	26	80021	0	1	24	80008	0	0	22	22	0	5109	2	17	1	1	80039	1	80000	0	7	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	620	0	0	0	0	0	0	16	0	1	0	80027	5	6	10	11	0	25	400172	80100	240070	80000	80100	240000	80000	480499	480027	3120349	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	25	80022	0	0	345	80021	6	1	21	21	0	5109	1	17	1	1	80039	1	80000	0	6	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	621	0	0	0	0	0	0	16	0	1	0	80027	7	6	10	0	0	25	400364	80100	240072	80000	80100	240000	80000	480499	480002	3122342	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	26	80013	0	0	20	80007	6	0	22	22	0	5109	1	17	1	1	80102	0	80000	6	0	80000	240000	80100	80043	80115	80043	80043	80114
320204	80042	620	0	0	1	1	0	0	20	0	1	0	80095	5	6	10	0	0	25	400121	80100	240015	80000	80100	240000	80000	480499	480027	3122342	80085	80042	80042	0	3	24	400100	200	80000	240000	200	160080	240000	80042	80115	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	26	80010	0	0	20	80042	6	0	5	13	0	5109	1	17	1	1	80039	0	80000	6	6	80000	240000	80100	80043	80043	80043	80043	80043
320204	80042	621	0	0	0	0	0	0	26	0	1	0	80027	5	6	6	0	0	25	400115	80100	240015	80040	80100	240000	80000	480499	480023	3120852	80023	80042	80042	0	3	24	400100	200	80000	240000	200	160000	240000	80042	80049	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	0	80020	0	1	21	80010	0	1	20	22	0	5109	1	17	1	1	80039	0	80000	6	0	80000	240000	80100	80043	80043	80043	80043	80043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	80056	620	0	0	0	0	0	0	0	34	0	0	0	80027	0	6	6	0	0	25	400263	80010	240059	80000	80010	240000	80000	480049	480015	3121493	80023	80042	80042	0	0	3	24	400010	20	80000	240000	20	160000	240000	80118	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80013	0	0	17	80014	0	1	13	20	0	0	5019	0	7	17	7	5	80039	0	80000	0	10	0	80000	240000	80010	80043	80043	80043	80043	80119
320024	80042	620	0	0	0	1	0	0	0	34	0	0	0	80027	0	6	6	0	0	25	400069	80010	240059	80000	80010	240000	80000	480049	480015	3119994	80023	80042	80042	0	0	3	24	400210	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80016	0	0	14	80000	6	1	14	22	0	0	5019	0	4	17	7	5	80039	1	80000	13	10	0	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	621	0	0	0	0	0	0	0	34	0	0	0	80027	1	6	6	0	0	25	400069	80010	240000	80000	80010	240000	80000	480049	480015	3120050	80023	80042	80042	0	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	18	80016	0	0	18	80000	0	1	0	0	0	0	5019	0	5	17	8	5	80039	1	80000	14	10	0	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	0	0	0	0	0	0	0	35	0	0	0	80027	1	6	6	0	0	25	400069	80010	240065	80000	80010	240120	80000	480049	480021	3121469	80023	80223	80042	0	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80000	1	0	14	80013	6	1	13	20	0	0	5019	0	7	17	7	7	80039	0	80000	13	10	0	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	0	0	0	0	0	0	0	34	0	0	0	80027	1	6	6	0	0	25	400069	80010	240000	80000	80010	240000	80000	480049	479998	3119994	80023	80042	80042	0	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80016	0	0	0	80015	6	1	14	18	0	0	5019	0	5	17	7	5	80039	1	80000	13	0	0	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	0	0	0	1	0	0	0	34	0	1	0	80027	1	6	6	0	0	25	400069	80010	240051	80000	80010	240000	80000	480049	480007	3119994	80023	80042	80042	0	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80016	0	0	0	80014	6	1	0	0	0	0	5019	0	7	17	7	7	80039	1	80000	13	10	0	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	1	1	1	0	0	0	0	35	0	0	0	80027	1	6	0	0	0	25	400061	80010	240114	80000	80010	240000	80000	480049	480019	3121542	80023	80042	80042	0	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80000	0	0	17	80013	6	1	13	20	0	0	5019	0	7	17	5	7	80039	1	80000	13	0	0	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	0	0	0	0	0	0	0	34	0	0	0	80027	0	6	6	0	0	25	400069	80010	240051	80000	80010	240000	80000	480049	481632	3121493	80023	80042	80042	0	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80037	0	18	80016	0	0	0	80000	6	0	0	20	0	0	5019	0	6	17	8	8	80039	0	80040	0	10	0	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	0	0	0	0	0	0	1	6	0	1	0	80027	1	6	0	0	0	25	400069	80010	240059	80000	80010	240000	80000	480049	480015	3119994	80095	80042	80042	0	0	3	24	400210	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80016	0	0	16	80014	6	1	16	20	0	0	5019	0	5	25	5	7	80039	1	80000	13	13	0	80000	240000	80010	80043	80043	80043	80043	80043
320024	80042	620	0	0	0	0	0	0	0	166	0	0	0	80027	1	6	6	0	0	25	400010	80010	240059	80000	80010	240000	80000	480049	480015	3121493	80023	80042	80042	0	0	3	24	400010	20	80000	240000	20	160000	240000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80015	2	0	553	80000	6	1	16	0	0	0	5019	0	7	17	6	4	80039	1	80000	13	0	0	80000	240000	80010	80043	80043	80043	80043	80043

LD3R (post-index, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations