Firestorm: LD3 (multiple, 16B) measurements

Code:

  ld3 { v0.16b, v1.16b, v2.16b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.008

Integer unit issues: 0.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 3.008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	19	1e	1f	22	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
66005	28677	214	24	0	1	28	0	1	1	0	6	0	0	0	0	5054	28563	0	0	1	16022	6008	3006	3000	3000	3000	15004	35677	6	22998	28272	28431	3	10	6000	3000	3000	3000	9000	28214	28338	1	1	61001	1000	1000	1	3000	0	6	3004	0	0	4	3004	5	1	3	9	0	0	13055	10016	7115	3298	9	76	19128	3369	3816	17	63	66	27994	14588	12064	13086	3000	3000	28453	28444	28357	28257	28324
66004	28369	212	30	0	1	28	0	0	1	0	6	0	0	0	0	5033	28152	0	0	0	16375	6009	3009	3000	3000	3000	15004	35726	7	23013	28686	28306	3	10	6000	3000	3000	3000	9000	28271	28303	1	1	61001	1000	1000	0	3000	0	6	3004	0	0	1	3004	5	1	3	6	0	0	13248	9969	7115	3305	12	60	19319	3423	3812	14	56	55	27944	14695	12240	13177	3000	3000	28435	28298	28432	28411	28336
66004	28872	212	26	0	1	29	0	0	0	0	9	0	0	0	0	5055	28120	3	3	1	15942	6006	3006	3000	3000	3000	15004	35757	6	23081	28245	28312	3	10	6000	3000	3000	3000	9000	28360	28384	1	1	61001	1000	1000	0	3000	0	6	3001	0	0	1	3001	3	1	3	9	0	0	13685	10054	7040	3370	13	67	19229	3280	3821	9	64	60	27874	14232	11879	13457	3000	3000	28843	28381	28487	28455	28451
66004	28389	214	28	0	0	30	0	0	0	0	9	0	1	0	0	5104	28040	0	3	0	16401	6006	3009	3000	3000	3000	15000	35711	1	23077	28341	28360	3	10	6000	3000	3000	3000	9000	28161	28209	1	1	61001	1000	1000	0	3000	0	6	3004	0	0	4	3004	5	1	1	9	0	0	13977	10061	7238	3313	11	58	19118	3347	3817	19	57	60	27882	14722	11898	13160	3000	3000	28314	28769	28360	28438	28351
66004	28247	212	24	0	0	24	0	1	0	0	9	0	0	0	0	5004	28190	0	0	0	16019	6006	3009	3000	3000	3000	15000	35745	6	23021	28262	28414	3	10	6000	3000	3000	3000	9000	28212	28631	1	1	61001	1000	1000	1	3000	0	6	3001	0	1	1	3004	5	1	3	6	0	0	13606	10045	7100	3377	9	54	19148	3329	3808	13	61	58	27966	15712	11879	13301	3000	3000	28305	28392	28442	28278	28310
66004	28418	211	24	0	0	29	0	0	0	0	6	0	1	0	0	4995	28188	0	0	3	16423	6006	3006	3000	3000	3000	15000	35764	8	23019	28411	28464	3	10	6000	3000	3000	3000	9000	28267	28358	1	1	61001	1000	1000	0	3000	0	6	3001	0	0	1	3004	5	1	4	9	0	0	13691	10038	7109	3385	12	54	19210	3355	3817	17	61	67	27924	14629	11910	13267	3000	3000	28438	28321	28369	28384	28325
66004	28788	212	27	0	0	27	0	0	0	0	6	0	0	0	0	4638	28102	0	0	1	15855	6006	3009	3000	3000	3000	15004	35688	1	23010	28690	28460	3	10	6000	3000	3000	3000	9000	28618	28465	1	1	61001	1000	1000	0	3000	0	6	3004	0	0	1	3001	5	1	6	6	0	0	12963	9954	7168	3288	13	58	19614	3408	3812	15	50	56	27877	14785	12700	13130	3000	3000	28447	28801	28464	28229	28684
66004	28765	213	24	0	0	27	0	0	0	0	9	0	0	0	0	4990	28213	0	3	3	15902	6008	3006	3000	3000	3000	15000	35755	1	23019	28191	28742	3	10	6000	3000	3000	3000	9000	28282	28373	1	1	61001	1000	1000	0	3000	0	6	3004	0	0	4	3001	5	0	1	6	0	0	13862	10083	6946	3366	14	60	19167	3400	3818	8	57	59	27949	14471	12004	12994	3000	3000	28350	28279	28397	28741	28468
66004	28412	215	23	0	0	25	0	0	1	0	9	0	0	0	0	4797	28172	0	3	0	15932	6009	3006	3000	3000	3000	15004	35731	3	22984	28276	28376	3	10	6000	3000	3000	3000	9000	28275	28192	1	1	61001	1000	1000	0	3000	0	6	3004	0	0	1	3001	5	1	3	6	0	0	13623	10080	6841	3305	11	65	19167	3314	3817	15	59	57	27985	15732	11899	13291	3000	3000	28335	28350	28330	28245	28411
66004	28440	213	30	0	0	30	0	1	1	0	9	0	0	0	0	5111	27970	0	0	1	16123	6006	3006	3000	3000	3000	15000	35694	6	23058	28187	28351	3	10	6000	3000	3000	3000	9000	28170	28190	1	1	61001	1000	1000	0	3000	0	6	3001	0	0	1	3001	5	1	3	6	0	0	13858	9938	7139	3407	9	55	19105	3391	3820	15	52	62	27955	14755	12532	13378	3000	3000	28426	28475	28420	28708	28830

Count: 8

Code:

  ld3 { v0.16b, v1.16b, v2.16b }, [x6]
  ld3 { v0.16b, v1.16b, v2.16b }, [x6]
  ld3 { v0.16b, v1.16b, v2.16b }, [x6]
  ld3 { v0.16b, v1.16b, v2.16b }, [x6]
  ld3 { v0.16b, v1.16b, v2.16b }, [x6]
  ld3 { v0.16b, v1.16b, v2.16b }, [x6]
  ld3 { v0.16b, v1.16b, v2.16b }, [x6]
  ld3 { v0.16b, v1.16b, v2.16b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	24	37	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480205	80050	599	1	0	0	0	0	0	0	0	0	1	0	0	1	1	80042	0	0	15	0	25	480101	100	240011	240000	100	240000	240000	500	3533849	4862939	0	80040	0	80080	80067	14	0	3	49	480100	200	240000	240000	200	240000	720000	80067	80049	1	1	80201	100	99	0	100	100	80000	80000	0	100	240018	21	42	0	240057	1	3	1	59	240039	0	1	37	38	0	0	5109	1	17	1	1	80041	0	6	0	240000	240000	100	80058	80063	80067	80067	80045
480204	80062	599	1	1	1	0	0	0	0	0	64	0	0	0	0	0	80051	3	18	18	14	25	480136	100	240039	240000	100	240000	240000	500	3515364	5532975	1	80025	0	80044	80062	10	0	3	44	480100	200	240000	240000	200	240000	720000	80058	80058	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	39	0	240042	0	0	0	3	240039	5	1	17	42	17	1	5109	1	17	1	1	80047	9	0	0	240000	240000	100	80050	80068	80068	80050	80068
480204	80067	599	1	0	0	0	0	0	0	0	42	1	0	0	2	0	80064	0	0	18	0	25	480138	102	240014	240000	100	240000	240000	500	3545551	4862421	1	80048	0	80067	80067	0	0	3	32	480100	200	240000	240000	200	240000	720000	80067	80067	1	1	80201	100	99	0	100	100	80000	80000	0	100	240018	17	0	0	240056	0	0	0	60	240039	5	1	37	45	0	0	5109	1	17	1	1	80059	10	0	0	240000	240000	100	80063	80045	80063	80063	80046
480205	80062	601	1	1	1	0	0	0	0	0	64	1	0	0	2	4	80057	3	18	18	0	25	480118	100	240030	240130	100	240000	240000	500	3542979	5556030	0	80043	0	80044	80062	10	0	3	44	480100	200	240000	240000	200	240000	720000	80062	80057	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	39	0	240000	0	0	0	0	240040	5	0	56	0	17	1	5109	1	17	1	1	80064	9	9	0	240000	240000	100	80068	80068	80068	80050	80068
480204	80067	600	1	0	0	0	0	0	0	0	0	0	0	0	0	2	80047	3	15	0	0	25	480149	100	240039	240000	100	240000	240000	500	3542979	3601919	1	80043	0	80062	80062	10	0	3	44	480100	200	240000	240000	200	240000	720000	80062	80044	1	1	80201	100	99	1	100	100	80000	80000	0	100	240000	0	38	0	240042	0	0	0	41	240040	5	1	56	42	17	0	5109	1	17	1	1	80047	9	0	0	240000	240000	100	80067	80068	80068	80068	80068
480204	80049	599	1	0	0	0	1	0	4	0	47	1	0	0	0	0	80047	3	19	15	10	25	480107	100	240009	240000	100	240000	240000	500	3538807	5724897	1	80025	0	80056	80062	10	0	3	30	481553	200	240000	240000	200	240000	720000	80044	80057	1	1	80201	100	99	1	100	100	80000	80000	1	100	240000	0	39	0	240042	0	0	0	0	240038	5	0	37	45	0	0	5109	1	17	1	1	80059	10	10	0	240000	240000	100	80063	80063	80045	80063	80063
480204	80044	600	1	0	0	0	0	0	0	0	50	1	0	0	0	1	80050	3	15	0	10	25	480137	100	240042	240000	100	240000	240000	500	3505352	4863729	1	80048	0	80067	80067	15	0	3	49	480100	200	240000	240756	200	240000	720000	80067	80067	1	1	80201	100	99	0	100	100	80000	80000	0	100	240019	17	42	0	240017	1	0	1	60	240039	5	1	37	0	0	0	5109	1	17	1	1	80041	0	6	0	240000	240000	100	80045	80063	80063	80063	80045
480204	80062	600	1	0	0	0	0	0	0	0	47	0	0	0	0	2	80047	3	15	18	0	25	480142	100	240042	240000	100	240000	240000	500	3505352	4863698	1	80048	0	80067	80067	0	0	3	32	480100	200	240000	240000	200	240000	720000	80067	80050	1	1	80201	100	99	0	100	100	80000	80000	0	100	240018	18	42	65	240057	1	0	2	59	240039	5	0	36	45	0	0	5109	1	17	1	1	80041	0	10	0	240000	240000	100	80045	80058	80058	80064	80063
480204	80052	599	1	1	0	1	0	0	0	0	65	1	0	0	0	3	81979	3	15	0	14	157	480147	100	240005	240000	100	240000	240000	500	3495893	5698290	0	80031	0	80067	80066	0	0	3	49	480100	200	240000	240000	200	240000	720000	80050	80067	1	1	80201	100	99	0	100	100	80000	80000	0	100	240537	18	0	0	240017	1	0	1	20	240040	0	1	36	0	0	0	5163	1	17	1	1	80059	6	0	0	240000	240000	100	80073	80045	80063	80058	80063
480204	80062	599	1	0	1	1	1	1	0	0	64	0	0	0	0	2	80055	0	18	18	14	25	480139	100	240039	240000	100	240000	240000	500	3542979	5535097	0	80025	0	80062	80062	0	0	3	44	480100	200	240000	240000	200	240000	720000	80057	80057	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	39	0	240043	0	0	0	42	240039	5	1	37	45	0	0	5109	1	17	1	1	80059	0	10	0	240000	240000	100	80063	80045	80057	80063	80045

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	09	l2 tlb miss data (0b)	0e	0f	19	1e	22	24	37	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480025	80131	601	0	0	0	0	0	0	47	1	0	2	1	80047	2	15	15	0	25	480054	10	240005	240000	10	240558	240000	50	3525157	5743380	1	80043	80062	80066	10	3	44	480374	20	240000	240000	20	240000	720000	80062	80062	1	1	80021	10	9	1	10	10	80000	80000	0	10	240000	0	0	240042	0	278	240042	5	1	42	45	5019	5	17	4	4	80059	10	10	0	240000	240000	10	80065	80071	80082	80063	80063
480024	80145	600	0	0	0	0	1	0	47	0	0	1	1	80029	2	15	15	0	25	480052	10	240042	240000	10	240000	240000	50	1676441	5532980	1	80047	80044	80062	14	3	44	480010	20	240000	240000	20	240000	720000	80062	80062	1	1	80021	10	9	1	10	10	80000	80000	0	10	240000	45	0	240000	0	297	240041	5	0	0	45	5019	4	17	3	4	80059	10	10	0	240000	240000	10	80063	80067	80063	80067	80063
480024	80343	601	1	0	0	0	0	0	47	1	0	2	1	80047	2	4	15	10	25	480055	10	240044	240000	10	240000	240000	50	2645118	3603705	1	80043	80062	80062	10	3	44	480010	20	240000	240000	20	240000	720000	80062	80062	1	1	80021	10	9	1	10	10	80000	80000	0	10	240000	0	0	240042	0	258	240042	6	0	42	45	5019	4	17	3	4	80059	14	0	0	240000	240000	10	80063	80063	80063	80045	80067
480024	80355	600	0	0	0	0	0	0	47	0	0	3	1	80029	0	15	15	10	25	480055	10	240047	240000	10	240000	240000	50	2853226	5747985	1	80025	80044	80062	0	3	44	480010	20	240000	240000	20	240000	720000	80062	80062	1	1	80021	10	9	1	10	10	80000	80000	0	10	240000	45	0	240042	1	51	240042	5	1	42	0	5019	4	17	4	4	80041	0	10	0	240000	240000	10	80045	80063	80049	80085	80045
480024	80320	600	0	0	0	1	1	0	47	0	0	0	1	80029	0	4	15	10	25	480055	10	240042	240000	10	240000	240000	50	1676441	3595923	1	80043	80062	80062	0	3	44	480010	20	240000	240000	20	240000	720000	80044	80062	1	1	80021	10	9	1	10	10	80000	80000	0	10	240000	45	0	240041	0	288	240042	5	1	0	45	5019	4	17	3	4	80041	0	10	0	240000	240000	10	80063	80063	80063	80063	80063
480024	80342	601	0	0	0	0	0	0	47	1	0	2	1	80047	0	15	0	10	25	480055	10	240042	240000	10	240000	240712	50	3508586	5691649	1	80043	80044	80062	10	3	26	480010	20	240000	240000	20	240189	720000	80062	80062	1	1	80021	10	9	5	10	10	80000	80000	0	10	240000	45	0	240042	0	270	240042	0	0	43	45	5019	4	17	4	3	80059	14	0	0	240000	240000	10	80045	80063	80063	80063	80063
480024	80200	600	0	0	0	0	0	0	0	1	0	2	1	80047	2	0	15	10	25	480052	10	240006	240000	10	240000	240000	50	3515062	3603246	0	80043	80062	80062	10	3	26	480010	20	240000	240000	20	240000	720000	80062	80062	1	1	80021	10	9	1	10	10	80000	80000	0	10	240000	45	0	240131	1	243	240043	5	1	42	0	5019	4	17	4	4	80059	10	10	0	240000	240000	10	81780	81499	80070	80063	80063
480024	80363	601	0	0	0	0	0	0	0	1	0	0	1	80047	2	15	15	0	25	480056	10	240043	240000	10	240000	240000	50	1676441	5532975	1	80025	80062	80062	10	3	44	480010	20	240000	240000	20	240000	720000	80062	80062	1	1	80021	10	9	1	10	10	80000	80000	0	10	240000	45	0	240000	0	258	240042	5	0	42	45	5019	4	17	4	3	80059	14	10	0	240000	240000	10	80063	80045	80045	80351	80067
480024	80120	600	0	0	0	0	0	0	71	0	0	6	0	80029	2	0	15	10	25	480277	10	240172	240000	10	240000	240178	50	3525157	5739198	1	80043	80065	80044	12	3	48	480010	20	240000	240000	20	240000	720000	80213	80077	1	1	80021	10	9	1	10	10	80000	80000	1	10	240000	45	0	240174	1	45	240041	5	1	41	45	5019	4	17	4	4	80074	10	10	3	240000	240000	10	80045	80063	80045	80063	80063
480024	80214	600	0	0	0	1	1	0	47	0	0	1	1	80231	2	15	15	0	25	480052	10	240043	240000	10	240000	240000	50	3556201	5519827	1	80043	80044	80383	0	3	44	480010	20	240000	240177	20	240000	720639	80049	80062	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	45	0	240042	5	160	240000	5	0	42	45	5019	4	17	4	3	80059	0	10	0	240000	240000	10	80063	80045	80063	80067	80063

LD3 (multiple, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations