Firestorm: LD3 (multiple, 2D) measurements

Code:

  ld3 { v0.2d, v1.2d, v2.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.006

Integer unit issues: 0.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 3.006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
66005	29194	219	1	0	1	0	0	0	0	1	6	1	4593	28738	0	0	16841	6006	3006	3000	3000	3000	15000	35721	13	23034	29102	29200	3	10	6000	3000	3000	3000	9000	29101	29112	1	1	61001	1000	1000	0	3000	0	3	3000	0	0	0	3004	5	1	4	9	0	0	12884	9127	6856	3065	52	20038	3034	3806	11	35	43	28408	15993	13220	14933	3000	3000	29300	29220	29218	29230	29241
66004	29252	218	0	0	0	0	0	0	0	0	6	1	4529	28792	1	0	16796	6009	3009	3000	3000	3000	15000	35714	5	23022	29069	29258	3	10	6000	3000	3000	3000	9000	29164	29204	1	1	61001	1000	1000	0	3000	0	6	3000	0	0	1	3001	5	0	0	6	0	0	12923	9238	6845	3042	33	20028	3083	3810	5	40	46	28379	16232	13168	14941	3000	3000	29250	29234	29284	29340	29184
66004	29238	220	0	0	0	0	0	0	0	0	0	1	4553	28704	0	0	16802	6009	3003	3000	3000	3000	15000	35766	5	23016	29115	29177	3	10	6000	3000	3000	3000	9000	29111	29174	1	1	61001	1000	1000	0	3000	0	6	3001	0	0	0	3004	5	1	1	6	0	0	12927	9158	6924	3077	37	20065	3048	3812	11	38	44	28305	16375	13075	14905	3000	3000	29276	29246	29272	29274	29253
66004	29215	219	0	0	0	0	0	0	0	0	0	0	4526	28785	0	0	16950	6000	3000	3000	3000	3000	15000	35749	0	23031	29157	29204	3	10	6000	3000	3000	3000	9000	29181	29128	1	1	61001	1000	1000	0	3000	0	0	3000	0	0	7	3000	5	1	4	9	0	0	12764	9144	6817	3073	33	20040	3114	3811	7	39	33	28415	16449	13353	15014	3000	3000	29178	29251	29255	29263	29279
66004	29218	218	0	0	0	0	0	0	0	0	6	0	4507	28819	0	0	16901	6000	3009	3000	3000	3000	15000	35785	6	23022	29138	29214	3	10	6000	3000	3000	3000	9000	29181	29122	1	1	61001	1000	1000	0	3005	5	6	3011	0	2	5	3003	3	1	4	6	0	0	12766	9242	6824	3096	37	20077	3026	3813	12	35	32	28419	16329	13259	15019	3000	3000	29167	29270	29245	29248	28848
66004	29245	218	0	0	0	0	0	0	0	0	9	0	4600	28793	0	0	16920	6006	3006	3000	3000	3000	15000	35781	5	22995	29050	29233	3	10	6000	3000	3000	3000	9000	29174	28992	1	1	61001	1000	1000	0	3000	0	0	3001	0	0	7	3001	5	1	1	6	0	0	12713	8994	6916	3044	35	20087	3073	3818	9	33	30	28454	16158	13176	14964	3000	3000	29233	29290	29223	29258	29339
66004	29221	219	0	0	0	0	0	0	0	0	0	1	4500	28879	3	0	16913	6009	3000	3000	3000	3000	15000	35739	4	22981	29171	29256	3	10	6000	3000	3000	3000	9000	29167	29078	1	1	61001	1000	1000	0	3000	0	6	3001	0	0	4	3001	5	1	1	9	0	0	12736	9133	6812	3083	36	19976	3084	3810	10	38	32	28364	16566	13530	15095	3000	3000	29294	29334	29126	29300	29243
66004	29286	219	0	0	0	0	0	0	0	0	6	1	4664	28837	0	0	16862	6006	3000	3000	3000	3000	15000	35728	0	23007	29102	29207	3	10	6000	3000	3000	3000	9000	29195	29156	1	1	61001	1000	1000	0	3000	0	9	3004	0	0	1	3004	5	1	0	9	0	0	12879	9089	6890	3061	37	20053	3088	3817	4	37	30	28365	16461	13276	14917	3000	3000	29286	29323	29253	29285	29193
66004	29313	220	0	0	0	0	0	1	0	0	9	1	4469	28759	0	0	16931	6006	3000	3000	3000	3000	15000	35760	3	23026	29183	29269	3	10	6000	3000	3000	3000	9000	29212	29140	1	1	61001	1000	1000	0	3000	0	6	3001	0	0	1	3001	0	0	1	6	0	0	12891	9133	6935	3097	33	20067	3053	3817	7	36	29	28358	16436	13374	14910	3000	3000	29258	29305	29263	29350	29267
66004	29229	218	0	0	0	0	0	0	0	0	0	1	4668	28838	0	0	16870	6000	3006	3000	3000	3000	15000	35832	3	22969	29168	29313	3	10	6000	3000	3000	3000	9000	29169	29077	1	1	61001	1000	1000	1	3000	0	0	3001	1	0	4	3001	5	1	0	6	0	0	12868	9132	6879	3059	35	20053	3044	3814	11	32	36	28396	16452	13278	14854	3000	3000	29227	28803	29311	29287	28986

Count: 8

Code:

  ld3 { v0.2d, v1.2d, v2.2d }, [x6]
  ld3 { v0.2d, v1.2d, v2.2d }, [x6]
  ld3 { v0.2d, v1.2d, v2.2d }, [x6]
  ld3 { v0.2d, v1.2d, v2.2d }, [x6]
  ld3 { v0.2d, v1.2d, v2.2d }, [x6]
  ld3 { v0.2d, v1.2d, v2.2d }, [x6]
  ld3 { v0.2d, v1.2d, v2.2d }, [x6]
  ld3 { v0.2d, v1.2d, v2.2d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	1f	22	23	37	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480205	80098	600	0	0	0	0	1	1	42	0	1	0	0	2	80047	0	0	19	5	25	480136	100	240008	240000	100	240024	240020	500	3501557	4908111	0	80041	80057	80057	4	0	7	28	480145	200	240024	240024	200	240024	720072	80062	80057	1	1	80201	100	99	0	100	100	80000	80000	0	100	240017	18	42	240056	0	0	1	60	240040	5	1	56	0	17	2	1	1	1	5117	0	16	0	0	80063	9	9	0	240000	240000	100	80068	80067	80068	80050	80068
480204	80050	600	1	1	0	0	0	0	42	0	0	0	9	1	80030	3	19	0	5	25	480134	100	240045	240000	100	240024	240022	500	3501859	5763388	1	80025	80057	80057	0	0	7	27	480147	200	240024	240024	200	240024	720072	80057	80057	1	1	80201	100	99	0	100	100	80000	80000	0	100	240001	0	39	240037	0	1	0	37	240037	5	0	37	39	0	0	1	1	1	5117	0	16	0	0	80059	6	6	0	240000	240000	100	80058	80045	80063	80046	80063
480204	80062	600	0	0	0	0	0	0	0	0	0	0	0	1	80030	3	15	19	0	25	480137	100	240035	240000	100	240024	240024	500	3519847	5738076	1	80025	80044	80057	4	0	6	33	480145	200	240024	240024	200	240024	720072	80062	80057	1	1	80201	100	99	1	100	100	80000	80000	0	100	240000	0	39	240042	0	0	0	37	240042	5	1	0	0	0	0	1	1	1	5116	0	17	0	0	80054	10	6	0	240000	240000	100	80058	80058	80058	80058	80058
480204	80057	600	0	0	0	0	0	0	0	0	0	0	6	1	80047	3	0	15	5	25	480136	100	240007	240000	100	240024	240022	500	3522640	5667752	0	80038	80056	80045	10	0	6	33	480147	200	240024	240024	200	240024	720072	80056	80053	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	39	240037	0	0	0	0	240042	0	1	37	39	0	0	1	1	1	5117	0	16	0	0	80054	0	0	0	240000	240000	100	80065	80045	80045	80047	80045
480204	80044	602	1	0	1	1	1	1	64	0	0	0	9	3	80225	3	15	15	5	25	480142	100	240043	240000	100	240000	240000	500	3253166	5593431	1	80037	80062	80044	5	0	3	44	480100	200	240000	240000	200	240000	720000	80062	80044	1	1	80201	100	99	1	100	100	80000	80000	0	100	240000	0	38	240042	0	1	0	42	240042	0	1	37	0	0	0	0	0	0	5109	1	17	1	1	80054	6	6	0	240000	240000	100	80063	80063	80057	80058	80058
480204	80062	600	0	0	0	0	0	0	99	0	1	0	1	0	80029	0	0	15	10	25	480106	100	240038	240000	100	240201	240000	500	3508328	5654906	0	80043	80057	80057	10	0	3	44	480100	200	240000	240000	200	240000	720000	80056	80057	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	38	240037	0	0	0	0	240040	0	1	37	0	0	0	0	0	0	5109	1	17	1	1	80041	10	0	0	240000	240000	100	80045	80063	80250	80065	80066
480204	80377	600	1	1	1	1	0	0	65	0	1	0	1	2	80029	3	0	19	0	25	480102	100	240039	240000	100	240000	240000	500	3553577	4346729	1	80038	80056	80059	10	0	3	44	480100	200	240000	240000	200	240000	720000	80057	80057	1	1	80201	100	99	1	100	100	80000	80000	0	100	240000	0	39	240037	0	0	0	62	240038	5	1	56	42	17	2	0	0	0	5109	1	17	1	1	80067	9	9	0	240000	240000	100	80068	80068	80050	80068	80068
480204	80079	600	1	0	0	1	0	0	45	0	1	0	0	0	80029	0	15	0	10	25	480142	100	240037	240000	100	240000	240000	500	3524329	5534190	0	80043	80044	80044	0	0	3	44	480100	200	240000	240000	200	240000	720000	80056	80057	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	39	240000	0	0	0	48	240000	5	0	42	38	0	0	0	0	0	5109	1	17	1	1	80041	0	10	0	240000	240000	100	80045	80058	80057	80058	80063
480204	80069	600	0	0	0	0	1	0	42	0	1	0	2	0	80042	0	15	0	5	25	480106	100	240040	240000	100	240000	240000	500	3524458	5762629	1	80043	80062	80062	0	0	3	26	480100	200	240000	240000	200	240000	720000	80057	80057	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	0	240037	0	0	0	61	240037	5	1	41	45	0	0	0	0	0	5109	1	17	1	1	80054	10	0	0	240000	240000	100	80045	80045	80058	80045	80058
480204	80713	599	0	0	0	0	0	0	42	0	1	0	7	1	80042	3	15	0	5	25	480143	100	240034	240000	100	240000	240000	500	3494949	5871396	0	80043	80044	80057	5	0	3	26	480100	200	240000	240000	200	240000	720000	80044	80056	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	0	240000	0	0	0	40	240042	5	1	0	45	0	0	0	0	0	5109	1	17	1	1	80059	6	10	0	240000	240000	100	80063	80058	80058	80063	80102

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	0e	0f	18	1e	1f	22	24	37	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480025	80062	599	0	1	0	0	0	42	0	1	0	4	2	80042	0	15	19	4	25	480043	10	240010	240000	10	240000	240000	50	3524458	5762629	1	80038	0	80057	80057	4	0	3	38	480010	20	240000	240000	20	240000	720000	80057	80057	1	1	80021	10	9	0	10	10	80000	80000	1	10	240000	39	0	240037	0	37	240042	5	1	0	39	0	5019	11	17	12	13	80054	10	6	240000	240000	10	80073	80068	80045	80045	80063
480024	80057	599	0	0	0	1	0	42	0	0	0	0	0	80047	3	19	0	10	25	480315	10	240034	240000	10	240000	240000	50	1676441	5542341	0	80025	0	80062	80062	0	0	3	49	480010	20	240000	240000	20	240000	720000	80062	80060	1	1	80021	10	9	1	10	10	80000	80000	1	10	240000	39	0	240037	0	42	240000	0	1	37	0	0	5019	12	17	10	11	80059	0	6	240000	240000	10	80070	80063	80063	80045	80063
480024	80047	599	0	0	0	1	0	42	0	0	0	1	1	80029	0	19	15	0	25	480017	10	240036	240000	10	240000	240000	50	3494065	5532975	1	80043	0	80062	80062	10	0	3	44	480010	20	240000	240000	20	240000	720000	80044	80056	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	39	0	240036	0	42	240042	5	1	37	45	0	5019	12	17	10	6	80054	10	6	240000	240000	10	80080	80058	80057	80063	80059
480024	80057	599	0	0	0	0	0	42	0	1	0	5	1	80029	3	19	19	0	25	480018	10	240043	240000	10	240000	240000	50	3553577	5534190	1	80043	0	80062	80062	0	0	3	44	480010	20	240000	240000	20	240000	720000	80062	80044	1	1	80021	10	9	0	10	10	80000	80000	1	10	240000	38	0	240037	1	42	240000	5	1	37	39	0	5019	11	17	7	12	80054	0	6	240000	240000	10	80070	80073	80058	80060	80045
480024	80062	599	0	0	0	0	0	42	0	1	0	8	2	80047	3	19	19	5	25	480054	10	240042	240000	10	240000	240000	50	3494949	3603255	1	80043	0	80044	80057	4	0	3	44	480010	20	240000	240000	20	240000	720000	80062	80057	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	0	240042	0	37	240036	0	1	0	45	0	5019	10	17	7	12	80059	6	6	240000	240000	10	80392	80181	80072	80063	80045
480024	80062	599	0	0	0	0	0	47	132	1	0	2	2	80029	3	19	19	10	25	480049	10	240004	240000	10	240000	240000	50	3529181	3603250	1	80038	0	80062	80057	4	0	3	39	480010	20	240000	240000	20	240000	720000	80044	80057	1	1	80021	10	9	1	10	10	80000	80000	0	10	240000	38	0	240037	0	42	240042	5	1	42	39	0	5019	11	17	7	10	80059	0	6	240000	240000	10	80059	80045	80058	80058	80063
480024	80057	600	0	0	0	0	0	42	0	0	0	1	0	80029	3	15	18	0	25	480047	10	240042	240000	10	240000	240000	50	3553577	5586488	1	80025	0	80062	80057	4	0	3	44	480010	20	240000	240000	20	240000	720000	80044	80057	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	39	0	240037	0	37	240037	5	1	37	45	0	5019	7	17	10	10	80059	10	0	240000	240000	10	80057	80063	80063	80058	80045
480024	80057	599	0	0	0	0	0	0	0	0	0	2	2	80047	3	15	15	10	25	480016	10	240033	240000	10	240000	240000	50	1676441	5577915	1	80025	0	80064	80048	0	0	3	39	480010	20	240000	240000	20	240000	720639	80280	80044	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	39	0	240000	0	0	240037	5	1	36	45	0	5019	11	17	11	14	80054	10	0	240000	240000	10	80063	80057	80058	80058	80045
480024	80058	599	0	0	0	0	0	42	0	0	0	0	0	80047	0	19	19	10	25	480047	10	240001	240000	10	240000	240000	50	3524329	5556045	0	80043	0	80044	80062	0	0	3	39	480010	20	240000	240000	20	240000	720000	80062	80057	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	39	0	240036	0	41	240042	5	1	42	0	0	5019	13	17	12	7	80054	10	0	240000	240000	10	80167	80065	80045	80063	80045
480024	80056	600	0	0	0	1	0	0	0	0	0	0	1	80029	3	19	15	0	25	480052	10	240040	240000	10	240000	240000	50	1676441	3603287	1	80043	0	80057	80057	4	0	3	39	480010	20	240000	240000	20	240000	720000	80044	80057	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	0	240042	0	0	240042	5	0	42	0	0	5019	12	17	11	13	80059	6	6	240000	240000	10	80062	80146	80215	80071	80045

LD3 (multiple, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations