Firestorm: LD3 (multiple, 2S) measurements

Code:

  ld3 { v0.2s, v1.2s, v2.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.009

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 3.009

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	0e	0f	1e	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	df	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
65005	29329	220	11	4	0	0	1	0	8	1	0	4543	28796	0	0	2	16990	5009	3012	2000	3000	2000	10000	35733	6	22921	0	29041	29247	3	10	5000	2000	3000	2000	6000	29142	29129	1	1	61001	1000	1000	0	2000	6	2002	0	0	4	2004	4	0	6	13326	9069	6874	3094	3	84	20213	3195	3809	16	62	57	10	28336	16396	13272	15024	2000	3000	29385	29327	29405	29398	29220
65004	29267	220	3	1	0	0	0	0	6	0	0	4568	28849	0	2	2	16987	5012	3009	2000	3000	2000	10003	35746	3	22892	0	29105	29375	3	10	5000	2000	3000	2000	6000	29163	29066	1	1	61001	1000	1000	0	2000	6	2000	0	0	2	2000	4	2	4	12873	9128	6853	3072	2	62	20188	3058	3808	15	59	61	10	28408	16315	13329	14986	2000	3000	29277	29376	29302	29360	29379
65004	29236	220	4	0	0	0	0	0	6	0	0	4556	28874	0	2	2	17033	5009	3006	2000	3000	2000	10000	35796	3	22954	0	29050	29358	3	10	5000	2000	3000	2000	6000	29217	29111	1	1	61001	1000	1000	0	2000	6	2000	0	0	2	2002	4	2	6	12968	9240	6820	3080	3	63	20269	3131	3815	13	52	53	11	28419	16597	13337	15025	2000	3000	29282	29291	29418	29253	29407
65004	29286	220	3	0	0	0	0	0	3	1	0	4597	28815	0	2	0	17106	5006	3012	2000	3000	2000	10000	35770	8	22897	0	29163	29394	3	10	5000	2000	3000	2000	6000	29262	29197	1	1	61001	1000	1000	0	2000	6	2000	0	0	2	2004	4	0	4	12800	9041	6902	3131	0	64	20237	3031	3823	23	67	66	9	28405	16395	13444	15220	2000	3000	29285	29318	29310	29374	29305
65004	29240	219	8	1	0	0	0	0	8	0	0	4576	28837	0	0	2	16944	5006	3009	2000	3000	2000	10000	35750	9	22906	0	29075	29316	3	10	5000	2000	3000	2000	6000	29135	29100	1	1	61001	1000	1000	0	2000	6	2002	0	0	0	2002	4	2	6	12828	9104	6913	3063	0	63	20158	3115	3817	19	68	66	12	28412	16325	13255	14961	2000	3000	29304	29303	29365	29363	29458
65004	29304	219	7	0	0	0	0	0	6	1	0	4466	28795	0	2	2	17077	5009	3012	2000	3000	2000	10000	35773	3	22927	0	29106	29257	3	10	5000	2000	3000	2000	6000	29191	29172	1	1	61001	1000	1000	0	2000	6	2004	0	0	2	2002	4	2	4	12858	9112	6928	3067	0	76	20161	3121	3815	20	63	56	10	28456	16278	13352	14941	2000	3000	29298	29238	29262	29245	29334
65004	29347	219	5	0	0	0	0	0	8	1	0	4577	28828	0	0	0	16920	5009	3006	2000	3000	2000	10003	35749	3	22900	0	29089	29363	3	10	5000	2000	3000	2000	6000	29182	29185	1	1	61001	1000	1000	0	2000	4	2004	0	0	2	2000	4	2	6	13007	9047	6955	3091	1	67	20243	3100	3811	18	65	67	10	28464	15996	13212	14948	2000	3000	29174	29279	29341	29357	29340
65004	29280	219	6	0	0	0	0	0	8	0	0	4599	28813	0	0	1	17004	5009	3012	2000	3000	2000	10000	35783	5	22872	0	29134	29324	3	10	5000	2000	3000	2000	6000	29111	29167	1	1	61001	1000	1000	0	2000	6	2000	0	0	0	2004	4	2	6	12771	9045	6895	3123	1	62	20176	3115	3814	19	70	70	12	28365	16239	13254	14926	2000	3000	29239	29192	29275	29226	29345
65004	29309	220	5	0	0	0	0	0	4	0	0	4606	28797	0	1	0	16961	5012	3009	2000	3000	2000	10000	35766	5	22901	0	29122	29168	3	10	5000	2000	3000	2000	6000	29135	29158	1	1	61001	1000	1000	0	2000	6	2002	0	0	2	2002	4	0	6	12856	9162	6858	3086	3	65	20277	3085	3812	12	60	62	11	28479	16411	13371	15023	2000	3000	29363	29337	29440	29166	29229
65004	29363	220	5	0	0	0	0	0	8	1	0	4544	28788	0	2	0	17063	5006	3009	2000	3000	2000	10000	35779	2	22906	0	29074	29253	3	10	5000	2000	3000	2000	6000	29128	29226	1	1	61001	1000	1000	0	2000	4	2000	0	0	4	2002	4	2	6	13079	9287	6937	3168	4	61	20203	3080	3817	17	71	66	10	28454	16494	13252	15240	2000	3000	29336	29359	29315	29301	29296

Count: 8

Code:

  ld3 { v0.2s, v1.2s, v2.2s }, [x6]
  ld3 { v0.2s, v1.2s, v2.2s }, [x6]
  ld3 { v0.2s, v1.2s, v2.2s }, [x6]
  ld3 { v0.2s, v1.2s, v2.2s }, [x6]
  ld3 { v0.2s, v1.2s, v2.2s }, [x6]
  ld3 { v0.2s, v1.2s, v2.2s }, [x6]
  ld3 { v0.2s, v1.2s, v2.2s }, [x6]
  ld3 { v0.2s, v1.2s, v2.2s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	80069	600	0	1	0	1	1	0	38	0	1	0	0	80026	2	12	0	0	25	400157	100	240000	160000	100	240000	160000	500	800377	2881982	1	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	160000	0	0	0	160000	6	1	32	35	0	5109	1	17	1	1	80038	1	0	10	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	600	0	0	0	0	0	0	38	0	1	0	0	80026	2	12	12	0	25	400158	100	240058	160000	100	240000	160000	500	800377	2881975	0	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	160032	0	0	35	160032	6	1	0	35	0	5109	1	17	1	1	80038	1	10	10	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	600	0	0	0	0	0	0	38	0	1	0	0	80026	0	12	12	0	25	400157	100	240057	160000	100	240000	160000	500	800374	2882019	1	80022	80128	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	160032	0	0	0	160032	0	0	0	35	0	5109	1	17	1	1	80038	1	10	10	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	599	0	0	0	0	0	0	38	0	1	0	0	80026	2	12	12	0	25	400157	100	240111	160152	100	240000	160000	500	800374	2881968	1	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	160032	0	0	32	160000	6	1	32	35	0	5109	1	17	1	1	80038	1	0	10	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	600	0	0	0	0	0	0	38	0	1	0	0	80026	2	12	12	0	25	400158	100	240058	160000	100	240000	160000	500	800377	2882023	0	80022	80041	80105	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	160032	0	0	0	160000	6	1	32	40	0	5109	1	17	1	1	80038	1	10	0	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	600	0	0	0	0	0	0	38	0	0	0	0	80026	2	12	12	0	25	400157	100	240057	160000	100	240000	160000	500	800377	2880000	0	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	160032	0	0	32	160000	6	1	0	0	0	5109	1	17	1	1	80038	0	10	10	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	599	0	0	0	0	0	0	311	176	1	0	0	80026	2	12	12	0	25	400157	100	240058	160000	100	240000	160000	500	800853	2880000	1	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	160000	0	0	0	160032	0	0	32	40	0	5109	1	17	1	1	80038	1	14	0	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	599	0	0	0	0	0	0	0	0	0	0	0	80026	2	12	12	0	25	400100	100	240000	160000	100	240000	160000	500	800000	2880000	1	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	160036	0	0	0	160032	6	1	32	40	0	5109	1	17	1	1	80038	1	10	14	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	600	0	0	0	0	0	0	0	0	0	0	0	80026	0	12	12	0	46	400100	100	240057	160000	100	240000	160000	500	800000	2880000	0	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	160032	0	1	41	160032	6	1	0	35	0	5109	1	17	1	1	80038	1	14	10	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	599	0	1	0	0	0	0	42	0	0	1	0	80026	0	12	0	0	25	400157	100	240063	160000	100	240000	160000	500	800374	2881968	1	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	160032	0	0	0	160032	6	1	0	35	0	5109	1	17	1	1	80038	1	10	10	160000	240000	100	80042	80042	80042	80042	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	1f	22	23	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	db	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	80055	600	0	0	0	0	0	0	54	0	1	0	2	80026	2	12	12	25	400068	10	240063	160000	10	240000	160000	50	800000	2881982	0	1	80022	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	1	10	160000	35	160032	0	35	160036	6	1	32	0	0	0	5022	3	1	1	1	22	17	0	0	23	18	80038	1	0	10	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	599	1	0	1	0	0	0	54	0	1	0	0	80026	2	12	12	25	400010	10	240063	160000	10	240000	160000	50	800960	2889757	0	0	80022	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160036	0	36	160036	6	0	0	35	0	0	5020	0	0	0	1	23	17	0	0	18	23	80038	0	14	10	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	600	1	0	1	0	0	0	0	0	1	0	0	80026	2	12	12	25	400010	10	240063	160000	10	240000	160000	50	800886	2883416	0	0	80022	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	160000	0	0	160036	6	1	32	35	0	0	5020	3	0	0	1	23	17	0	0	22	12	80038	1	0	10	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	599	1	0	1	0	0	0	42	0	1	0	2	80026	2	12	12	25	400073	10	240063	160000	10	240000	160000	50	800377	2881982	0	0	80022	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	1	10	160000	0	160036	0	0	160036	0	0	32	0	0	0	5022	3	0	0	1	13	17	0	0	23	12	80038	0	0	0	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	600	1	0	1	0	0	0	38	0	1	0	2	80026	2	0	12	47	400441	10	240000	160000	10	240000	160000	50	800075	2881977	0	0	80022	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160036	0	36	160032	6	1	36	0	0	0	5020	0	0	0	1	23	17	0	0	19	23	80038	0	14	14	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	599	1	0	1	0	0	0	42	0	1	0	2	80026	2	12	0	25	400073	10	240000	160000	10	240000	160000	50	800377	2883327	0	0	80022	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160036	0	36	160000	6	0	32	40	0	0	5020	0	0	0	1	23	17	0	0	23	22	80038	0	0	10	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	600	0	0	0	0	0	0	42	0	1	0	0	80026	0	12	12	25	400067	10	240063	160000	10	240000	160000	50	800000	2882021	0	0	80022	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160000	0	36	160032	6	1	0	0	0	0	5020	3	0	0	1	23	17	0	0	18	22	80038	0	0	0	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	599	1	0	1	0	0	0	42	0	1	0	0	80026	0	12	0	25	400010	10	240063	160000	10	240000	160000	50	800000	2883327	0	0	80022	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160000	0	36	160032	6	1	0	35	0	0	5020	3	0	0	1	15	17	0	0	22	13	80038	0	14	10	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	600	1	0	1	0	0	0	42	0	1	0	0	80026	0	12	12	25	400010	10	240058	160000	10	240000	160000	50	800000	2881975	0	0	80022	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480276	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160000	0	39	160049	6	1	0	0	0	0	5020	3	0	0	1	23	17	0	0	22	23	80038	0	14	0	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	600	1	0	1	0	0	1	38	0	1	0	2	80026	2	12	0	25	400073	10	240063	160000	10	240000	160000	50	803751	2881975	0	0	80022	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	160000	2	36	160032	6	1	36	35	0	0	5020	0	0	0	1	23	17	0	0	13	23	80038	0	10	14	160000	240000	10	80042	80042	80042	80042	80042

LD3 (multiple, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations