Firestorm: LD3 (multiple, 4H) measurements

Code:

  ld3 { v0.4h, v1.4h, v2.4h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.009

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 3.009

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	1e	22	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
65005	28592	213	10	1	3	0	1	0	0	1	0	10	1	5098	28048	0	2	16202	5012	3012	2000	3000	2000	10000	35793	0	0	8	22944	0	28411	28352	3	10	5000	2000	3000	2000	6000	28128	28339	1	1	61001	1000	1000	1	2004	3	4	2005	0	29	1	5	2000	4	2	4	2	1	13411	9750	7038	3454	5	78	19457	3158	3826	16	58	65	27897	14078	12334	13560	2000	3000	28603	28502	28039	28506	28542
65004	28324	213	4	1	1	1	1	1	0	0	0	2	0	4938	28220	0	0	16327	5015	3009	2000	3000	2000	10000	35638	0	0	8	22890	0	28358	28475	3	10	5000	2000	3000	2000	6000	28221	28509	1	1	61001	1000	1000	0	2004	3	0	2002	0	0	2	5	2000	0	2	4	2	6	13809	9895	7228	3306	1	61	19201	3197	3822	18	58	59	27918	14699	12281	13697	2000	3000	28502	28382	28508	28504	28579
65004	28598	213	5	1	1	1	1	1	0	0	0	2	1	4714	28253	1	0	16258	5003	3009	2000	3000	2000	10000	35643	1	0	0	22979	0	28493	28410	3	10	5000	2000	3000	2000	6000	28427	28328	1	1	61001	1000	1000	0	2002	3	4	2005	0	34	1	4	2000	4	4	4	2	0	13765	9788	7034	3330	0	57	19362	3210	3820	27	63	67	27972	15026	12452	14173	2000	3000	28647	28564	28628	28563	28343
65004	28565	213	7	1	1	1	1	1	0	0	0	2	0	4913	28298	0	0	16324	5009	3009	2000	3000	2000	10000	35755	3	1	8	22966	0	28455	28609	3	10	5000	2000	3000	2000	6000	28429	28326	1	1	61001	1000	1000	0	2002	3	4	2003	0	28	2	5	2002	4	2	6	2	1	13175	9678	7108	3420	0	64	19328	3320	3823	18	62	62	28014	15142	12003	14216	2000	3000	28549	28429	28442	28307	28370
65004	28395	213	4	1	1	1	1	1	0	0	0	4	0	4782	28072	0	0	16196	5012	3012	2000	3000	2000	10002	35746	0	0	8	22994	0	28513	28574	3	10	5000	2000	3000	2000	6000	28527	28456	1	1	61001	1000	1000	0	2003	3	4	2002	0	33	2	2	2002	4	2	4	2	1	13455	9980	7184	3341	2	63	19220	3177	3821	13	62	60	28040	14164	12432	13887	2000	3000	28299	28575	28669	28509	28237
65004	28333	213	2	1	1	1	1	1	0	0	0	5	0	4943	28048	0	0	16156	5009	3003	2000	3000	2000	10000	35628	1	1	8	22987	0	28409	28384	3	10	5000	2000	3000	2000	6000	28473	28261	1	1	61001	1000	1000	0	2002	3	6	2005	0	3	2	7	2000	4	2	6	2	1	13297	9677	7010	3279	1	62	19471	3221	3823	18	56	59	28060	14675	12130	13871	2000	3000	28548	28564	28549	28494	28489
65004	28281	214	6	1	1	1	1	1	0	0	0	2	0	4860	28074	2	1	16155	5009	3009	2000	3000	2000	10000	35724	0	0	0	22959	0	28307	28410	3	10	5000	2000	3000	2000	6000	28514	28228	1	1	61001	1000	1000	0	2002	2	4	2004	0	0	2	7	2000	4	2	0	2	2	13407	9782	7117	3306	1	58	19437	3346	3821	19	57	55	27944	15090	12419	13749	2000	3000	28523	28474	28372	28468	28578
65004	28622	213	5	1	1	1	1	0	0	0	0	3	0	5093	28130	0	0	16318	5012	3009	2000	3000	2000	10000	35729	0	0	8	22982	0	28198	28452	3	10	5000	2000	3000	2000	6000	28278	28172	1	1	61001	1000	1000	0	2003	2	4	2002	0	39	1	2	2000	4	2	4	2	1	13363	10038	7205	3170	2	59	19168	3183	3819	14	61	67	28022	15346	12078	13527	2000	3000	28615	28381	28339	28456	28257
65004	28321	212	6	1	1	0	1	0	0	0	0	299	1	5075	28302	0	0	16212	5009	3009	2000	3000	2000	10000	35761	1	1	0	22931	0	28396	28258	3	10	5000	2000	3000	2000	6000	28333	28188	1	1	61001	1000	1000	0	2003	4	4	2002	0	0	2	2	2000	0	4	4	2	1	13344	10041	7165	3360	0	59	19132	3197	3817	16	60	66	28050	14621	11961	13850	2000	3000	28121	28506	28293	28425	28478
65004	28341	212	4	1	1	1	1	1	1	0	0	3	1	4968	27964	0	0	16306	5009	3009	2000	3000	2000	10003	35637	5	0	0	22968	0	28301	28352	3	10	5000	2000	3000	2000	6000	28255	28221	1	1	61001	1000	1000	0	2002	3	4	2004	0	37	1	2	2000	0	2	6	2	2	13708	10063	7085	3355	2	67	19361	3198	3816	12	59	65	27870	14437	12252	13064	2000	3000	28394	28564	28375	28151	28543

Count: 8

Code:

  ld3 { v0.4h, v1.4h, v2.4h }, [x6]
  ld3 { v0.4h, v1.4h, v2.4h }, [x6]
  ld3 { v0.4h, v1.4h, v2.4h }, [x6]
  ld3 { v0.4h, v1.4h, v2.4h }, [x6]
  ld3 { v0.4h, v1.4h, v2.4h }, [x6]
  ld3 { v0.4h, v1.4h, v2.4h }, [x6]
  ld3 { v0.4h, v1.4h, v2.4h }, [x6]
  ld3 { v0.4h, v1.4h, v2.4h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	1f	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	80054	599	1	0	1	0	0	57	0	1	0	80026	2	5	5	3	25	400120	100	240068	160000	100	240000	160000	500	801386	2880258	1	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160015	13	0	160015	0	2	52	160039	6	1	52	43	13	1	5109	2	17	2	2	80038	13	13	1	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	599	1	1	0	0	0	12	0	0	2	80026	2	5	0	3	25	400174	100	240077	160000	100	240000	160000	500	800042	2884893	1	80022	80041	80041	0	3	23	400100	200	160092	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160013	13	0	160053	0	1	51	160039	6	1	12	0	13	0	5109	2	17	2	2	80038	13	0	1	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	600	1	1	1	0	0	58	0	1	2	80026	2	0	5	3	25	400179	100	240074	160000	100	240000	160000	500	801387	2884892	1	80022	80249	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160013	12	0	160054	0	1	52	160039	6	0	52	0	12	1	5109	2	17	2	2	80038	0	13	1	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	599	1	0	1	0	0	13	0	1	2	80026	2	5	5	3	25	400174	100	240074	160000	100	240000	160000	500	800042	2884893	1	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160014	13	43	160053	0	1	55	160039	6	1	52	0	13	1	5109	2	17	2	2	80103	0	13	1	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	599	1	1	0	0	0	58	0	0	2	80026	2	5	0	3	25	400120	100	240068	160000	100	240000	160000	500	801380	2886602	1	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	160013	15	0	160052	0	1	12	160000	0	1	52	43	13	1	5109	2	17	2	2	80038	13	13	0	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	600	1	1	0	0	0	58	0	1	0	80026	2	5	5	3	25	400168	100	240021	160000	100	240000	160000	500	801372	2884895	1	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160014	13	43	160053	0	1	55	160039	6	1	13	43	13	1	5109	2	17	2	2	80038	0	0	0	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	599	1	1	1	0	0	58	0	0	2	80026	2	5	5	0	25	400179	100	240071	160000	100	240000	160000	500	801387	2884892	1	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160013	13	43	160013	0	1	51	160000	6	1	52	43	13	1	5109	2	17	2	2	80038	13	13	0	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	600	1	1	1	0	0	58	0	1	2	80026	2	5	5	0	25	400168	100	240019	160000	100	240000	160000	500	800042	2880278	1	80022	80140	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160013	14	43	160014	0	2	54	160039	6	1	51	43	13	2	5109	2	17	2	2	80038	0	13	1	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	599	1	1	0	0	0	13	0	1	2	80026	2	5	5	3	25	400118	100	240071	160000	100	240000	160000	500	801383	2880249	1	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160015	15	43	160051	1	2	70	160039	0	1	52	43	13	0	5109	2	17	2	2	80038	0	13	1	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	599	1	0	1	0	0	12	0	0	2	80026	2	0	0	3	25	400118	100	240074	160000	100	240000	160000	500	800042	2884893	1	80022	80041	80041	0	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160014	14	43	160053	0	0	52	160039	0	1	13	0	12	1	5109	2	17	2	2	80038	13	13	0	160000	240000	100	80042	80042	80042	80042	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	80069	599	0	0	0	1	0	0	57	0	0	0	2	80026	2	0	12	0	25	400073	10	240000	160000	10	240000	160000	50	801386	2880278	0	80022	0	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	1	10	160013	14	0	160054	0	0	52	160039	6	1	52	43	13	1	0	5019	3	17	0	3	2	80038	0	13	13	0	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	599	1	0	1	0	0	0	12	0	0	0	2	80026	2	0	12	0	25	400073	10	240063	160000	10	240000	160000	50	800853	2881968	0	80022	0	80041	80041	0	0	3	23	400235	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	160000	0	35	160032	0	0	32	160000	6	1	32	35	0	0	0	5019	3	17	0	2	3	80038	0	14	10	0	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	600	0	0	0	0	0	0	42	0	0	0	2	80026	0	12	12	0	25	400010	10	240063	160000	10	240000	160000	50	800853	2880000	1	80022	0	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	160000	0	35	160036	0	0	0	160000	6	1	32	40	0	0	0	5019	3	17	0	3	3	80038	0	14	0	0	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	600	0	0	0	0	0	0	42	0	1	0	2	80026	2	0	12	0	25	400010	10	240000	160000	10	240000	160000	50	800374	2881968	0	80119	0	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	160000	0	35	160000	1	0	36	160036	6	0	0	35	0	0	0	5019	2	17	0	3	3	80038	0	14	0	0	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	599	0	0	0	0	0	0	42	0	0	0	0	80026	2	12	0	0	25	400073	10	240063	160000	10	240000	160000	50	800000	2880000	0	80022	0	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	160012	13	43	160051	0	1	51	160039	6	1	51	0	13	1	0	5019	3	17	0	3	3	80038	0	0	13	0	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	599	1	1	1	0	0	0	13	0	0	0	0	80026	2	0	5	3	25	400089	10	240079	160000	10	240000	160000	50	800048	2880258	0	80022	0	80041	80041	0	7	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	160000	0	35	160032	2	0	32	160000	6	1	32	40	0	0	0	5019	3	17	0	3	3	80038	0	10	14	0	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	599	0	0	0	0	0	0	38	0	0	0	2	80026	1	12	12	0	25	400010	10	240063	160000	10	240000	160000	50	800377	2880000	0	80022	0	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	160000	0	35	160036	0	0	32	160035	6	1	32	0	0	0	0	5019	3	17	0	3	3	80038	0	14	10	0	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	599	0	0	0	0	0	0	42	0	0	0	2	80026	0	12	12	0	25	400073	10	240063	160000	10	240000	160000	50	800853	2883365	1	80022	0	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	160000	0	35	160036	0	0	36	160036	0	0	36	40	0	0	0	5019	3	17	0	3	3	80038	0	0	10	0	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	600	0	0	0	1	0	0	42	0	0	0	2	80026	2	0	12	0	25	400010	10	240063	160000	10	240000	160000	50	800853	2881968	0	80022	0	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	160000	0	35	160000	0	0	0	160032	6	0	0	40	0	0	0	5019	3	17	0	2	3	80038	0	0	0	0	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	599	1	0	1	0	0	0	13	0	0	0	2	80026	2	5	5	3	25	400089	10	240079	160000	10	240000	160000	50	801386	2884997	0	80022	0	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	1	10	160013	13	43	160054	0	1	13	160039	0	0	52	43	12	3	0	5019	3	17	0	3	2	80038	0	14	0	0	160000	240000	10	80042	80042	80042	80042	80042

LD3 (multiple, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations