Firestorm: LD3 (multiple, 4S) measurements

Code:

  ld3 { v0.4s, v1.4s, v2.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.006

Integer unit issues: 0.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 3.006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	46	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
66005	29323	219	1	11	1	16	0	0	0	0	1	4610	28878	0	16856	6006	3006	3000	3000	3000	15000	35692	2	23016	29137	29276	3	10	6000	3000	3000	3000	9000	29133	29163	1	1	61001	1000	1000	1	3000	6	3000	0	1	3001	3	1	0	3	12906	9091	6869	3085	11	52	20058	3090	3821	5	36	34	28422	16400	13315	15032	3000	3000	29300	29234	29404	29315	29260
66004	29335	219	0	10	0	14	0	1	1	6	1	4668	28870	0	16868	6006	3006	3000	3000	3000	15000	35753	1	23009	29155	29219	3	10	6000	3000	3000	3000	9000	29095	29198	1	1	61001	1000	1000	0	3000	3	3001	0	1	3000	3	1	1	3	12829	9241	6866	3054	5	27	20074	3085	3812	13	35	34	28538	16356	13296	14908	3000	3000	29221	29283	29387	29254	29271
66004	29281	219	0	9	0	10	0	0	0	6	1	4570	28836	0	16856	6009	3003	3000	3000	3000	15000	35765	1	23076	29100	29269	3	10	6000	3000	3000	3000	9000	29140	29138	1	1	61001	1000	1000	0	3000	6	3000	0	0	3001	3	1	0	3	13032	9248	6852	3030	5	35	20071	3017	3820	7	36	38	28485	16356	13424	15031	3000	3000	29273	29236	29268	29230	29239
66004	29281	220	0	17	0	13	0	0	0	5	1	4541	28878	0	16847	6006	3003	3000	3000	3000	15000	35712	2	23053	29065	29243	3	10	6000	3000	3000	3000	9000	29135	29090	1	1	61001	1000	1000	0	3000	6	3006	0	0	3001	5	1	1	3	12921	9111	6869	3051	5	31	20119	3139	3828	9	31	27	28398	16374	13313	15027	3000	3000	29315	29294	29245	29272	29257
66004	29226	219	0	12	0	13	0	0	0	6	1	4579	28909	3	16887	6003	3006	3000	3000	3000	15000	35686	2	22929	29110	29265	3	10	6000	3000	3000	3000	9000	29147	29115	1	1	61001	1000	1000	0	3000	3	3000	0	1	3001	5	0	1	6	12989	9254	6878	3050	7	32	20113	3080	3821	7	35	31	28423	16430	13242	14626	3000	3000	29242	29233	29300	29254	29310
66004	29228	220	0	8	0	14	0	0	0	6	1	4654	28873	0	16882	6006	3003	3000	3000	3000	15003	35698	2	23009	29096	29266	3	10	6000	3000	3000	3000	9000	29260	29086	1	1	61001	1000	1000	0	3000	6	3000	0	1	3004	5	1	1	8	12838	9261	6839	3070	4	33	20023	3141	3821	9	37	38	28429	16240	13258	14929	3000	3000	29305	29277	29255	29228	29195
66004	29309	218	0	8	0	9	0	0	0	6	1	4584	28852	0	16828	6006	3003	3000	3000	3000	15000	35717	1	23016	29097	29288	3	10	6000	3000	3000	3000	9000	29142	29178	1	1	61001	1000	1000	0	3000	3	3001	0	0	3001	5	1	1	6	12812	9190	6958	3148	6	34	20093	3104	3819	7	30	34	28394	16474	13168	14879	3000	3000	29312	29253	29298	29285	29235
66004	29198	219	0	11	0	8	0	0	0	6	1	4601	28894	0	16840	6006	3006	3000	3000	3000	15000	35721	2	23007	29113	29166	3	10	6000	3000	3000	3000	9000	29105	29059	1	1	61001	1000	1000	0	3000	6	3000	0	1	3003	5	1	1	6	12971	8927	6808	3032	3	30	20099	3076	3815	9	37	40	28429	16381	13419	14979	3000	3000	29248	29218	29273	29267	29269
66004	29291	220	0	16	0	16	0	0	0	6	1	4622	28904	0	16902	6006	3006	3000	3000	3000	15000	35703	3	23015	29069	29227	3	10	6000	3000	3000	3000	9000	29071	29120	1	1	61002	1000	1000	0	3000	6	3001	0	1	3001	5	1	1	6	12788	9095	6851	3042	7	27	20107	3096	3823	8	33	32	28394	16235	13215	14875	3000	3000	29316	29319	29273	29305	29285
66004	29287	219	0	10	0	14	0	0	0	6	1	4654	28872	0	16862	6006	3006	3000	3000	3000	15005	35716	2	22950	29043	29256	3	10	6000	3000	3000	3000	9000	29129	29177	1	1	61001	1000	1000	0	3000	6	3000	0	1	3000	3	1	0	6	12750	9239	6862	3001	8	33	20087	3113	3811	9	32	35	28386	16271	13361	14817	3000	3000	29233	29192	29319	29220	29235

Count: 8

Code:

  ld3 { v0.4s, v1.4s, v2.4s }, [x6]
  ld3 { v0.4s, v1.4s, v2.4s }, [x6]
  ld3 { v0.4s, v1.4s, v2.4s }, [x6]
  ld3 { v0.4s, v1.4s, v2.4s }, [x6]
  ld3 { v0.4s, v1.4s, v2.4s }, [x6]
  ld3 { v0.4s, v1.4s, v2.4s }, [x6]
  ld3 { v0.4s, v1.4s, v2.4s }, [x6]
  ld3 { v0.4s, v1.4s, v2.4s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	23	37	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480205	80080	600	0	1	0	0	0	0	7	0	80047	2	0	4	14	25	480142	100	240043	240000	100	240000	240000	500	1676441	5730957	1	80047	80044	80044	10	0	3	48	480100	200	240000	240000	200	240000	720000	80066	80062	1	1	80201	100	99	1	100	100	80000	80000	0	100	240000	0	45	240043	0	0	0	240042	5	1	0	0	0	5109	1	17	1	1	80059	14	10	3	240000	240000	100	80067	80067	80045	80063	80045
480204	80044	599	0	1	1	47	1	0	2	2	80056	2	4	4	0	25	480415	100	240043	240000	100	240000	240000	500	3541752	5532980	1	80034	80046	80072	0	0	3	37	480100	200	240000	240000	200	240000	720000	80062	80062	1	1	80201	100	99	5	100	100	80000	80000	0	100	240000	0	0	240000	0	0	42	240000	5	0	0	45	0	5109	1	17	1	1	80063	14	14	0	240000	240000	100	80045	80045	80063	80067	80045
480204	80044	599	1	1	1	96	0	0	0	1	80051	0	0	4	14	25	480144	100	240044	240000	100	240000	240000	500	3529373	5542764	1	80025	80066	80044	14	0	3	44	480100	200	240000	240000	200	240000	720000	80062	80062	1	1	80201	100	99	5	100	100	80000	80000	0	100	240000	0	45	240000	0	0	42	240042	0	1	42	45	0	5109	1	17	1	1	80059	14	0	0	240000	240000	100	80045	80067	80045	80063	80067
480204	80066	599	0	1	1	48	0	0	2	2	80051	0	4	4	14	25	480142	100	240042	240000	100	240000	240000	500	3541752	3603263	1	80047	80066	80066	0	0	3	48	480100	200	240000	240000	200	240000	720000	80044	80062	1	1	80201	100	99	1	100	100	80000	80000	0	100	240000	0	45	240000	0	0	42	240000	0	1	43	0	0	5109	1	17	1	1	80063	0	0	3	240000	240000	100	80067	80067	80045	80067	80045
480204	80066	600	0	0	1	48	1	0	50	2	80051	0	4	4	14	25	480144	100	240042	240000	100	240000	240000	500	3524521	5569461	1	80047	80068	80044	0	0	3	48	480100	200	240000	240000	200	240000	720000	80066	80044	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	0	240000	1	0	0	240000	0	1	42	45	0	5109	1	17	1	1	80059	14	0	3	240000	240000	100	80067	80067	80072	80067	80067
480204	80066	600	0	1	1	0	0	0	3	1	80051	2	4	4	0	25	480143	100	240043	240000	100	240000	240000	500	1676441	5732393	1	80025	80062	80066	14	0	3	48	480100	200	240000	240000	200	240000	720000	80066	80044	1	1	80201	100	99	5	100	100	80000	80000	0	100	240000	0	0	240000	0	0	42	240043	5	0	42	45	0	5109	1	17	1	1	80063	14	0	0	240000	240000	100	80067	80067	80063	80067	80045
480204	80066	600	0	1	0	0	0	0	3	2	80234	0	15	0	0	25	480145	100	240045	240000	100	240000	240000	500	3529373	5542351	1	80025	80044	80044	10	0	3	26	480100	200	240000	240000	200	240000	720000	80044	80044	1	1	80201	100	99	5	100	100	80000	80000	0	100	240000	0	45	240000	0	0	43	240043	5	1	0	45	0	5109	1	17	1	1	80063	14	14	0	240000	240000	100	80067	80045	80067	80045	80045
480204	80066	600	0	1	1	48	0	0	1	2	80047	3	15	4	14	25	480105	100	240044	240000	100	240000	240000	500	1676441	3880301	1	80047	80062	80066	0	0	3	48	480100	200	240000	240000	200	240000	720000	80066	80044	1	1	80201	100	99	5	100	100	80000	80000	0	100	240000	0	45	240000	0	0	54	240000	0	1	43	0	0	5109	1	17	1	1	80041	14	0	3	240000	240000	100	80067	80067	80067	80067	80067
480204	80044	600	0	0	0	0	0	0	2	0	80029	0	4	0	0	25	480142	100	240043	240000	100	240000	240000	500	3541752	5532975	1	80047	80063	80066	14	0	3	48	480100	200	240000	240000	200	240000	720000	80062	80044	1	1	80201	100	99	5	100	100	80000	80000	0	100	240000	0	45	240043	0	0	0	240000	5	1	0	45	0	5109	1	17	1	1	80059	0	0	0	240000	240000	100	80066	80067	80067	80045	80087
480204	80066	600	0	0	0	51	0	0	3	0	80051	0	4	4	14	25	480144	100	240006	240000	100	240000	240000	500	3524521	5569535	1	80037	80070	80070	0	0	3	26	480100	200	240000	240000	200	240000	720000	80062	80044	1	1	80201	100	99	0	100	100	80000	80000	1	100	240000	0	0	240000	0	0	0	240043	6	1	42	0	0	5109	1	17	1	1	80063	0	0	3	240000	240000	100	80068	80067	80068	80063	80067

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	1e	22	24	37	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	cd	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480025	80067	600	0	0	1	1	48	1	0	1	0	80029	2	15	0	10	25	480052	10	240042	240000	10	240000	240000	50	3524329	5532975	4	1	80025	80068	80062	0	0	3	48	480010	20	240000	240000	20	240000	720000	80062	80062	1	1	80021	10	9	1	10	10	80000	80000	0	10	240017	17	43	0	240017	0	1	20	240040	5	1	0	0	0	0	5019	1	17	1	1	1	80059	10	10	0	240000	240000	10	80063	80045	80063	80063	80063
480024	80062	600	0	0	1	1	48	0	0	12	0	80047	2	15	15	14	25	480020	10	240045	240000	10	240000	240000	50	3288778	5579325	3	1	80025	80062	80044	10	0	3	26	480010	20	240000	240000	20	240000	720000	80381	80091	1	1	80021	10	9	1	10	10	80000	80000	0	10	240000	0	45	0	240042	1	0	44	240042	5	1	41	45	0	0	5019	1	17	0	1	1	80059	10	10	0	240000	240000	10	80063	80045	80045	80063	80063
480024	80062	599	0	0	0	0	47	0	0	0	1	80047	2	15	15	0	25	480053	10	240046	240000	10	240000	240000	50	3542951	5731103	8	1	80043	80062	80066	9	0	19	243	480010	20	240000	240000	20	240000	720000	80044	80062	1	1	80021	10	9	0	10	10	80000	80000	1	10	240000	0	45	0	240000	0	0	0	240000	0	1	42	45	0	0	5019	1	17	0	1	1	80041	10	10	0	240000	240000	10	80067	80063	80045	80063	80045
480024	80062	600	0	0	1	1	47	1	0	0	0	80047	2	4	15	0	25	480016	10	240042	240000	10	240000	240000	50	1676441	5532980	8	1	80025	80062	80062	9	0	3	44	480010	20	240000	240000	20	240000	720000	80044	80062	1	1	80021	10	9	1	10	10	80000	80000	0	10	240000	0	45	0	240000	1	0	42	240042	5	0	42	0	0	0	5019	1	17	0	1	1	80041	10	10	0	240000	240000	10	80063	80045	80045	80045	80045
480024	80044	600	0	0	1	1	0	1	0	8	1	80047	0	15	15	13	25	480052	10	240042	240000	10	240000	240000	50	3541560	5542353	7	1	80043	80062	80044	10	15	3	26	480010	20	240000	240000	20	240000	720000	80062	80044	1	1	80021	10	9	1	10	10	80000	80000	0	10	240000	0	45	0	240042	0	0	42	240042	0	1	42	45	0	0	5019	1	17	0	1	1	80059	10	10	0	240000	240000	10	80045	80063	80063	80063	80045
480024	80071	601	0	0	0	1	47	1	0	0	0	80029	2	15	15	10	25	480052	10	240042	240000	10	240000	240000	50	3524329	5542344	0	0	80043	80066	80044	10	0	3	48	480010	20	240000	240000	20	240000	720000	80062	80062	1	1	80021	10	9	1	10	10	80000	80000	0	10	240000	0	45	0	240042	0	0	42	240043	0	1	42	45	0	0	5019	1	17	0	1	1	80041	10	10	0	240000	240000	10	80045	80063	80063	80067	80063
480024	80062	600	0	0	0	1	47	1	0	1	1	80047	0	15	0	10	25	480052	10	240042	240000	10	240000	240000	50	3524521	5693971	0	1	80043	80062	80062	0	0	3	44	480010	20	240000	240000	20	240000	720000	80062	80044	1	1	80021	10	9	1	10	10	80000	80000	0	10	240000	0	45	0	240042	0	0	42	240000	5	1	42	45	0	0	5019	1	17	0	1	1	80059	10	10	0	240000	240000	10	80063	80063	80063	80063	80063
480024	80062	599	1	1	0	0	47	0	0	1	0	80047	2	0	15	10	25	480016	10	240008	240000	10	240000	240000	50	3529181	5783076	0	1	80043	80062	80062	0	0	3	44	480010	20	240000	240000	20	240000	720000	80062	80062	1	1	80021	10	9	1	10	10	80000	80000	0	10	240000	0	0	0	240041	0	0	42	240000	0	0	42	45	0	0	5019	1	17	0	1	1	80059	10	0	0	240000	240000	10	80045	80067	80063	80063	80045
480024	80066	600	0	0	1	0	47	0	0	3	1	80047	2	0	15	10	25	480052	10	240042	240000	10	240000	240202	50	3529373	5723241	0	1	80047	80062	80044	10	0	3	44	480010	20	240000	240000	20	240000	720000	80079	80045	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	45	0	240041	0	0	0	240042	6	0	42	45	0	0	5019	1	17	0	1	1	80041	14	10	0	240000	240000	10	80063	80074	80066	80063	80045
480024	80062	599	0	0	0	0	48	1	0	5	1	80047	2	4	0	10	25	480052	10	240045	240000	10	240000	240000	50	3541560	5725599	0	0	80025	80044	80062	10	0	3	44	480010	20	240000	240000	20	240000	720000	80044	80044	1	1	80021	10	9	1	10	10	80000	80000	1	10	240000	0	45	0	240000	0	0	42	240042	5	1	41	45	0	0	5019	1	17	0	1	1	80059	10	0	0	240000	240000	10	80067	80063	80063	80045	80045

LD3 (multiple, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations