Firestorm: LD3 (multiple, 8B) measurements

Code:

  ld3 { v0.8b, v1.8b, v2.8b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.006

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 3.006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	0e	0f	1e	22	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
65005	29366	221	2	1	3	0	0	0	1	0	0	4665	28785	0	0	0	16946	5009	3009	2000	3000	2000	10000	35722	11	22916	29125	29279	3	10	5000	2000	3000	2000	6000	29192	29146	1	1	61001	1000	1000	0	2000	0	2000	0	0	2000	4	2	4	0	12985	9087	6869	3058	0	60	20209	3118	3822	10	54	48	28450	16324	13311	14960	2000	3000	29331	29248	29260	29317	29277
65004	29268	219	0	1	0	0	1	0	0	0	0	4559	28783	0	0	0	16989	5000	3009	2000	3000	2000	10000	35761	9	22882	29130	29301	3	10	5000	2000	3000	2000	6000	29129	29219	1	1	61001	1000	1000	0	2000	6	2000	0	0	2000	4	0	0	0	12860	9061	6866	3090	0	53	20377	3049	3822	14	48	48	28389	16247	13171	15007	2000	3000	29305	29270	29286	29269	29273
65004	29353	220	1	1	0	1	0	6	0	0	0	4674	28878	0	0	0	17020	5006	3012	2000	3000	2000	10000	35628	3	22824	29119	29242	3	10	5000	2000	3000	2000	6000	29136	29270	1	1	61001	1000	1000	0	2000	6	2002	0	0	2000	0	0	4	0	12841	9038	6836	3078	1	47	20203	3057	3822	14	46	47	28358	16349	13478	15026	2000	3000	29199	29302	29332	29243	29198
65004	29293	219	0	0	0	0	0	6	1	0	0	4567	28821	0	0	0	16877	5006	3006	2000	3000	2000	10000	35743	0	22906	29082	29179	3	10	5000	2000	3000	2000	6000	29074	29220	1	1	61001	1000	1000	1	2000	4	2000	0	0	2000	4	2	6	0	12776	9161	6862	3058	1	51	20225	3086	3825	12	44	50	28412	16089	13273	15169	2000	3000	29306	29255	29334	29300	29204
65004	29303	218	0	0	0	0	0	4	0	0	0	4623	28885	0	0	0	16948	5006	3006	2000	3000	2000	10004	35807	3	22930	29076	29317	3	10	5000	2000	3000	2000	6000	29209	29150	1	1	61001	1000	1000	0	2000	6	2000	0	0	2002	4	0	6	0	12835	9071	6825	3021	1	51	20233	3033	3829	13	49	45	28443	16395	13418	15045	2000	3000	29333	29266	29290	29287	29298
65004	29310	218	0	0	0	0	0	0	0	0	0	4581	28879	0	0	0	16967	5012	3012	2000	3000	2000	10000	35738	3	22903	29073	29359	3	10	5000	2000	3000	2000	6000	29040	29123	1	1	61001	1000	1000	0	2000	6	2000	0	2	2000	4	0	0	0	12891	9193	6871	3072	1	44	20234	3062	3826	12	46	51	28451	16568	13353	14896	2000	3000	29245	29279	29333	29308	29264
65004	29346	220	0	0	0	0	0	0	0	0	0	4560	28849	0	0	0	17032	5006	3006	2000	3000	2000	10000	35686	0	22882	29052	29304	3	10	5000	2000	3000	2000	6000	29114	29105	1	1	61001	1000	1000	1	2000	4	2000	1	0	2002	0	0	4	0	13031	9140	6843	3062	0	41	20215	3029	3825	14	45	44	28463	16416	13340	15054	2000	3000	29238	29235	29231	29240	29206
65004	29175	219	1	1	1	0	0	4	1	0	0	4506	28863	0	0	0	17012	5006	3000	2000	3000	2000	10000	35768	7	22877	29087	29249	3	10	5000	2000	3000	2000	6000	29194	29179	1	1	61001	1000	1000	0	2000	0	2002	0	5	2000	4	2	6	0	12719	9129	6846	3080	0	45	20183	3049	3822	11	48	45	28435	16405	13284	14961	2000	3000	29337	29336	29372	29309	29318
65004	29207	219	0	0	1	0	0	6	0	0	0	4598	28781	0	0	0	16985	5000	3006	2000	3000	2000	10000	35751	11	22860	29162	29263	3	10	5000	2000	3000	2000	6000	29148	29140	1	1	61001	1000	1000	0	2000	4	2002	0	3	2000	4	0	4	0	12737	9093	6880	3065	0	45	20181	3103	3823	11	49	48	28452	16292	13356	15063	2000	3000	29264	29315	29312	29245	29316
65004	29264	219	0	0	0	0	0	0	0	0	0	4607	28822	0	2	2	16989	5000	3000	2000	3000	2000	10000	35692	2	22905	29109	29285	3	10	5000	2000	3000	2000	6000	29149	29058	1	1	61001	1000	1000	1	2000	6	2002	0	0	2002	6	0	4	0	12892	9190	6882	3077	0	42	20163	3067	3828	15	47	47	28380	16417	13383	14750	2000	3000	29270	29253	29314	29369	29342

Count: 8

Code:

  ld3 { v0.8b, v1.8b, v2.8b }, [x6]
  ld3 { v0.8b, v1.8b, v2.8b }, [x6]
  ld3 { v0.8b, v1.8b, v2.8b }, [x6]
  ld3 { v0.8b, v1.8b, v2.8b }, [x6]
  ld3 { v0.8b, v1.8b, v2.8b }, [x6]
  ld3 { v0.8b, v1.8b, v2.8b }, [x6]
  ld3 { v0.8b, v1.8b, v2.8b }, [x6]
  ld3 { v0.8b, v1.8b, v2.8b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	80069	600	1	1	42	0	0	0	0	80027	2	12	0	0	26	400178	100	240120	160012	100	240024	160016	500	800210	2882157	0	80022	80042	80042	6	13	400140	200	160016	240024	200	160016	480048	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160004	35	160040	0	0	160040	6	1	0	35	1	1	1	5116	0	16	0	0	80039	0	14	10	160000	240000	100	80044	80043	80044	80043	80043
400204	80042	599	0	0	42	0	0	0	2	80028	2	12	12	0	25	400184	100	240009	160012	100	240024	160016	500	800929	2882167	1	80022	80042	80043	6	13	400140	200	160016	240024	200	160016	480048	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160004	35	160040	0	36	160036	6	1	0	40	1	1	1	5117	0	16	0	0	80039	0	14	14	160000	240000	100	80043	80043	80043	80043	80043
400204	80042	600	1	0	42	0	0	0	0	80027	0	0	12	0	25	400121	100	240072	160012	100	240024	160016	500	801096	2880856	0	80022	80042	80042	6	13	400140	200	160016	240024	200	160016	480048	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160004	0	160036	0	32	160040	6	0	32	35	1	1	1	5116	0	16	0	0	80039	0	14	10	160000	240000	100	80044	80044	80043	80043	80043
400204	80042	599	0	0	42	0	0	0	0	80027	0	0	12	0	25	400121	100	240072	160012	100	240024	160016	500	800929	2882164	0	80022	80042	80042	6	13	400140	200	160016	240024	200	160016	480048	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160004	0	160036	0	36	160040	6	1	32	35	1	1	1	5116	0	16	0	0	80039	0	0	14	160000	240000	100	80043	80043	80043	80043	80044
400204	80042	600	0	0	42	0	0	0	0	80027	2	12	0	0	25	400121	100	240072	160012	100	240024	160016	500	800929	2883516	0	80022	80041	80041	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	160000	0	36	160036	0	0	32	0	0	0	0	5109	1	17	1	1	80038	0	0	14	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	599	0	0	9	0	1	0	2	80026	0	12	12	0	25	400163	100	240063	160000	100	240000	160000	500	800853	2883327	0	80022	80041	80041	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	160036	0	0	160036	0	1	32	0	0	0	0	5109	1	17	1	1	80038	0	14	10	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	599	0	0	42	0	0	0	0	80026	2	12	0	0	25	400163	100	240063	160000	100	240000	160000	500	800853	2883329	0	80022	80041	80041	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	160096	0	0	160000	6	0	0	40	0	0	0	5109	1	17	1	1	80038	0	0	14	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	599	0	0	3	0	1	0	2	80026	2	12	12	0	25	400100	100	240000	160000	100	240000	160000	500	800374	2880000	1	80022	80041	80041	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	160000	0	32	160000	6	0	32	40	0	0	0	5109	1	17	1	1	80038	0	14	0	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	600	0	0	42	0	0	0	2	80026	2	12	12	0	25	400100	100	240058	160000	100	240000	160000	500	800853	2883330	0	80022	80041	80041	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	160000	0	36	160036	0	1	0	0	0	0	0	5109	1	17	1	1	80038	0	14	14	160000	240000	100	80042	80042	80042	80042	80042
400204	80041	600	0	0	0	0	0	1	0	80026	2	12	0	0	25	400163	100	240063	160000	100	240000	160000	500	800853	2880000	0	80022	80041	80041	3	23	400100	200	160000	240000	200	160000	480000	80041	80041	2	1	80201	100	99	100	100	80000	80000	0	100	160000	35	160035	0	0	160036	0	1	32	40	0	0	0	5109	1	17	1	1	80038	1	10	10	160000	240000	100	80042	80042	80042	80042	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cd	cf	d0	d2	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	80056	600	0	0	0	1	0	0	0	0	0	482	0	1	0	0	80026	2	0	12	0	25	400056	10	240057	160000	10	240000	160000	50	800000	2881210	0	1	80022	80041	80041	0	7	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	160000	0	0	32	160032	6	1	24	35	0	0	5019	0	0	17	17	0	0	9	10	80038	1	10	6	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	599	0	0	0	1	0	0	0	0	0	765	0	0	0	1	80026	2	12	12	0	25	400010	10	240057	160000	10	240000	160000	50	800000	2881282	0	0	80022	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	160032	0	0	32	160032	6	1	0	0	0	0	5019	0	0	11	17	0	0	8	10	80038	1	10	10	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	599	0	0	0	0	0	0	0	0	0	825	0	1	0	1	80026	2	0	0	0	25	400068	10	240045	160000	10	240000	160000	50	800398	2880000	0	0	80022	80041	80041	0	0	29	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	160032	0	0	32	160000	6	1	32	35	0	1	5019	0	0	9	17	0	0	9	10	80038	1	10	0	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	600	0	0	0	0	0	0	0	0	0	870	0	0	0	1	80026	2	12	12	0	25	400055	10	240057	160000	10	240000	160000	50	800374	2881210	0	0	80022	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	0	160024	0	0	32	160032	6	0	24	35	0	0	5019	0	0	10	17	0	0	8	10	80038	1	0	6	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	599	0	0	0	0	0	0	0	0	0	879	0	0	0	0	80026	2	0	12	0	25	400056	10	240000	160000	10	240000	160000	50	800377	2881212	0	0	80022	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	160024	0	0	0	160000	0	0	24	0	0	0	5019	0	0	10	17	0	0	10	10	80038	1	10	10	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	599	0	0	0	0	0	0	0	0	0	30	0	1	0	1	80026	2	12	12	0	25	400067	10	240000	160000	10	240000	160000	50	800374	2881210	0	0	80022	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	0	160024	0	0	0	160042	6	1	0	0	0	0	5019	0	0	10	17	0	0	9	11	80038	0	0	10	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	600	0	0	0	0	0	1	0	0	0	924	0	0	0	1	80026	0	0	12	0	25	400067	10	240000	160000	10	240000	160000	50	800374	2881968	0	1	80022	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	160032	1	0	32	160032	6	1	24	0	0	0	5019	0	0	10	17	0	0	10	10	80038	1	10	10	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	600	0	0	0	0	0	0	0	0	0	957	0	1	0	1	80026	2	12	12	0	25	400072	10	240057	160000	10	240000	160000	50	800374	2881210	0	0	80022	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	0	160000	0	0	0	160000	0	1	24	0	0	0	5019	0	0	9	17	0	0	10	10	80038	0	10	6	160000	240000	10	80042	80106	80042	80042	80042
400024	80041	600	0	0	0	0	0	0	0	0	0	894	0	0	0	1	80026	2	12	12	0	25	400068	10	240000	160000	10	240000	160000	50	800377	2880000	0	0	80022	80041	80041	0	0	3	23	400010	20	160000	240000	20	160000	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	0	160000	0	0	32	160000	0	0	32	35	0	0	5019	0	0	9	17	0	1	11	9	80038	1	10	10	160000	240000	10	80042	80042	80042	80042	80042
400024	80041	600	0	0	0	0	0	0	0	0	0	879	0	1	0	1	80026	2	12	0	0	25	400010	10	240057	160000	10	240000	160000	50	800374	2880000	0	0	80022	80041	80041	0	0	3	23	400010	20	160000	240000	20	160092	480000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	160032	0	0	207	160000	6	0	0	35	0	0	5019	0	0	9	17	0	0	9	8	80038	1	10	10	160000	240000	10	80042	80042	80042	80042	80042

LD3 (multiple, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations