Firestorm: LD3 (multiple, 8H) measurements

Code:

  ld3 { v0.8h, v1.8h, v2.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.006

Integer unit issues: 0.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 3.006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	0e	0f	1e	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
66005	29357	219	9	1	0	1	0	0	0	9	1	0	0	4592	28977	0	1	16861	6000	3006	3000	3000	3000	15000	35730	6	22947	29095	29297	3	10	6000	3000	3000	3000	9000	29133	29212	1	1	61001	1000	1000	0	3000	0	9	3004	0	0	1	3004	5	1	4	6	0	12980	9077	6847	3144	0	78	20105	3124	3821	12	56	51	28348	16494	13351	15160	3000	3000	29314	29386	29313	29212	29259
66004	29348	219	4	0	0	1	0	0	0	9	1	0	0	4562	28921	0	3	16912	6006	3006	3000	3000	3000	15004	35586	4	22963	29181	29233	3	10	6000	3000	3000	3000	9000	29182	29155	1	1	61001	1000	1000	0	3000	0	6	3000	0	0	0	3004	5	1	0	0	0	12776	9020	6839	3075	0	60	20181	3209	3814	12	50	52	28624	16293	13124	15012	3000	3000	29229	29287	29179	29279	29339
66004	29205	220	5	0	0	0	0	0	0	9	1	0	0	4542	28991	3	1	16975	6009	3009	3000	3000	3000	15004	35705	5	22991	29072	29198	3	10	6000	3000	3000	3000	9000	29167	29197	1	1	61001	1000	1000	0	3000	0	0	3004	0	0	4	3004	5	1	4	9	0	12892	9098	6982	3159	1	56	20116	3061	3816	18	65	60	28371	16397	13189	14542	3000	3000	29206	29395	29325	29286	29234
66004	29327	220	4	0	0	0	0	0	0	0	0	0	0	4564	28850	1	3	16837	6009	3009	3000	3000	3000	15000	35736	8	22987	29248	29245	3	10	6000	3000	3000	3000	9000	29192	29132	1	1	61001	1000	1000	0	3000	0	9	3004	0	0	0	3001	5	0	4	0	0	12868	9042	6965	3154	2	49	20173	3134	3821	18	59	50	28549	16335	13232	14809	3000	3000	29437	29360	29257	29216	29398
66004	29226	220	2	0	0	0	0	0	0	9	0	0	0	4684	28914	0	1	17001	6009	3009	3000	3000	3000	15000	35694	0	23002	29171	29205	3	10	6000	3000	3000	3000	9000	29154	29161	1	1	61001	1000	1000	0	3000	0	6	3004	1	2	4	3001	5	1	4	9	0	12855	9216	6943	3034	1	58	20026	3128	3818	8	56	53	28547	16383	13209	15044	3000	3000	29205	29248	29259	29262	29280
66004	29205	220	5	0	0	0	0	0	0	9	1	0	0	4758	28833	1	0	16821	6006	3008	3000	3000	3000	15000	35617	10	23036	29086	29269	3	10	6000	3000	3000	3000	9000	29064	29123	1	1	61001	1000	1000	0	3000	0	9	3000	0	0	1	3004	5	1	1	9	0	12841	9485	6791	3227	0	59	20109	3103	3816	18	52	52	28394	16098	12947	14820	3000	3000	29357	29190	29241	29328	29231
66004	29215	219	3	0	0	0	0	0	0	6	1	0	0	4608	28890	0	0	16923	6008	3000	3000	3000	3000	15000	35617	3	22942	29172	29252	3	10	6000	3000	3000	3000	9000	29290	29219	1	1	61001	1000	1000	0	3000	0	9	3001	1	0	0	3000	5	1	4	6	0	12741	9008	6936	3037	2	62	20130	3097	3818	15	53	59	28360	16358	13242	14939	3000	3000	29306	29318	29285	29329	29245
66004	29198	219	4	0	0	0	0	0	0	9	1	0	0	4559	28786	1	0	16976	6006	3006	3000	3000	3000	15000	35623	5	23005	29043	29287	3	10	6000	3000	3000	3000	9000	29029	29200	1	1	61001	1000	1000	0	3000	0	0	3004	0	0	0	3001	5	1	4	6	0	12884	9130	6851	3072	0	59	20069	3013	3816	13	54	58	28438	16200	13237	14851	3000	3000	29298	29318	29197	29303	29326
66004	29341	219	4	0	0	0	0	0	0	10	0	0	0	4571	28934	0	1	16995	6006	3008	3000	3000	3000	15000	35779	2	23081	29051	29280	3	10	6000	3000	3000	3000	9000	29151	29127	1	1	61001	1000	1000	1	3000	0	6	3000	0	0	0	3004	5	1	1	9	0	12918	9146	6924	3075	0	53	20103	3170	3813	11	51	58	28705	16367	13381	14867	3000	3000	29195	29324	29213	29252	29250
66004	29238	219	3	0	0	1	0	0	1	6	1	0	0	4586	28733	3	0	16810	6009	3008	3000	3000	3000	15000	35699	3	23031	29180	29257	3	10	6000	3000	3000	3000	9000	29226	29077	1	1	61001	1000	1000	0	3000	2	9	3001	0	0	4	3001	5	1	4	6	0	12807	9207	6901	3156	0	49	19990	3087	3822	13	58	58	28391	16262	13100	14765	3000	3000	29321	29395	29285	29248	29364

Count: 8

Code:

  ld3 { v0.8h, v1.8h, v2.8h }, [x6]
  ld3 { v0.8h, v1.8h, v2.8h }, [x6]
  ld3 { v0.8h, v1.8h, v2.8h }, [x6]
  ld3 { v0.8h, v1.8h, v2.8h }, [x6]
  ld3 { v0.8h, v1.8h, v2.8h }, [x6]
  ld3 { v0.8h, v1.8h, v2.8h }, [x6]
  ld3 { v0.8h, v1.8h, v2.8h }, [x6]
  ld3 { v0.8h, v1.8h, v2.8h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	1e	22	37	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480205	80085	599	1	1	0	0	0	0	65	1	2	2	80051	2	18	18	1	25	480139	100	240021	240000	100	240000	240000	500	3552190	5751169	0	80048	0	80072	80054	14	3	54	480100	200	240000	240000	200	240000	720000	80054	80067	1	1	80201	100	99	100	100	80000	80000	0	100	240018	17	0	240070	1	0	1	35	240039	5	1	32	0	17	2	5109	1	17	1	1	80229	0	9	0	240000	240000	100	80068	80054	80068	80068	80055
480204	80067	602	1	1	0	0	0	0	35	0	3	2	80052	3	18	30	1	25	480139	100	240039	240000	100	240000	240000	500	3505840	5776087	0	80048	3	80067	80055	14	3	49	480100	200	240000	240000	200	240000	720000	80067	80053	1	1	80201	100	99	100	100	80000	80000	0	100	240019	17	42	240056	1	0	2	35	240039	5	1	32	42	17	0	5109	1	17	1	1	80187	0	9	0	240000	240000	100	80068	80071	80068	80073	80068
480204	80067	600	1	1	0	0	0	0	64	1	2	2	80042	2	18	0	13	25	480121	100	240021	240000	100	240000	240000	500	3502397	5750782	1	80053	0	80067	80054	1	3	49	480100	200	240000	240000	200	240000	720000	80054	80054	1	1	80201	100	99	100	100	80000	80000	0	100	240017	18	42	240070	1	0	0	59	240039	0	1	56	42	17	1	5109	1	17	1	1	80369	0	0	1	240000	240000	100	80068	80068	80068	80069	80054
480204	80067	599	1	1	1	0	0	0	35	0	4	4	80039	15	0	18	1	25	480120	100	240032	240000	100	240000	240000	500	3530136	5755891	0	80051	0	80072	80072	19	3	54	480100	200	240000	240000	200	240000	720000	80067	80071	1	1	80201	100	99	100	100	80000	80000	1	100	240018	17	42	240056	1	0	0	35	240039	5	0	56	0	17	0	5109	1	17	1	1	80050	0	0	0	240000	240000	100	80068	80060	80068	80069	80073
480204	80066	600	1	1	1	0	0	0	65	1	1	2	80052	2	0	0	13	25	480139	100	240020	240000	100	240000	240000	500	3500140	5750713	1	80053	0	80067	80054	14	3	49	480100	200	240000	240000	200	240000	720000	80054	80054	1	1	80201	100	99	100	100	80000	80000	0	100	240017	18	57	240032	0	0	2	35	240053	5	0	56	44	17	1	5109	1	17	1	1	80342	9	0	0	240000	240000	100	80068	80054	80068	80068	80068
480204	80067	600	1	0	0	0	0	0	64	0	4	3	80057	3	18	0	1	25	480139	100	240039	240000	100	240000	240000	500	3542979	5776333	0	80047	0	80071	80053	15	3	49	480100	200	240000	240000	200	240000	720000	80067	80072	1	1	80201	100	99	100	100	80000	80000	0	100	240019	18	42	240056	0	0	1	59	240040	6	1	32	42	17	1	5109	1	17	1	1	80164	6	9	1	240000	240000	100	80068	80058	80071	80068	80071
480204	80054	600	1	1	1	0	0	0	79	0	4	2	80052	15	18	0	14	25	480139	100	240042	240000	100	240000	240000	500	3509722	5705547	0	80048	0	80072	80067	15	3	66	480100	200	240000	240000	200	240000	720000	80072	80067	1	1	80201	100	99	100	100	80000	80000	1	100	240019	18	0	240055	0	0	1	35	240039	5	1	57	42	17	0	5109	1	17	1	1	80336	9	9	0	240000	240000	100	80055	80055	80068	80054	80073
480204	80067	599	1	0	1	0	0	0	64	1	0	1	80067	3	18	0	14	25	480139	100	240039	240000	100	240000	240000	500	3542979	5715080	0	80048	0	80067	80053	1	3	49	480100	200	240000	240000	200	240000	720000	80080	80068	1	1	80201	100	99	100	100	80000	80000	0	100	240019	17	42	240032	0	0	1	73	240015	5	1	56	42	17	0	5109	1	17	1	1	80050	9	0	2	240000	240000	100	80057	80055	80068	80055	80068
480204	80067	600	1	1	1	0	0	0	65	0	4	1	80052	2	18	0	14	25	480124	100	240046	240000	100	240000	240000	500	3545551	5690539	0	80034	0	80054	80072	1	3	36	480100	200	240000	240000	200	240000	720000	80075	80075	1	1	80201	100	99	100	100	80000	80000	0	100	240017	20	42	240032	0	0	2	77	240040	5	1	70	44	17	1	5109	1	17	1	1	80064	9	9	0	240000	240000	100	80068	80068	80055	80068	80055
480204	80053	600	1	0	0	1	0	0	59	0	1	2	80039	3	0	18	17	25	480139	100	240039	240000	100	240000	240000	500	3505840	5776285	0	80048	0	80053	80067	19	3	49	480100	200	240000	240000	200	240000	720000	80083	80073	1	1	80201	100	99	100	100	80000	80000	0	100	240019	18	42	240032	1	0	1	35	240054	5	0	32	43	17	1	5109	1	17	1	1	80051	9	9	1	240000	240000	100	80068	80068	80055	80068	80068

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	1e	22	23	37	3a	3f	43	46	49	4f	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d0	d2	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480025	80063	600	0	0	0	0	0	0	41	1	0	2	2	80052	3	18	18	14	4	25	480045	10	240030	240000	10	240000	240000	50	3524561	5663662	0	0	0	80030	80067	80066	14	0	3	68	480010	20	240000	240000	20	240000	720000	80062	80044	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	0	0	240037	0	0	0	37	240037	5	1	0	39	0	0	0	5019	0	0	2	17	0	2	3	80064	0	9	0	240000	240000	10	80068	80051	80051	80068	80068
480024	80067	600	1	1	1	0	0	0	64	1	0	2	1	80042	3	19	19	5	0	25	480018	10	240039	240000	10	240000	240000	50	2392151	5762629	0	0	0	80038	80057	80057	4	0	3	39	480010	20	240213	240000	20	240000	720000	80184	80057	1	1	80021	10	9	10	10	80000	80000	0	10	240017	18	42	0	240056	1	0	1	20	240039	6	1	57	42	17	0	0	5019	5	0	3	17	0	2	3	80054	6	6	0	240000	240000	10	80058	80058	80057	80058	80058
480024	80057	599	0	0	0	0	0	0	42	0	0	2	3	80052	3	0	0	13	0	25	480064	10	240047	240000	10	240000	240000	50	3492808	5751540	0	1	5	80047	80067	80050	14	0	3	49	480010	20	240000	240000	20	240000	720000	80066	80061	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	39	0	240037	0	0	0	37	240037	0	0	37	38	0	0	0	5019	5	0	3	17	0	3	2	80064	9	9	0	240000	240000	10	80068	80051	80068	80050	80050
480024	80067	599	1	1	0	0	0	0	64	0	0	9	0	80029	3	19	19	0	0	25	480044	10	240001	240000	10	240000	240000	50	3509136	5536968	0	1	5	80025	80057	80057	0	0	3	29	480010	20	240000	240000	20	240000	720000	80078	80067	1	1	80021	10	9	10	10	80000	80000	0	10	240018	18	42	0	240058	0	0	1	20	240040	0	1	57	0	17	1	0	5019	5	1	4	17	0	3	2	80054	6	6	0	240000	240000	10	80058	80058	80045	80058	80058
480024	80057	599	0	0	0	0	0	0	0	0	0	3	2	80042	2	0	0	0	0	25	480056	10	240036	240000	10	240000	240000	50	3538809	4863673	0	1	5	80031	80067	80066	0	0	3	31	480010	20	240000	240000	20	240000	720000	80062	80071	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	38	0	240037	0	0	0	64	240037	0	1	37	39	0	0	0	5019	5	1	5	17	0	2	3	80064	9	9	0	240000	240000	10	80068	80068	80068	80067	80050
480024	80067	599	1	0	1	0	0	0	64	1	0	0	1	80042	3	19	0	0	0	25	480049	10	240005	240000	10	240000	240000	50	3522822	3603349	0	1	5	80025	80057	80057	0	0	3	39	480010	20	240000	240000	20	240000	720000	80059	80067	1	1	80021	10	9	10	10	80000	80000	0	10	240017	18	42	0	240057	0	0	0	60	240000	0	0	56	42	17	1	0	5019	5	1	4	17	0	3	3	80041	0	0	0	240000	240000	10	80058	80057	80045	80057	80058
480024	80044	599	0	0	0	0	0	0	42	1	0	26	3	80053	2	18	18	17	0	25	480053	10	240056	240000	10	240000	240000	50	3538809	5503798	0	1	5	80048	80067	80245	14	0	3	31	480010	20	240000	240000	20	240000	720000	80054	80044	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	38	0	240037	0	0	0	39	240035	5	1	37	38	0	0	0	5019	5	1	4	17	0	3	3	80064	9	9	0	240000	240000	10	80068	80068	80068	80068	80050
480024	80067	599	1	1	1	0	0	0	64	1	0	0	1	80029	3	0	19	5	0	25	480012	10	240039	240000	10	240000	240000	50	1676441	3603239	0	1	5	80025	80056	80044	4	0	3	26	480010	20	240000	240000	20	240000	720000	80076	80066	1	1	80021	10	9	10	10	80000	80000	0	10	240018	18	41	0	240056	1	0	1	59	240000	5	1	58	0	17	0	0	5019	5	1	3	17	0	3	2	80054	6	6	0	240000	240000	10	80058	80058	80058	80058	80057
480024	80057	599	0	0	0	0	0	0	42	1	0	0	2	80052	0	0	0	14	0	25	480054	10	240046	240000	10	240000	240000	50	3533849	5730686	0	1	5	80048	80067	80067	0	0	3	49	480010	20	240000	240000	20	240000	720000	80053	80063	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	0	0	240037	0	0	0	0	240037	5	1	37	39	0	0	0	5019	5	1	3	17	0	2	3	80167	9	9	1	240000	240000	10	80068	80068	80071	80075	80054
480024	80070	599	1	1	1	1	0	0	64	1	0	1	0	80042	3	0	19	4	0	25	480048	10	240036	240000	10	240000	240000	50	1676441	5534190	0	1	5	80038	80056	80057	5	0	3	38	480010	20	240000	240000	20	240000	720000	80079	80053	1	1	80021	10	9	10	10	80000	80000	1	10	240018	18	0	0	240056	1	0	0	20	240039	0	1	56	43	17	0	0	5019	5	0	2	17	0	3	2	80054	6	6	0	240000	240000	10	80058	80058	80057	80058	80059

LD3 (multiple, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations