Firestorm: LD3 (multiple, post-index, 16B) measurements

Code:

  ld3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 7.006

Integer unit issues: 1.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 3.006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch indir (93)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
66005	29675	239	1	12	11	0	0	1	0	0	393	0	0	0	0	4616	29149	3	0	0	17281	7009	1000	3009	3000	1000	3000	3000	5000	15000	35757	7	23047	29271	29496	3	10	7000	3000	3000	4000	9000	29372	29310	1	1	61001	0	1000	1000	0	3000	0	3004	1	0	3001	5	1	4	0	3	0	13189	9334	6947	3172	5	38	20392	3340	3816	12	44	45	28577	1000	16236	12952	14119	3000	3000	1000	29457	29513	29450	29490	29370
66004	29333	236	0	12	13	0	0	0	0	0	279	88	0	0	0	4572	28970	0	0	0	17188	7000	1000	3009	3000	1000	3000	3000	5000	15000	35704	11	22981	29224	29569	3	10	7000	3000	3000	4000	9000	29293	29511	1	1	61001	56	1000	1000	1	3000	0	3004	1	0	3000	5	0	0	0	0	204	13386	9334	6896	3135	12	57	20400	3288	3814	10	62	54	28626	1000	15851	12796	13697	3000	3000	1000	29498	29413	29451	29479	29451
66004	29500	236	0	9	10	0	0	0	0	0	6	0	0	1	0	4580	28955	0	0	0	16840	7006	1000	3006	3000	1000	3000	3000	5000	15011	35771	2	23046	29142	29353	3	10	7000	3000	3000	4000	9000	29281	29249	1	1	61001	0	1000	1000	0	3000	6	3004	0	0	3007	5	1	1	9	0	0	13214	9394	6932	3140	1	49	20184	3232	3811	13	41	34	28516	1000	16133	13136	14336	3000	3000	1000	29449	29337	29437	29507	29692
66004	29412	228	0	6	11	0	0	0	0	0	12	0	0	0	0	4679	28874	0	0	0	17016	7009	1000	3006	3000	1000	3000	3000	5000	15000	35700	5	23099	29239	29269	3	10	7000	3000	3000	4000	9000	29287	29272	1	1	61001	0	1000	1000	0	3000	9	3000	0	1	3000	5	0	0	6	0	0	13206	9432	7096	3151	6	40	20221	3227	3812	6	40	42	28621	1000	16191	13027	14244	3000	3000	1000	29380	29490	29775	29447	29373
66004	29407	227	0	7	10	0	0	0	0	1	0	0	0	0	1	4706	28910	3	3	0	16970	7007	1000	3009	3000	1000	3000	3000	5000	15000	35599	8	23011	29176	29432	3	10	7000	3000	3000	4000	9000	29316	29147	1	1	61001	0	1000	1000	0	3000	9	3004	0	4	3010	5	1	4	9	0	0	13277	9488	6934	3103	0	40	20020	3275	3808	10	39	41	28641	1000	16214	13155	14525	3000	3000	1000	29429	29377	29348	29443	29375
66004	29440	227	0	12	13	0	0	0	0	0	12	0	0	0	0	4637	28861	0	3	0	17055	7000	1000	3009	3000	1000	3000	3000	5000	15000	35779	5	23029	29223	29373	3	10	7000	3000	3000	4000	9000	29191	29253	1	1	61001	0	1000	1000	0	3000	9	3007	0	0	3000	5	1	1	9	0	0	13090	9480	6957	3197	3	45	20234	3349	3811	13	38	35	28659	1000	16012	12924	14023	3000	3000	1000	29210	29473	29411	29481	29339
66004	29387	237	0	11	9	0	1	1	0	0	306	0	0	0	0	4765	28960	0	3	0	16950	7012	1000	3000	3000	1000	3000	3000	5000	15004	35699	6	23030	29220	29395	3	10	7000	3000	3000	4000	9000	29213	29170	1	1	61001	0	1000	1000	0	3000	0	3000	1	7	3001	5	1	4	6	0	0	13322	9319	6943	3115	7	40	20300	3280	3815	9	36	37	28596	1000	16156	13238	14736	3000	3000	1000	29642	29751	29810	29850	29353
66004	29605	237	0	15	9	0	0	0	0	0	9	0	0	0	0	4625	28938	0	0	0	16976	7000	1000	3000	3000	1000	3000	3000	5000	15000	35832	1	23029	29244	29404	3	10	7000	3000	3000	4000	9000	29263	29209	1	1	61001	0	1000	1000	0	3000	0	3003	1	4	3003	0	0	0	0	0	0	13298	9477	6938	3180	2	42	20103	3326	3809	10	38	39	28700	1000	16000	13172	14564	3000	3000	1000	29290	29354	29316	29337	29261
66004	29428	236	0	11	11	0	0	0	0	0	18	0	0	0	0	4697	29050	0	0	2	16895	7006	1000	3000	3000	1000	3000	3000	5000	15018	35583	1	22981	29198	29386	3	10	7000	3000	3000	4000	9009	29206	29266	1	1	61001	0	1000	1000	0	3000	6	3001	4	10	3004	3	1	3	9	0	0	13170	9453	6965	3165	5	46	19552	3142	3817	15	43	38	28255	1000	15481	12452	13468	3000	3000	1000	28685	28695	28652	28674	28758
66004	28806	222	0	7	16	0	1	0	1	0	6	0	0	0	0	4792	28490	0	0	0	16331	7013	1000	3006	3000	1000	3000	3000	5000	15000	35711	5	23100	28514	28762	3	10	7007	3000	3000	4000	9009	28612	28706	1	1	61001	0	1000	1000	0	3000	6	3000	0	0	3001	0	0	6	0	0	0	13194	9407	6917	3090	6	46	19581	3213	3807	19	49	45	28301	1000	14768	12284	13676	3000	3000	1000	28682	28774	28664	28761	28532

Count: 8

Code:

  ld3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld3 { v0.16b, v1.16b, v2.16b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0009

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	37	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	67	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480205	80104	620	1	0	1	0	0	1	1	0	0	30	0	0	0	25	3	80056	2	7	0	0	25	560130	80100	240040	240000	80100	240000	240000	480499	3547236	5680255	0	80052	80075	80071	18	0	3	53	560100	200	240189	240000	200	320000	720000	80075	80071	1	1	80201	100	99	100	100	80000	80000	0	100	240016	16	44	0	240057	0	1	0	57	240000	5	1	56	45	15	0	0	5109	1	17	2	3	80068	0	80000	13	13	240000	240000	80100	80101	80263	80072	80072	80072
480204	80050	621	1	0	0	1	0	0	0	0	0	64	0	0	0	6	3	80055	3	7	1	17	25	560132	80101	240036	240000	80164	240000	240000	480495	3547236	5749842	0	80056	80071	80265	22	0	3	32	560100	200	240000	240000	200	320000	720000	80071	80070	1	1	80201	100	99	100	100	80000	80000	0	100	240015	15	43	0	240056	0	0	1	61	240000	5	1	15	0	15	2	0	5111	1	17	2	2	80047	0	80000	13	13	240000	240000	80100	80090	80073	80051	80072	80072
480204	80071	621	1	0	1	1	1	0	0	1	0	63	0	0	0	0	2	80056	3	7	0	1	25	560163	80100	240029	240000	80100	240210	240000	480497	2799892	5048306	0	80056	80075	80071	0	0	3	58	560100	200	240000	240000	200	320000	720567	80071	80074	1	1	80201	100	99	100	100	80000	80000	0	100	240015	15	43	0	240056	1	0	0	21	240041	5	1	56	43	15	0	0	5109	1	17	2	1	80072	0	80000	14	13	240000	240000	80100	80843	80064	80271	80286	80072
480204	80073	621	1	1	0	0	0	0	0	0	0	250	0	0	0	1	3	80060	2	7	7	16	25	560130	80100	240027	240000	80100	240000	240000	480498	3547236	5726207	0	80056	80071	80050	18	0	3	54	560526	200	240000	240000	200	320000	720000	80075	80050	1	1	80201	100	99	100	100	80000	80000	1	100	240015	15	43	0	240056	0	0	1	57	240000	5	1	15	0	15	0	0	5111	2	16	2	1	80211	0	80000	0	13	240000	240000	80100	80063	80076	80054	80072	80079
480204	80071	621	1	1	0	0	0	0	0	0	0	64	0	1	0	1	4	80056	3	7	7	17	25	560141	80100	240029	240000	80100	240000	240000	480497	3491624	4862056	1	80052	80071	80075	0	0	3	32	560100	200	240000	240189	200	320000	720000	80071	80075	1	1	80201	100	99	100	100	80000	80000	1	100	240015	16	43	0	240056	1	0	1	61	240040	5	1	56	43	15	0	0	5109	1	17	2	2	80068	0	80000	13	0	240000	240000	80100	80075	80051	80080	80051	80072
480204	80071	620	1	1	1	0	0	0	0	0	0	86	0	1	0	20	3	80035	2	7	0	17	25	560144	80100	240027	240000	80100	240000	240000	560464	3520518	5688606	1	80052	80071	80075	28	0	3	54	560100	200	240000	240000	200	320000	720567	80071	80075	1	1	80201	100	99	100	100	80000	80000	1	100	240015	16	43	0	240015	0	0	0	62	240000	5	1	15	43	15	1	0	5151	1	17	2	1	80068	0	80000	13	13	240000	240000	80100	80072	80072	80078	80079	80075
480204	80076	645	1	0	0	0	1	0	0	0	0	64	0	0	0	0	3	80059	2	7	7	88	25	560144	80100	240041	240000	80100	240000	240000	480496	3506232	5674890	0	80052	80075	80070	18	0	3	53	560100	200	240000	240189	200	320000	720000	80071	80075	1	1	80201	100	99	100	100	80000	80000	0	100	240016	15	0	0	240055	0	0	1	18	240040	5	1	55	43	15	0	0	5111	1	17	2	1	80068	0	80001	13	0	240000	240000	80100	80268	80072	80073	80072	80072
480204	80050	620	1	1	0	0	0	0	0	0	0	64	0	0	0	14	1	80056	3	7	7	17	25	560126	80100	240168	240000	80100	240000	240000	480497	3531921	5643953	0	80056	80071	80075	0	0	3	57	560100	200	240000	240000	200	320000	720000	80071	80264	1	1	80201	100	99	100	100	80000	80000	1	100	240015	15	43	0	240056	0	0	1	62	240041	5	1	56	43	15	2	0	5109	2	16	2	1	80072	0	80000	13	13	240000	240000	80100	80091	80084	80081	80075	80051
480204	80071	620	1	1	0	1	0	0	0	0	1	64	0	0	0	0	3	80056	2	7	7	17	25	560129	80100	240027	240000	80100	240000	240000	480496	3521480	3999042	0	80052	80071	80050	0	66	3	54	560100	200	240000	240000	200	320000	720000	80075	80071	1	1	80201	100	99	100	100	80000	80000	0	100	240015	18	44	0	240056	0	0	1	59	240041	5	1	56	43	15	1	0	5109	2	16	1	2	80072	0	80000	13	13	240000	240000	80100	80075	80054	80072	80074	80075
480204	80071	620	1	0	1	0	1	0	0	0	0	63	0	0	0	2	3	80056	0	7	7	17	25	560143	80100	240025	240000	80100	240000	240000	560464	3520229	5590654	1	80052	80071	80075	18	0	3	177	560100	200	240000	240000	200	320000	720000	80071	80071	1	1	80201	100	99	100	100	80000	80000	1	100	240015	15	43	57	240055	1	0	1	59	240040	5	1	55	43	15	1	0	5109	2	16	1	2	80080	0	80001	13	13	240000	240000	80100	80075	80076	80072	80072	80076

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	18	19	1e	1f	22	24	37	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	67	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480025	80076	620	1	1	0	0	0	0	0	62	0	0	0	3	0	80035	3	18	0	14	25	560041	80010	240039	240000	80010	240000	240000	480047	3564406	5752851	0	0	80047	80066	80067	14	0	3	50	560010	20	240000	240000	20	320000	720000	80071	80066	1	1	80021	10	9	10	10	80000	80000	1	10	240016	15	42	0	240052	0	1	1	58	240040	5	1	54	42	15	1	0	5019	9	17	6	9	80081	1	80000	10	6	240000	240000	80010	80061	80063	80063	80046	80057
480024	80062	620	1	0	0	0	0	0	0	45	0	0	0	0	2	80051	2	17	17	0	25	560021	80010	240040	240000	80010	240000	240000	480047	2027042	5545824	0	0	80047	80062	80066	0	0	23	54	560010	20	240000	240000	20	320000	720000	80062	80056	1	1	80021	10	9	10	10	80000	80000	0	10	240016	0	35	0	240000	0	0	0	33	240000	5	0	40	0	0	0	0	5019	9	16	9	10	80064	0	80434	6	0	240000	240000	80010	80068	80057	80063	80065	80046
480024	80237	621	0	0	0	0	0	0	0	50	0	0	0	0	2	80051	2	18	17	9	25	560045	80010	240039	240000	80010	240000	240000	480047	3511704	5537472	1	0	80043	80066	80062	9	0	3	49	560010	20	240000	240000	20	320000	720000	80062	80062	1	1	80021	10	9	10	10	80000	80000	0	10	240000	16	0	0	240055	0	1	0	43	240040	5	0	33	43	15	0	0	5019	9	16	5	9	80059	0	80000	10	10	240000	240000	80010	80063	80068	80057	80063	80063
480024	80071	620	0	0	0	0	0	0	0	45	0	0	0	0	2	80051	2	17	0	9	25	560049	80010	240044	240000	80010	240000	240000	480047	3533746	5641659	1	0	80043	80062	80062	13	0	3	45	560010	20	240000	240000	20	320000	720000	80067	80056	1	1	80021	10	9	10	10	80000	80000	1	10	240000	0	35	0	240038	0	0	0	58	240040	6	1	32	43	0	0	0	5019	9	16	9	9	80059	0	80000	10	6	240000	240000	80010	80063	80064	80067	80063	80063
480024	80056	620	0	0	0	0	0	0	0	45	0	0	0	1	2	80047	1	15	18	13	25	560038	80010	240023	240000	80010	240000	240000	480047	3506714	5637735	0	0	80048	80068	80066	0	0	3	32	560010	20	240000	240000	20	320000	720000	80050	80071	1	1	80021	10	9	10	10	80000	80000	1	10	240016	16	42	0	240054	0	2	0	58	240040	5	1	55	42	15	0	0	5019	9	17	10	11	80064	0	80000	9	9	240000	240000	80010	80068	80068	80068	80067	80068
480024	80068	621	1	0	0	0	0	0	0	6	0	0	0	20	2	80030	2	17	18	9	25	560019	80010	240028	240000	80010	240000	240000	480048	3536266	5700761	0	0	80048	80062	80056	0	0	3	45	560010	20	240000	240000	20	320000	720000	80056	80057	1	1	80021	10	9	10	10	80000	80000	1	10	240000	0	35	0	240040	0	0	0	0	240040	5	1	33	43	0	0	0	5019	9	16	9	9	80059	0	80000	10	10	240000	240000	80010	80063	80063	80046	80057	80050
480024	80069	621	1	0	0	0	0	0	0	45	0	0	0	0	3	80047	2	0	17	9	25	560050	80010	240039	240000	80010	240000	240000	480047	3533999	5627593	0	0	80055	80103	80071	16	0	3	38	560010	20	240000	240000	20	320000	720000	80056	80062	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	0	0	240033	0	0	0	0	240033	0	1	0	43	0	0	0	5019	11	16	9	8	80059	0	80000	9	6	240000	240000	80010	80068	80063	80063	80067	80063
480024	80062	620	0	0	0	0	0	0	0	46	0	0	0	5	0	80045	0	18	17	9	25	560052	80010	240000	240000	80010	240000	240000	480047	3496143	5574080	1	0	80043	80062	80062	11	0	3	50	560010	20	240000	240000	20	320000	720000	80062	80066	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	35	0	240054	0	0	0	39	240000	0	1	54	43	0	0	0	5019	9	17	8	8	80042	0	80000	10	9	240000	240000	80010	80057	80072	80046	80057	80067
480024	80062	621	0	0	0	0	0	0	0	38	0	0	0	0	2	80047	2	0	0	3	25	560051	80010	240001	240000	80010	240000	240000	480048	3520478	5764072	0	0	80045	80063	80061	9	0	3	48	560010	20	240000	240000	20	320000	720000	80045	80060	1	1	80021	10	9	10	10	80000	80000	1	10	240000	0	0	0	240000	0	0	0	18	240000	5	1	33	44	0	0	0	5019	8	16	5	9	80059	0	80000	10	6	240000	240000	80010	80063	80063	80068	80063	80063
480024	80064	621	0	1	0	0	0	0	0	50	0	0	0	9	2	80051	3	18	0	14	25	560045	80010	240045	240000	80010	240000	240000	480047	3469254	5560261	0	0	80051	80066	80054	0	0	3	55	560010	20	240000	240000	20	320000	720000	80067	80067	1	1	80021	10	9	10	10	80000	80000	0	10	240015	16	0	0	240015	0	0	1	67	240039	0	1	15	0	15	0	0	5019	8	17	9	9	80064	0	80000	9	9	240000	240000	80010	80068	80068	80068	80072	80068

LD3 (multiple, post-index, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations