Firestorm: LD3 (multiple, post-index, 2D) measurements

Code:

  ld3 { v0.2d, v1.2d, v2.2d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 7.006

Integer unit issues: 1.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 3.006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	0e	0f	1e	22	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
66005	29420	230	33	0	1	23	0	0	9	0	4569	28960	0	3	3	17031	7009	1000	3009	3000	1000	3000	3000	5000	15013	35729	8	23032	29181	29401	3	10	7000	3000	3000	4000	9000	29211	29301	1	1	61001	1000	1000	3000	9	3004	61	4	3004	5	1	4	9	13038	9403	6849	3131	14	70	20153	3213	3822	17	74	74	28576	1000	16439	13113	14619	3000	3000	1000	29385	29399	29344	29437	29501
66004	29534	228	22	0	0	23	0	0	9	0	4715	29306	3	3	3	17194	7009	1000	3009	3000	1000	3000	3000	5000	15033	35749	0	23077	29483	30064	3	10	7000	3000	3000	4000	9000	29224	29256	1	1	61001	1000	1000	3000	9	3004	62	10	3001	5	1	4	9	12938	9187	6818	3068	14	75	20278	3086	3819	22	73	65	28412	1000	16244	13277	14428	3000	3000	1000	29278	29352	29348	29375	29484
66004	29314	219	29	0	1	21	1	1	18	0	4581	28839	0	3	3	16937	7009	1000	3009	3000	1000	3000	3000	5000	15000	35741	4	22965	29100	29279	3	10	7000	3000	3000	4000	9000	29276	29153	1	1	61001	1000	1000	3000	9	3004	58	7	3004	5	1	4	9	12935	9274	6846	3065	12	60	20170	3130	3823	17	63	64	28424	1000	16292	13408	14430	3000	3000	1000	29388	29400	29376	29321	29398
66004	29264	219	23	0	0	23	0	0	9	0	4540	28900	0	3	3	17004	7012	1000	3009	3000	1000	3000	3000	5000	15001	35733	0	23015	29131	29326	3	10	7000	3000	3000	4000	9000	29151	29196	1	1	61001	1000	1000	3000	9	3004	33	85	3004	5	1	4	9	12992	9068	6866	3050	13	68	20116	3059	3824	22	68	64	28483	1000	16460	13182	14552	3000	3000	1000	29406	29407	29385	29234	29543
66004	29364	220	29	0	0	24	0	0	12	0	4573	28814	0	3	3	17035	7009	1000	3009	3000	1000	3000	3000	5000	15001	35729	2	23038	29221	29317	3	10	7000	3000	3000	4000	9000	29219	29222	1	1	61001	1000	1000	3000	9	3004	0	1263	3004	5	1	4	9	13297	9209	6827	3043	11	72	20103	3204	3821	27	64	68	28504	1000	16245	13401	14508	3000	3000	1000	29433	29366	29356	29444	29368
66004	29427	220	23	0	0	27	0	0	18	0	4579	28890	0	3	3	16902	7009	1000	3009	3000	1000	3000	3000	5000	15000	35724	0	22987	29088	29371	3	10	7000	3000	3000	4000	9000	29368	29204	1	1	61001	1000	1000	3000	9	3007	0	184	3004	5	1	4	9	12896	9287	6801	3059	12	67	20237	3195	3823	23	64	68	28527	1000	16455	13468	14509	3000	3000	1000	29356	29313	29450	29427	29465
66004	29510	220	27	0	0	30	0	0	6	0	4555	28931	0	0	0	16964	7006	1000	3006	3000	1000	3000	3000	5000	15000	35708	4	22994	29242	29365	3	10	7000	3000	3000	4000	9000	29387	29236	1	1	61001	1000	1000	3000	6	3001	0	178	3001	5	1	1	6	13164	9243	6842	3184	11	67	20202	3073	3824	21	63	59	28552	1000	16546	13256	14484	3000	3000	1000	29417	29393	29304	29237	29323
66004	29402	220	24	0	0	28	0	0	6	0	4708	28884	0	0	0	17028	7006	1000	3006	3000	1000	3000	3000	5000	15009	35709	4	23040	29147	29435	3	10	7000	3000	3000	4000	9000	29276	29290	1	1	61001	1000	1000	3000	6	3001	0	1	3001	5	1	1	6	12958	9052	6803	3076	8	66	20227	3111	3823	22	65	65	28454	1000	16519	13318	14427	3000	3000	1000	29362	29463	29378	29381	29413
66004	29336	220	27	0	1	26	0	0	6	0	4544	28912	0	0	0	16984	7007	1000	3006	3000	1000	3000	3000	5000	15000	35682	0	23045	29152	29332	3	10	7000	3000	3000	4000	9000	29227	29226	1	1	61001	1000	1000	3000	6	3001	0	13	3001	5	1	1	6	12924	9251	6857	3091	14	66	20260	3210	3823	16	57	68	28434	1000	16444	13146	14752	3000	3000	1000	29358	29414	29430	29361	29347
66004	29379	219	25	0	0	22	0	0	6	0	4709	28905	0	0	0	16947	7006	1000	3006	3000	1000	3000	3000	5000	15006	35710	5	23010	29118	29421	3	10	7000	3000	3000	4000	9000	29215	29244	1	1	61001	1000	1000	3000	6	3001	0	1	3001	5	1	1	6	12902	9117	6840	3091	14	63	20258	3107	3819	16	69	66	28514	1000	16428	13471	14519	3000	3000	1000	29380	29407	29420	29402	29407

Count: 8

Code:

  ld3 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld3 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld3 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld3 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld3 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld3 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld3 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld3 { v0.2d, v1.2d, v2.2d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	37	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	67	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480205	80086	643	1	0	0	0	0	0	0	0	0	72	0	0	18	1	80073	2	18	18	13	25	560128	80100	240047	240000	80100	240000	240000	480492	3519408	5713174	0	80046	80063	80063	9	0	3	27	560100	200	240000	240000	200	320000	720000	80070	80056	1	1	80201	100	99	0	100	100	80000	80000	0	100	240015	16	42	0	240055	0	104	2	1986	240039	5	1	38	0	0	0	5109	10	16	8	8	80061	0	80000	0	7	240000	240000	80100	80046	80047	80063	80046	80393
480204	80071	643	0	0	0	0	0	0	0	0	0	45	0	0	1	0	80050	2	17	0	15	25	560107	80103	240041	240000	80100	240000	240000	480498	3526370	5558677	0	80049	80062	80062	10	0	3	45	560100	200	240000	240000	200	320000	720000	80203	80057	1	1	80201	100	99	0	100	100	80000	80000	1	100	240000	0	35	0	240040	0	146	0	33	240040	5	1	33	35	0	0	5109	8	16	8	7	80042	0	80000	6	7	240000	240000	80100	80063	80050	80064	80047	80057
480204	80056	643	0	0	0	0	0	0	0	0	0	45	0	0	2	0	80047	2	17	17	9	25	560140	80101	240041	240000	80100	240000	240000	480497	3533501	5589725	0	80043	80072	80056	0	0	3	45	560100	200	240000	240000	200	320000	720000	80068	80062	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	43	0	240040	0	52	0	32	240000	0	1	40	44	0	0	5109	7	17	8	4	80044	0	80000	10	6	240000	240000	80100	80063	80063	80064	80057	80058
480204	80066	643	0	0	0	0	0	0	0	0	0	45	0	0	2	2	80048	2	17	17	11	25	560141	80103	240039	240000	80100	240000	240000	480496	3525215	5764153	0	80044	80068	80068	0	0	3	46	560100	200	240000	240000	200	320000	720000	80060	80045	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	43	0	240000	0	97	0	39	240040	5	1	33	43	0	0	5109	9	16	8	8	80059	1	80000	10	6	240000	240000	80100	80083	80064	80064	80063	80406
480204	80047	643	0	0	0	0	0	0	0	0	0	45	0	0	10	2	80047	2	17	17	9	25	560140	80100	240039	240000	80100	240000	240000	480497	3520381	5719238	0	80043	80062	80065	0	0	3	42	560100	200	240000	240000	200	320000	720000	80046	80062	2	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	35	0	240040	0	0	0	36	240040	5	1	33	43	0	0	5109	8	17	8	8	80054	0	80000	10	6	240000	240000	80100	80063	80060	80063	80067	80057
480204	80062	643	0	0	0	0	0	0	0	0	0	48	88	0	2	2	80030	2	17	17	18	25	560141	80100	240043	240000	80100	240000	240000	480497	3520329	5764144	0	80043	80057	80056	0	0	3	47	560100	200	240000	240000	200	320000	720000	80063	80048	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	35	0	240040	0	26	0	39	240040	5	1	33	43	0	0	5109	7	17	9	8	80059	0	80000	10	6	240000	240000	80100	80057	80063	80254	80065	80414
480204	80062	643	0	0	0	0	0	0	0	0	0	48	0	0	2	2	80049	2	0	17	9	25	560139	80101	240168	240000	80100	240000	240000	480498	3520426	3866645	0	80043	80062	80066	13	0	3	38	560100	200	240000	240000	200	320000	720000	80045	80056	1	1	80201	100	99	0	100	100	80000	80000	0	100	240130	0	0	57	240170	0	0	0	43	240000	5	1	0	44	0	0	5124	9	17	7	8	80053	0	80061	10	10	240000	240000	80100	80254	80064	80259	80254	83724
480204	80262	646	0	1	0	0	0	0	0	2	2	177	88	0	0	2	80429	2	17	17	77	61	560787	80224	240301	240130	80162	240369	240202	481198	3389223	4449255	2	82903	83334	83329	883	0	3	164	560526	200	240000	240186	200	320244	721134	80433	80429	2	1	80201	100	99	0	100	100	80000	80000	0	100	240130	0	0	57	240302	0	87	4	3000	240300	6	1	30	43	0	0	5151	9	35	8	8	80385	0	80000	12	0	240000	240000	80100	80063	80064	80062	80046	80304
480204	80066	643	0	0	0	0	0	0	1	0	0	45	0	0	5	2	80047	2	17	17	10	62	560141	80100	240170	240000	80100	240000	240178	480497	3520280	5585138	0	80043	80067	80066	53	0	3	31	560100	200	240000	240000	200	320000	720000	80045	80254	1	1	80201	100	99	0	100	100	80000	80000	1	100	240000	0	35	0	240130	0	7	0	41	240000	0	1	33	43	0	0	5109	10	17	8	4	80059	0	80062	10	7	240000	240000	80100	80046	80067	80050	80254	80046
480204	80061	643	0	0	0	0	0	0	0	1	0	45	0	0	2	2	80248	0	12	17	9	25	560460	80100	240039	240000	80164	240000	240000	480498	2881964	5674634	0	80210	80253	80063	13	0	24	45	560100	200	240000	240000	200	320000	720000	80067	80070	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	35	0	240040	0	0	0	61	240040	0	1	35	44	0	0	5109	8	16	8	8	80059	0	80000	10	6	240000	240000	80100	80067	80068	80063	80063	80240

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	37	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	67	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	d9	da	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480025	80068	620	0	0	0	0	0	0	0	0	46	0	0	0	0	0	80051	2	0	7	15	25	560049	80010	240041	240000	80010	240000	240000	480048	3476132	3867001	0	0	0	80051	80045	80066	13	0	3	52	560010	20	240000	240000	20	320000	720000	80069	80062	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	43	0	240041	1	0	0	240041	5	1	42	44	0	0	5019	3	16	0	2	3	3	80063	80000	14	10	240000	240000	80010	80069	80067	80067	80067	80046
480024	80062	620	0	0	0	0	0	0	0	0	46	0	0	0	7	2	80051	2	1	7	14	25	560049	80010	240040	240000	80010	240000	240000	480047	3491437	5683236	0	0	0	80047	80070	80067	37	0	3	51	560010	20	240000	240000	20	320000	720000	80062	80062	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	43	0	240041	0	0	0	240041	0	1	40	0	0	0	5019	2	16	0	1	3	3	80067	80000	0	10	240000	240000	80010	80047	80067	80067	80071	80068
480024	80066	620	0	0	0	0	0	0	0	0	46	0	0	0	1	2	80055	2	7	7	16	25	560051	80010	240040	240000	80010	240000	240000	480047	3491235	5616135	0	0	0	80047	80066	80070	13	0	3	53	560010	20	240000	240000	20	320000	720000	80045	80062	1	1	80021	10	9	0	10	10	80000	80000	1	10	240000	0	43	0	240040	0	0	41	240171	5	0	40	43	0	0	5019	3	16	0	0	4	3	80063	80000	14	0	240000	240000	80010	80071	80067	80067	80067	80046
480024	80065	621	0	0	0	0	1	1	0	0	0	0	0	0	2	2	80050	2	7	7	14	25	560049	80010	240043	240000	80010	240000	240000	480047	3542695	5751420	0	0	0	80047	80066	80066	17	0	3	49	560010	20	240000	240000	20	320000	720000	80066	80045	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	0	0	240040	0	0	44	240040	5	1	40	0	0	0	5019	3	16	0	0	3	3	80042	80000	14	10	240000	240000	80010	80067	80067	80067	80067	80155
480024	80066	620	0	0	0	0	0	0	0	0	46	0	0	0	1	2	80050	2	7	0	14	25	560051	80010	240018	240000	80010	240000	240000	480047	3539043	5753731	0	0	0	80051	80066	80066	13	0	3	54	560010	20	240000	240000	20	320000	720000	80066	80066	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	44	0	240041	0	0	41	240000	5	1	0	44	0	0	5019	3	17	0	0	3	3	80059	80000	14	0	240000	240000	80010	80067	80067	80063	80067	80066
480024	80071	621	0	0	0	0	0	0	0	0	0	0	0	0	2	2	80051	2	7	1	13	25	560049	80010	240039	240000	80010	240000	240000	480047	3491235	3866849	0	0	0	80026	80066	80066	17	0	3	50	560010	20	240000	240000	20	320000	720000	80062	80045	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	44	0	240042	0	0	44	240041	5	1	40	45	0	0	5019	3	17	0	0	3	3	80063	80000	14	10	240000	240000	80010	80046	80067	80064	80067	80067
480024	80066	620	0	0	0	0	0	0	0	0	46	0	0	0	2	2	80050	2	7	7	14	25	560052	80010	240040	240000	80010	240000	240000	480046	3491235	5709577	0	0	0	80047	80066	80066	0	0	3	49	560010	20	240000	240000	20	320000	720000	80066	80062	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	43	0	240041	1	0	41	240041	5	1	41	44	0	1	5019	3	16	0	0	3	2	80063	80000	14	14	240000	240000	80010	80067	80067	80067	80071	80067
480024	80066	620	0	0	0	0	0	0	0	0	46	0	0	0	0	2	80053	2	7	0	0	25	560049	80010	240039	240000	80010	240000	240000	480046	1917848	5703189	0	0	0	80047	80066	80066	20	0	3	49	560010	20	240000	240000	20	320000	720000	80066	80066	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	43	0	240041	0	0	857	240041	5	1	41	44	0	0	5019	2	16	0	0	7	14	82739	80000	14	10	240000	240000	80010	80067	80071	80066	80067	80067
480024	80045	620	0	0	0	0	0	0	0	0	58	0	0	0	2	2	80051	2	7	7	14	25	560034	80010	240039	240000	80010	240000	240000	480049	1917848	5753998	0	0	0	80048	80076	80065	13	0	3	49	560010	20	240000	240000	20	320000	720000	80066	80066	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	0	57	240041	0	0	41	240041	5	1	41	44	0	0	5019	3	16	0	0	3	3	80063	80000	14	10	240000	240000	80010	80067	80067	80072	80067	80066
480024	80045	621	0	0	0	0	0	0	0	0	0	0	0	0	6	2	80053	2	1	7	13	25	560049	80010	240040	240000	80010	240000	240000	480048	3491235	3866637	0	0	0	80047	80066	80062	13	0	3	27	560010	20	240000	240000	20	320000	720567	80070	80070	1	1	80022	10	9	0	10	10	80000	80000	0	10	240000	0	43	0	240041	1	0	41	240041	6	0	41	44	0	0	5019	3	16	0	0	3	3	80042	80000	14	14	240000	240000	80010	80067	80071	80067	80067	80067

LD3 (multiple, post-index, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations