Firestorm: LD3 (multiple, post-index, 2S) measurements

Code:

  ld3 { v0.2s, v1.2s, v2.2s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 6.006

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 3.006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	c3	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
65005	29432	226	16	0	0	15	0	0	0	0	0	4	0	0	4650	28882	0	0	17037	6006	1000	3006	2000	1000	3000	2000	5000	10000	35629	4	0	0	22911	29170	29397	3	10	6000	2000	3000	3000	6000	29208	29220	1	1	61001	1000	1000	0	2000	0	4	2002	0	0	0	0	2000	4	0	6	0	0	0	13103	9374	6874	3182	8	45	20185	3242	3814	11	43	43	28470	1000	16182	13302	14329	2000	3000	1000	29288	29351	29263	29275	29243
65004	29252	227	19	0	0	20	0	0	0	0	0	8	0	1	4612	28874	0	0	16984	6009	1000	3009	2000	1000	3000	2000	5000	10003	35724	3	0	0	22943	29037	29470	3	10	6000	2000	3000	3000	6000	29282	29185	1	1	61001	1000	1000	0	2000	0	6	2000	0	0	0	0	2000	0	0	4	0	0	0	13119	9496	6920	3109	9	43	20063	3250	3812	17	39	41	28501	1000	16096	13142	14264	2000	3000	1000	29366	29226	29311	29231	29396
65004	29461	227	15	0	0	20	0	0	0	0	0	0	0	0	4693	28805	0	0	16870	6006	1000	3006	2000	1000	3000	2000	5000	10000	35625	6	0	0	22867	29242	29323	3	10	6000	2000	3000	3000	6000	29296	29263	1	1	61001	1000	1000	3	2000	0	6	2000	0	0	0	0	2000	4	0	6	0	0	0	13124	9327	6864	3114	5	46	20361	3135	3815	12	42	42	28438	1000	16011	13186	14510	2000	3000	1000	29358	29346	29253	29323	29312
65004	29264	227	13	0	0	21	0	0	0	0	0	8	0	0	4593	28885	0	0	17069	6000	1000	3006	2000	1000	3000	2000	5000	10000	35599	0	0	0	22960	29135	29337	3	10	6000	2000	3000	3000	6000	29153	29293	1	1	61001	1000	1000	0	2000	0	4	2004	0	0	0	0	2002	4	0	4	0	0	0	13167	9354	6921	3145	7	40	20230	3237	3815	17	47	45	28443	1000	16327	13211	14384	2000	3000	1000	29494	29351	29392	29331	29328
65004	29265	227	23	0	0	16	0	0	0	0	0	21	0	1	4663	28882	0	0	16853	6000	1000	3000	2000	1000	3000	2000	5000	10000	35687	2	0	5	22866	29096	29284	8	10	6000	2000	3000	3000	6000	29113	29172	1	1	61001	1000	1000	0	2000	0	4	2001	0	0	11	0	2000	6	0	6	0	0	0	12867	9417	6932	3159	7	43	20127	3230	3816	10	42	40	28515	1000	16404	13129	14162	2000	3000	1000	29211	29240	29200	29326	29300
65004	29175	228	15	0	0	14	0	0	0	0	0	12	0	0	4608	28846	0	0	16892	6006	1000	3006	2000	1000	3000	2000	5000	10000	35734	0	0	0	22989	29174	29339	3	10	6000	2000	3000	3000	6000	29250	29146	1	1	61001	1000	1000	1	2000	0	6	2000	0	1	0	0	2000	4	0	4	0	0	0	13146	9486	6897	3074	4	42	20212	3223	3814	15	41	39	28560	1000	16032	13241	14292	2000	3000	1000	29298	29358	29342	29275	29311
65004	29380	226	16	1	0	18	0	0	1	0	0	0	0	0	4640	28961	0	0	17073	6006	1000	3006	2000	1000	3000	2000	5000	10000	35613	0	0	0	22897	29053	29263	3	10	6000	2000	3000	3000	6000	29136	29178	1	1	61001	1000	1000	1	2000	0	0	2000	0	1	0	0	2000	4	0	6	0	0	0	12963	9301	6938	3090	10	40	20171	3215	3816	14	37	38	28519	1000	15984	13497	14432	2000	3000	1000	29160	29535	29284	29339	29286
65004	29297	227	21	0	0	20	0	0	0	0	0	5	88	0	4645	28819	0	0	17002	6006	1000	3012	2000	1000	3000	2000	5005	10076	35668	0	0	0	22930	29170	29324	3	10	6000	2000	3000	3000	6000	29237	29294	1	1	61001	1000	1000	1	2000	0	4	2000	0	0	0	0	2000	0	2	4	0	0	0	13140	9474	6927	3094	7	39	20204	3172	3812	14	46	44	28429	1000	15930	13511	14572	2000	3000	1000	29209	29393	29336	29304	29301
65004	29308	227	17	0	0	14	0	0	0	0	0	3	0	0	4531	28848	0	0	17028	6006	1000	3009	2000	1000	3000	2000	5000	10000	35728	0	0	0	22928	29151	29348	3	10	6000	2000	3000	3000	6000	29333	29235	1	1	61001	1000	1000	1	2000	0	6	2000	0	0	0	0	2000	4	0	4	0	0	0	13105	9542	6936	3176	9	45	20337	3221	3816	12	40	41	28611	1000	16165	13384	14272	2000	3000	1000	29616	29434	29228	29300	29220
65004	29287	227	13	0	0	13	0	0	0	0	2	3	0	0	4616	28814	0	0	16967	6012	1000	3000	2000	1000	3000	2000	5000	10000	35722	2	0	0	22902	29106	29327	3	10	6000	2000	3000	3000	6000	29228	29210	1	1	61001	1000	1000	0	2000	0	6	2000	0	0	0	0	2004	0	0	6	0	0	0	13324	9372	6875	3066	10	45	20330	3179	3815	15	35	42	28525	1000	16116	13289	14442	2000	3000	1000	29497	29568	29338	29453	29329

Count: 8

Code:

  ld3 { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld3 { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld3 { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld3 { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld3 { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld3 { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld3 { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld3 { v0.2s, v1.2s, v2.2s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	18	19	1e	1f	23	24	3a	3f	43	46	49	4f	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	80071	620	0	1	0	1	0	0	36	0	0	0	0	80027	2	12	0	0	0	25	480154	80100	240057	160000	80100	240000	160000	480499	960328	3121763	80023	80042	80042	0	0	3	24	480100	200	160000	240000	200	240000	480000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160000	27	160030	0	22	160028	6	1	0	33	0	5109	1	17	1	1	80039	1	80000	10	10	160000	240000	80100	80043	80043	80043	80043	80043
400204	80042	620	0	0	0	0	0	0	51	0	0	0	1	80027	2	12	12	0	0	25	480154	80100	240054	160000	80100	240000	160000	480499	960331	3121161	80023	80042	80042	0	0	3	24	480100	200	160000	240000	200	240000	480000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160000	25	160030	0	21	160030	6	1	22	33	0	5109	1	17	1	1	80039	1	80000	10	12	160000	240000	80100	80043	80043	80043	80043	80043
400204	80042	620	0	0	0	0	0	0	36	0	0	0	0	80027	2	12	12	0	0	25	480154	80100	240044	160000	80100	240000	160000	480499	960364	3121181	80023	80042	80042	0	0	3	24	480100	200	160000	240000	200	240000	480000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160000	25	160030	0	24	160030	6	1	22	33	0	5109	1	17	1	1	80039	0	80163	10	14	160000	240000	80100	80043	80043	80043	80043	80043
400204	80042	620	0	0	0	0	0	0	36	0	0	0	1	80027	0	12	12	0	0	25	480154	80100	240054	160000	80100	240000	160000	480499	960330	3121073	80023	80042	80042	0	0	3	24	480100	200	160000	240000	200	240000	480000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160000	25	160029	0	30	160030	6	1	22	33	0	5109	1	17	1	1	80039	0	80000	10	0	160000	240000	80100	80043	80043	80043	80043	80043
400204	80042	620	0	0	0	3	0	0	39	0	0	0	1	80027	2	12	12	0	0	25	480154	80100	240054	160000	80100	240000	160000	480499	960330	3121155	80023	80042	80042	0	0	3	24	480100	200	160000	240000	200	240000	480000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160000	33	160030	1	22	160029	0	1	20	39	0	5109	1	17	1	1	80039	0	80000	10	0	160000	240000	80100	80043	80043	80043	80043	80043
400204	80042	621	0	0	0	0	0	0	48	0	0	0	1	80027	2	12	12	0	0	25	480154	80100	240055	160000	80100	240000	160000	480499	960330	3121073	80023	80042	80042	0	0	3	24	480100	200	160000	240000	200	240000	480000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160000	37	160030	0	33	160021	6	1	22	33	0	5109	1	17	1	1	80039	1	80000	10	10	160000	240000	80100	80043	80043	80043	80043	80043
400204	80042	621	0	0	0	0	0	0	36	0	0	0	1	80027	2	12	0	0	0	25	480154	80100	240054	160000	80100	240000	160000	480499	960338	3121088	80023	80042	80042	0	0	3	24	480100	200	160000	240000	200	240000	480000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160000	33	160030	0	33	160022	6	1	22	33	0	5109	1	17	1	1	80039	0	80000	10	10	160000	240000	80100	80043	80043	80043	80043	80043
400204	80042	620	0	0	0	0	0	0	27	0	0	0	1	80027	2	12	12	0	0	25	480154	80100	240055	160000	80100	240000	160000	480499	960331	3121104	80023	80042	80042	0	0	3	24	480100	200	160000	240000	200	240000	480000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160000	25	160030	0	21	160000	6	1	30	33	0	5109	1	17	1	1	80039	1	80000	10	11	160000	240000	80100	80043	80043	80043	80043	80043
400204	80042	621	0	0	0	0	0	0	36	0	0	0	1	80027	2	12	12	0	0	25	480155	80100	240054	160000	80100	240000	160000	480499	960338	3121051	80115	80156	80042	0	0	17	24	480100	200	160108	240000	200	240000	480324	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160000	33	160022	0	30	160030	6	1	21	33	0	5109	1	17	1	1	80039	1	80000	10	0	160000	240000	80100	80043	80043	80043	80043	80043
400204	80042	621	0	0	0	0	0	0	36	0	0	0	1	80027	2	12	12	0	0	25	480154	80100	240055	160000	80100	240000	160000	480499	960331	3119994	80023	80042	80042	0	0	3	24	480100	200	160000	240000	200	240000	480000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	160030	0	30	160030	6	1	22	25	0	5109	1	17	1	1	80039	1	80000	10	10	160000	240000	80100	80043	80043	80043	80043	80043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	80058	620	0	0	0	1	1	0	0	43	0	1	0	0	80027	2	0	12	0	25	480073	80010	240063	160000	80010	240000	160000	480049	960650	3121768	0	80023	0	80042	80042	0	3	24	480010	20	160000	240000	20	240000	480000	80042	80042	1	1	80021	10	9	10	10	80000	80000	1	10	160000	0	33	160037	0	2	0	30	160037	0	1	29	43	11	0	0	5019	4	17	3	4	80039	0	80000	13	13	160000	240000	80010	80043	80043	80043	80043	80043
400024	80042	620	1	0	0	1	0	0	0	67	0	0	0	2	80027	2	6	1	3	25	480085	80010	240075	160000	80010	240000	160000	480048	961273	3124651	0	80023	0	80042	80042	0	3	24	480010	20	160000	240000	20	240000	480648	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160011	10	43	160050	0	1	1	50	160039	6	1	50	43	11	0	0	5019	5	17	4	4	80039	0	80000	13	13	160000	240000	80010	80043	80043	80043	80043	80043
400024	80042	621	1	1	1	1	1	0	0	55	0	1	0	2	80027	2	6	6	3	25	480086	80010	240071	160000	80010	240000	160000	480049	961279	3124571	0	80023	0	80042	80042	0	3	24	480010	20	160000	240000	20	240000	480000	80042	80042	1	1	80021	10	9	10	10	80000	80000	1	10	160012	12	43	160049	0	1	1	53	160039	6	1	49	43	11	0	0	5019	7	17	4	7	80039	0	80000	13	14	160000	240000	80010	80043	80043	80043	80043	80043
400024	80042	620	1	0	1	1	1	0	0	56	0	0	0	2	80027	0	6	6	3	25	480086	80010	240075	160000	80010	240000	160000	480049	961283	3124559	0	80023	0	80042	80042	0	3	24	480010	20	160000	240000	20	240000	480372	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160010	11	43	160051	0	6	0	56	160039	6	1	49	43	10	1	0	5019	7	17	6	5	80039	0	80000	13	13	160000	240000	80010	80043	80043	80043	80043	80043
400024	80042	621	1	0	0	1	1	0	0	55	0	0	0	2	80027	2	7	6	3	25	480083	80010	240075	160000	80010	240000	160000	480049	961303	3124555	0	80023	0	80042	80042	0	3	24	480010	20	160000	240000	20	240000	480000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160011	11	43	160050	0	0	0	50	160039	6	1	50	43	11	0	0	5019	8	17	5	5	80384	0	80000	0	0	160000	240000	80010	80043	80043	80043	80043	80043
400024	80042	621	0	0	0	1	1	0	0	35	0	1	0	0	80027	2	12	12	0	25	480073	80010	240063	160000	80010	240000	160000	480049	960649	3119994	0	80023	0	80042	80042	0	3	24	480010	20	160000	240000	20	240000	480000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	41	160000	0	0	0	0	160037	0	1	37	41	0	0	0	5019	4	17	4	5	80039	0	80000	14	13	160000	240000	80010	80043	80043	80043	80043	80043
400024	80042	621	0	0	0	1	1	0	0	48	0	0	0	2	80027	0	12	0	0	25	480073	80010	240000	160000	80010	240000	160000	480049	959996	3121776	0	80023	0	80042	80042	0	3	24	480010	20	160000	240000	20	240000	480000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	33	160000	0	0	0	37	160037	6	1	29	41	0	0	0	5019	3	17	3	4	80039	0	80000	16	10	160000	240000	80010	80043	80043	80043	80043	80043
400024	80042	620	0	0	0	0	1	0	0	43	0	0	0	2	80027	2	12	0	0	25	480073	80010	240063	160000	80010	240000	160000	480049	959996	3119994	0	80023	0	80042	80042	0	3	24	480010	20	160000	240000	20	240000	480000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	33	160037	0	0	0	37	160000	6	1	0	41	0	0	0	5019	4	17	5	4	80039	0	80000	14	10	160000	240000	80010	80043	80043	80043	80043	80043
400024	80042	621	0	0	0	1	1	0	0	0	0	0	0	2	80027	2	0	12	0	25	480073	80010	240063	160000	80010	240000	160000	480049	959996	3119994	0	80023	0	80042	80042	0	3	24	480010	20	160000	240000	20	240000	480000	80042	80042	1	1	80021	10	9	10	10	80000	80000	1	10	160000	0	33	160037	0	0	0	37	160000	6	1	29	41	0	0	0	5019	4	17	5	4	80039	0	80000	14	10	160000	240000	80010	80043	80043	80043	80043	80043
400024	80042	620	0	0	0	1	1	0	1	43	0	0	0	0	80027	2	12	12	0	25	480073	80010	240063	160000	80010	240000	160000	480049	960781	3120094	0	80023	0	80042	80042	0	3	24	480010	20	160000	240000	20	240000	480000	80042	80042	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	33	160030	0	0	0	30	160037	6	1	37	41	0	0	0	5019	4	17	6	4	80142	0	80000	14	10	160000	240000	80010	80043	80043	80043	80043	80043

LD3 (multiple, post-index, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations