Firestorm: LD3 (multiple, post-index, 4S) measurements

Code:

  ld3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 7.003

Integer unit issues: 1.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 3.003

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
66005	29362	228	27	0	0	28	0	1	1	0	0	9	0	1	0	4614	28890	3	0	16900	7006	1000	3006	3000	1000	3000	3000	5000	15002	35726	5	23058	29269	29239	3	10	7000	3000	3000	4000	9000	29264	29188	1	1	61001	1000	1000	0	3000	0	9	3004	0	0	0	3004	5	1	4	6	0	0	12966	9399	6838	3241	15	63	20116	3363	3809	15	58	53	28558	1000	15954	13154	14503	3000	3000	1000	29321	29354	29428	29428	29231
66004	29451	228	24	0	0	24	0	0	0	0	0	9	0	1	0	4658	28910	1	1	16915	7009	1000	3003	3000	1000	3000	3000	5000	15006	35755	7	23034	29192	29473	3	10	7000	3000	3000	4000	9000	29216	29248	1	1	61001	1000	1000	0	3000	0	0	3004	0	0	4	3004	5	1	4	9	0	0	12802	9418	6902	3133	10	57	20166	3207	3808	15	58	58	28471	1000	16319	13301	14487	3000	3000	1000	29416	29488	29317	29413	29551
66004	29454	227	23	0	0	31	0	0	0	0	0	9	0	1	0	4615	28928	0	1	16849	7009	1000	3009	3000	1000	3000	3000	5000	15003	35757	5	23034	29122	29248	3	10	7000	3000	3000	4000	9000	29214	29170	1	1	61001	1000	1000	0	3000	0	9	3004	0	0	0	3004	5	1	4	9	0	0	13095	9264	6928	3099	9	57	20055	3166	3808	12	55	54	28506	1000	15966	13280	14319	3000	3000	1000	29304	29381	29366	29392	29299
66004	29333	227	21	0	0	25	0	0	0	0	0	18	0	1	0	4673	28863	3	3	16934	7009	1000	3008	3000	1000	3000	3000	5000	15006	35745	6	23001	29177	29312	9	10	7000	3000	3000	4000	9000	29166	29158	1	1	61001	1000	1000	0	3000	0	9	3004	0	0	4	3004	5	1	0	9	0	0	12982	9382	6896	3124	16	56	20226	3233	3811	6	51	59	28466	1000	16179	13329	14431	3000	3000	1000	29377	29294	29258	29368	29382
66004	29310	228	22	0	0	24	0	0	0	0	0	0	0	1	0	4573	28867	0	1	16960	7012	1000	3008	3000	1000	3000	3000	5000	15003	35765	5	23004	29167	29349	3	10	7000	3000	3000	4000	9000	29246	29202	1	1	61001	1000	1000	0	3000	2	9	3004	1	0	4	3004	5	1	4	9	0	0	13094	9421	6891	3149	15	66	20194	3252	3806	13	53	62	28531	1000	15819	13280	14428	3000	3000	1000	29337	29434	29400	29344	29285
66004	29425	227	20	0	0	27	0	0	0	0	0	9	0	1	0	4711	28919	0	0	16938	7003	1000	3009	3000	1000	3000	3000	5000	15000	35628	5	22958	29230	29353	3	10	7000	3000	3000	4000	9000	29315	29226	1	1	61001	1000	1000	0	3000	0	9	3004	0	0	4	3004	3	1	0	9	0	0	13143	9418	6885	3185	16	55	20104	3150	3808	14	61	61	28448	1000	16039	13430	14290	3000	3000	1000	29428	29360	29376	29427	29329
66004	29359	227	23	0	0	21	0	0	0	0	0	3	0	1	0	4616	28825	1	0	16977	7008	1000	3009	3000	1000	3000	3000	5000	15003	35675	0	22988	29195	29349	3	10	7000	3000	3000	4000	9000	29265	29109	1	1	61001	1000	1000	0	3000	0	9	3001	0	0	0	3004	5	1	4	9	0	0	13119	9308	6885	3093	11	56	20081	3232	3804	10	54	63	28408	1000	15779	13071	14354	3000	3000	1000	29285	29226	29307	29342	29356
66004	29496	227	27	0	0	25	0	0	0	0	0	21	0	1	0	4626	28827	3	3	16871	7008	1000	3008	3000	1000	3000	3000	5000	15000	35729	5	22996	29080	29255	3	10	7000	3000	3000	4000	9000	29160	29339	1	1	61001	1000	1000	0	3000	0	9	3000	1	0	4	3004	5	1	0	9	0	0	12945	9132	6949	3049	15	62	19965	3310	3813	9	63	60	28493	1000	16176	13125	14292	3000	3000	1000	29478	29328	29436	29556	29255
66004	29433	226	26	0	0	22	0	0	0	0	0	9	0	1	0	4644	28887	0	0	16950	7009	1000	3009	3000	1000	3000	3000	5000	15000	35728	3	22982	29290	29339	3	10	7000	3000	3000	4000	9000	29151	29224	1	1	61001	1000	1000	0	3000	0	9	3004	0	0	4	3004	5	1	4	9	0	0	12902	9121	6865	3136	14	59	20193	3220	3809	8	55	59	28628	1000	16345	13314	14305	3000	3000	1000	29345	29296	29265	29430	29343
66004	29287	227	18	0	0	28	0	1	0	0	0	9	0	1	0	4681	28895	0	0	17064	7008	1000	3008	3000	1000	3000	3000	5000	15003	35725	6	23017	29328	29356	3	10	7000	3000	3000	4000	9000	29217	29052	1	1	61001	1000	1000	0	3000	0	9	3004	0	0	4	3004	5	1	4	9	0	0	13132	9319	6919	3133	11	56	20187	3241	3809	16	54	60	28561	1000	16296	13096	14337	3000	3000	1000	29424	29397	29231	29484	29469

Count: 8

Code:

  ld3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld3 { v0.4s, v1.4s, v2.4s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	37	3a	3c	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	67	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	77	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480205	80081	620	0	0	0	0	0	0	0	46	0	0	0	2	0	80032	2	17	7	14	25	560146	80106	240041	240000	80108	240024	240019	480536	3491346	5754228	0	0	80047	80066	80070	17	0	7	37	0	560154	200	240024	240024	200	320032	720072	80065	80062	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	43	0	240041	0	0	0	44	240000	5	1	40	44	0	1	1	1	5116	0	16	0	0	80059	0	80006	10	10	240000	240000	80100	80071	80067	80047	80067	80071
480204	80066	621	0	0	0	0	0	0	0	12	0	0	0	1	0	80051	2	0	0	18	25	560146	80106	240040	240000	80108	240024	240019	480536	3491346	5751534	0	0	80047	80070	80066	0	0	6	39	0	560151	200	240024	240024	200	320032	720072	80066	80062	1	1	80201	100	99	1	100	100	80000	80000	0	100	240000	0	43	0	240041	0	0	0	40	240041	5	0	40	44	0	1	1	1	5116	0	16	0	0	80043	0	80006	10	10	240000	240000	80100	80067	80067	80047	80067	80064
480204	80065	621	0	1	0	0	0	0	0	45	0	0	2	2	0	80051	0	7	7	14	25	560146	80106	240003	240006	80108	240024	240019	480536	3524694	5702136	1	0	80434	80062	80068	13	0	6	37	0	560151	200	240024	240024	200	320032	720072	80066	80069	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	43	0	240041	0	0	0	41	240040	5	1	40	44	0	1	1	1	5116	0	16	0	0	80046	0	80006	10	14	240000	240000	80100	80047	80064	80067	80067	80067
480204	80066	643	0	0	0	0	0	0	0	46	0	0	1	0	0	80058	2	7	7	14	25	560145	80106	240041	240000	80108	240024	240024	480538	3526565	3866824	0	0	80047	80062	80062	9	0	6	17	0	560151	200	240024	240024	200	320032	720072	80066	80062	1	1	80201	100	99	0	100	100	80000	80000	1	100	240000	0	44	0	240041	0	0	0	0	240040	5	1	41	44	0	1	1	1	5117	0	16	0	0	80059	0	80006	10	10	240000	240000	80100	80071	80071	80076	80071	80071
480204	80066	643	0	0	0	0	0	0	0	46	0	0	0	2	0	80051	2	7	0	14	25	560147	80106	240041	240000	80108	240024	240024	480536	1917988	5732273	0	0	80047	80069	80066	13	0	3	48	0	560100	200	240000	240000	200	320000	720000	80045	80069	1	1	80201	100	99	1	100	100	80000	80000	0	100	240000	0	44	0	240042	0	1	0	41	240000	0	1	41	45	0	0	0	0	5109	1	17	1	1	80067	0	80000	10	14	240000	240000	80100	80071	80067	80067	80067	80071
480204	80066	643	0	0	0	0	0	0	0	45	0	0	2	2	0	80055	2	7	7	14	25	560139	80100	240039	240000	80100	240000	240000	480497	3491430	4631336	0	0	80047	80066	80045	0	0	3	45	0	560100	200	240000	240000	200	320000	720000	80066	80064	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	0	0	240040	0	1	0	41	240041	5	1	40	44	0	0	0	0	5109	1	16	1	1	80063	0	80000	10	14	240000	240000	80100	80072	80071	80068	80067	80071
480204	80066	643	0	0	0	0	0	0	0	0	0	0	2	2	0	80055	0	4	7	13	25	560140	80100	240041	240000	80100	240000	240000	480498	3528698	5685662	0	0	80030	80066	80066	13	0	3	49	0	560100	200	240000	240000	200	320000	720000	80062	80066	1	1	80201	100	99	1	100	100	80000	80000	0	100	240000	0	44	0	240041	0	0	0	44	240041	0	0	40	44	0	0	0	0	5109	1	16	1	1	80063	0	80000	29	14	240000	240000	80100	80066	80070	80067	80067	80046
480204	80045	643	0	0	0	0	0	0	0	46	0	0	2	0	0	80051	0	7	7	9	25	560139	80100	240040	240000	80100	240000	240000	480497	3524540	5753735	0	0	80051	80066	80065	13	0	3	52	0	560100	200	240000	240000	200	320000	720000	80066	80067	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	0	0	240039	0	0	0	44	240039	5	0	40	44	0	0	0	0	5109	1	16	1	1	80063	0	80000	10	10	240000	240000	80100	80067	80067	80071	80046	80067
480204	80066	643	0	0	0	0	0	0	0	58	0	0	1	1	0	80051	2	0	0	14	25	560139	80100	240005	240000	80100	240000	240000	480497	3524540	5727019	0	0	80047	80083	80066	19	0	3	53	0	560100	200	240000	240000	200	320000	720000	80068	80070	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	44	0	240040	0	1	0	40	240041	5	1	41	44	0	0	0	0	5109	1	17	1	1	80063	0	80000	10	10	240000	240000	80100	80046	80067	80067	80071	80067
480204	80067	643	0	0	0	0	0	24	15	47	0	0	4	2	0	80051	0	7	2	14	25	560139	80100	240039	240000	80100	240000	240000	480499	3524540	3866667	0	0	80047	80066	80066	9	0	3	49	0	560100	200	240000	240000	200	320000	720000	80066	80066	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	0	0	240040	0	1	0	39	240000	0	0	41	45	0	0	0	0	5109	1	16	1	1	80059	0	80000	10	10	240000	240000	80100	80066	80071	80067	80067	80063

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	37	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	67	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480025	80070	621	1	0	0	0	0	0	0	46	0	3	2	80239	2	17	17	7	60	560049	80010	240042	240000	80010	240000	240000	480417	3511704	5683980	1	80051	80062	80062	9	0	3	43	560010	20	240000	240000	20	320000	720000	80062	80056	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	35	0	240000	0	0	26986	240040	0	1	0	43	0	5019	0	6	16	10	9	80070	1	80000	0	6	240000	240000	80010	80063	80065	80063	80063	80067
480024	80062	620	0	0	0	0	0	0	0	45	0	0	0	80047	2	17	17	9	25	560049	80010	240043	240000	80010	240000	240000	480048	3533453	5720187	0	80339	80050	80062	9	0	3	56	560010	20	240000	240000	20	320500	720000	80061	80045	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	35	0	240040	0	0	0	240040	5	1	33	43	0	5019	0	9	16	9	9	80053	0	80000	6	10	240000	240000	80010	80063	80063	80046	80063	80062
480024	80066	620	0	0	0	0	0	0	0	47	0	8	0	80047	2	7	7	17	25	560049	80010	240044	240000	80010	240000	240000	480418	3524540	5738213	0	80061	80076	80066	45	0	3	27	560010	20	240000	240000	20	320000	720000	80045	80062	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	44	0	240041	1	0	43	240041	5	1	40	44	0	5019	0	7	17	10	10	80063	0	80000	14	10	240000	240000	80010	80067	80067	80067	80067	80066
480024	80066	620	0	0	0	0	1	0	0	46	0	0	2	80055	0	7	7	14	25	560049	80010	240039	240000	80010	240000	240178	480047	3524540	3866584	2	80102	80066	80066	16	0	3	49	560010	20	240000	240000	20	320000	720000	80065	80062	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	43	0	240041	0	0	41	240041	5	1	40	44	0	5033	0	10	16	10	10	80042	0	80000	14	14	240000	240000	80010	80071	80072	80067	80067	80071
480024	80066	621	0	0	0	0	0	0	0	46	0	3	2	80051	2	7	7	14	25	560049	80010	240039	240000	80010	240000	240000	480047	3522004	5751340	0	80051	80045	80070	16	0	3	27	560010	20	240000	240000	20	320000	720000	80045	80061	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	44	0	240040	0	0	44	240040	5	1	40	44	0	5019	0	10	16	10	10	80063	0	80000	14	14	240000	240000	80010	80067	80067	80067	80202	80067
480024	80066	620	0	0	0	0	0	0	0	57	0	0	2	80051	2	7	7	17	25	560049	80010	240039	240000	80010	240000	240000	480047	3530665	5698278	2	80108	80066	80045	18	0	3	51	560010	20	240000	240000	20	320000	720000	80066	80066	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	44	0	240041	0	0	41	240040	0	1	40	44	0	5019	0	10	16	10	10	80063	0	80000	14	10	240000	240000	80010	80067	80069	80066	80067	80067
480024	80062	621	0	0	0	0	0	0	0	46	0	3	2	80055	2	0	7	14	25	560049	80010	240040	240000	80010	240000	240000	480047	3524540	3866607	3	80060	80066	80066	13	0	3	45	560436	20	240000	240000	20	320000	720000	80262	80066	1	1	80021	10	9	0	10	10	80000	80000	0	10	240131	43	61	240173	0	0	5996	240301	0	1	40	44	0	5047	0	7	34	10	7	83371	0	80124	0	14	240000	240000	80010	80258	80450	80259	80258	80260
480024	80259	622	0	0	1	0	0	2	2	179	176	1	2	80422	2	7	7	919	688	565834	81054	242239	242210	81063	242955	241958	480414	3524540	5140114	4	80112	80066	80260	114	89	43	171	560862	20	240189	240378	20	320252	721134	80257	80253	3	1	80021	10	9	0	10	10	80000	80000	0	10	240130	44	115	240175	1	0	2041	240171	6	0	40	44	0	5019	0	10	17	10	10	80063	0	80000	14	10	240000	240000	80010	80071	80067	80067	80046	80067
480024	80070	620	0	0	0	0	0	0	0	55	0	10	2	80047	2	7	7	14	25	560039	80010	240041	240000	80010	240000	240000	480047	3522787	5706576	0	80070	80062	80066	0	0	3	49	560010	20	240000	240000	20	320000	720000	80067	80045	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	44	0	240041	1	0	41	240040	5	1	41	44	0	5019	0	10	17	7	10	80062	0	80000	10	10	240000	240000	80010	80067	80067	80067	80067	80067
480024	80066	621	0	0	0	0	0	0	0	46	0	0	0	80055	2	7	0	13	25	560049	80010	240039	240000	80010	240000	240000	480048	3522004	5703059	0	80065	80065	80062	0	0	3	32	560010	20	240000	240000	20	320000	720000	80066	80062	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	43	0	240000	1	0	44	240040	5	1	40	44	0	5019	0	10	16	10	6	80067	0	80000	14	10	240000	240000	80010	80067	80068	80067	80071	80067

LD3 (multiple, post-index, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations