Firestorm: LD3 (multiple, post-index, 8H) measurements

Code:

  ld3 { v0.8h, v1.8h, v2.8h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 7.009

Integer unit issues: 1.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 3.009

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	0f	1e	22	23	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
66005	28765	222	1	18	16	0	12	0	0	4906	28320	3	3	0	16212	7012	1000	3003	3000	1000	3000	3000	5000	15003	35805	9	1	0	23069	28764	28802	3	10	7000	3000	3000	4000	9000	28382	28420	1	1	61001	1000	1000	0	3000	3	0	3003	1	0	4	3003	5	1	4	9	0	13387	9674	6916	3147	7	45	19516	3210	3814	16	44	50	28098	1000	15189	12234	13390	3000	3000	1000	28536	28692	28502	28882	28695
66004	28522	222	0	15	14	0	3	1	0	4877	28163	3	0	3	16272	7009	1000	3008	3000	1000	3000	3003	5000	15003	35625	11	0	0	23021	28421	28476	3	10	7000	3000	3000	4000	9000	28690	28545	1	1	61001	1000	1000	0	3000	0	0	3004	1	0	3	3004	0	1	4	6	0	13338	9429	6952	3095	7	40	19530	3205	3810	10	45	45	28033	1000	15020	12460	13336	3000	3000	1000	28510	28658	28628	28485	28522
66004	28532	222	0	13	17	0	12	0	0	4771	28397	3	0	3	16301	7012	1000	3009	3000	1000	3000	3000	5000	15003	35749	9	0	8	23058	28429	28719	3	10	7000	3000	3000	4000	9000	28464	28549	1	1	61001	1000	1000	0	3000	0	11	3004	0	0	4	3006	0	0	3	6	0	13233	9460	6922	3194	5	41	19460	3246	3803	11	38	40	28234	1000	15369	12642	13446	3000	3000	1000	28581	28772	28676	28655	28696
66004	28683	223	0	15	14	0	9	0	0	4760	28354	3	0	3	16358	7009	1000	3003	3000	1000	3000	3000	5000	15004	35639	11	0	0	23021	28701	28758	3	10	7007	3000	3003	4000	9000	28954	28683	1	1	61001	1000	1000	0	3000	0	9	3003	3	0	4	3007	0	1	4	0	715	13253	9429	6897	3129	6	44	19531	3310	3818	5	40	39	28131	1000	16274	13431	14534	3000	3000	1000	29340	29253	29269	29254	29214
66004	29297	219	0	14	11	0	7	0	0	4560	28959	3	0	3	16900	7009	1000	3009	3000	1000	3000	3000	5000	15003	35634	0	0	0	22984	29094	29323	3	10	7000	3000	3000	4000	9000	29314	29079	1	1	61001	1000	1000	0	3000	0	9	3003	1	0	4	3003	5	1	3	0	0	12771	8897	6850	3053	4	43	20106	3064	3810	7	45	39	28421	1000	16429	13399	14567	3000	3000	1000	29505	29328	29246	29283	29250
66004	29327	219	0	17	13	0	7	0	0	4615	28845	3	1	0	17037	7006	1000	3009	3000	1000	3000	3000	5000	15000	35828	4	0	0	23026	29176	29320	3	10	7000	3000	3000	4000	9000	29247	29299	1	1	61001	1000	1000	0	3004	3	15	3010	1	1	14	3010	5	1	13	0	0	12907	9126	6846	3066	7	40	20074	3165	3811	10	41	36	28441	1000	16307	13407	14686	3000	3000	1000	29290	29305	29394	29237	29218
66004	29248	219	0	18	14	0	3	0	0	4559	28774	3	0	0	16959	7009	1000	3009	3000	1000	3003	3000	5000	15004	35753	1	0	0	22985	29039	29384	3	10	7000	3000	3000	4000	9000	29221	29158	1	1	61001	1000	1000	0	3000	0	9	3004	3	0	13	3004	5	1	4	0	0	12831	9099	6821	3013	6	45	20161	3067	3817	11	40	42	28377	1000	16419	13322	14674	3000	3000	1000	29324	29337	29314	29269	29187
66004	29326	219	0	11	17	0	7	0	0	4504	28832	3	0	3	16932	7009	1000	3009	3000	1000	3000	3000	5000	15003	35738	1	0	0	22963	29107	29337	3	10	7000	3000	3000	4000	9000	29128	29164	1	1	61001	1000	1000	0	3000	0	9	3004	3	0	7	3004	5	1	3	0	0	12790	9372	6810	3005	7	38	20114	3117	3815	12	38	63	28392	1000	16238	13196	14478	3000	3000	1000	29183	29389	29336	29259	29295
66004	29314	220	0	15	12	1	3	0	1	4650	28828	3	0	3	16883	7009	1000	3009	3000	1000	3000	3000	5000	15003	35750	5	0	0	23029	29151	29262	3	10	7000	3000	3000	4000	9000	29132	29179	1	1	61001	1000	1000	0	3000	0	9	3004	3	0	7	3003	5	1	4	9	0	12877	9215	6843	3057	9	40	20041	3106	3811	9	37	41	28356	1000	16255	13355	14525	3000	3000	1000	29281	29243	29285	29248	29206
66004	29283	220	0	15	15	0	21	0	0	4596	28853	3	0	3	16800	7009	1000	3009	3000	1000	3000	3000	5000	15003	35758	9	0	0	22982	29196	29277	3	10	7000	3000	3000	4000	9000	29212	29244	1	1	61001	1000	1000	0	3000	0	0	3004	2	0	7	3004	5	1	3	0	0	12882	9083	6856	3061	9	41	20035	3115	3816	12	40	36	28378	1000	16303	13314	14468	3000	3000	1000	29277	29320	29294	29239	29269

Count: 8

Code:

  ld3 { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld3 { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld3 { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld3 { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld3 { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld3 { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld3 { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld3 { v0.8h, v1.8h, v2.8h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0009

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	24	37	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	67	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480205	80083	621	1	0	1	0	0	1	1	0	0	0	66	0	0	7	3	80056	3	4	7	17	25	560130	80100	240027	240000	80100	240000	240000	480496	3520229	5591084	0	0	80118	0	80071	80205	22	0	3	53	560100	200	240000	240000	200	320000	720000	80071	80071	1	1	80201	100	99	0	100	100	80000	80000	100	240015	17	43	0	240056	0	0	0	58	240040	5	1	55	43	15	0	0	5109	11	16	13	13	80068	80001	13	13	240000	240000	80100	80076	80072	80072	80072	80076
480204	80071	620	1	0	0	0	0	1	0	0	0	0	76	0	0	1	2	80056	3	7	7	18	25	560122	80100	240029	240000	80100	240000	240000	480498	3520229	5688606	0	0	80055	0	80072	80071	18	0	3	54	560100	200	240000	240000	200	320000	720000	80071	80075	1	1	80201	100	99	0	100	100	80000	80000	100	240015	15	43	0	240056	1	0	1	59	240039	5	1	55	43	15	1	0	5109	8	16	12	12	80068	80000	13	13	240000	240000	80100	80072	80072	80076	80072	80072
480204	80072	620	1	0	1	0	0	0	0	0	0	0	76	0	0	5	2	84866	3	7	7	17	25	560140	80100	240026	240000	80100	240000	240000	480497	3520229	5688612	0	1	80077	0	80075	80071	18	0	3	52	560100	200	240000	240000	200	320000	720000	80071	80071	1	1	80201	100	99	0	100	100	80000	80000	100	240016	16	43	0	240056	0	0	0	61	240041	6	1	55	43	15	0	0	5109	8	17	13	8	80072	80000	13	13	240000	240000	80100	80072	80072	80076	80072	80072
480204	80071	620	1	0	0	0	0	1	0	0	0	0	76	0	0	1	2	80056	3	7	7	17	25	560143	80101	240027	240000	80100	240000	240000	480498	3547236	5723387	0	1	80052	0	80071	80071	18	0	3	54	560100	200	240000	240000	200	320000	720000	80071	80071	1	1	80201	100	99	0	100	100	80000	80000	100	240015	15	43	0	240056	0	0	1	59	240039	5	1	57	43	15	2	0	5109	11	16	13	6	80068	80000	13	13	240000	240000	80100	80072	80072	80072	80075	80072
480204	80075	620	1	0	0	1	0	1	0	0	0	0	64	0	0	0	2	80056	2	7	7	17	25	560140	80100	240042	240000	80100	240000	240000	480497	3491432	5728632	0	1	80052	0	80071	80071	18	0	3	53	560100	200	240000	240000	200	320000	720000	80074	80071	1	1	80201	100	99	0	100	100	80000	80000	100	240015	16	43	0	240056	0	0	1	62	240040	5	1	56	43	15	1	0	5109	12	16	12	12	80076	80000	13	13	240000	240000	80100	80072	80072	80072	80076	80072
480204	80071	620	1	0	1	0	0	0	0	0	0	0	76	0	0	0	2	80056	2	7	7	17	25	560128	80100	240041	240000	80100	240000	240000	480495	3527986	5680668	0	3	80057	0	80080	80071	20	0	3	55	560100	200	240000	240000	200	320000	720000	80071	80071	1	1	80201	100	99	0	100	100	80000	80000	100	240016	15	43	0	240056	1	0	1	59	240040	5	1	56	43	15	1	0	5109	14	16	8	12	80069	80000	13	13	240000	240000	80100	80072	80072	80076	80079	80076
480204	80071	621	1	0	1	0	0	0	0	0	0	0	73	0	0	0	1	80063	3	7	7	17	25	560129	80100	240042	240000	80100	240000	240000	560464	3544826	5529743	0	2	80056	0	80071	80071	18	0	3	57	560100	200	240000	240000	200	320000	720000	80071	80071	1	1	80201	100	99	0	100	100	80000	80000	100	240016	15	44	0	240055	1	0	2	59	240038	5	1	56	43	15	0	0	5109	13	17	13	13	80072	80000	13	13	240000	240000	80100	80072	80071	80076	80072	80072
480204	80071	620	1	0	0	1	0	1	0	0	0	0	75	0	0	0	3	80056	3	7	7	17	25	560143	80101	240027	240000	80100	240000	240000	480495	3547236	5673984	1	0	80055	0	80071	80071	18	0	3	54	560100	200	240000	240000	200	320000	720000	80071	80262	12	1	80201	100	99	0	100	100	80000	80000	100	240015	15	43	0	240055	0	0	0	61	240040	6	1	56	43	15	0	0	5123	10	16	15	14	80072	80000	13	13	240000	240000	80100	80072	80072	80077	80071	80072
480204	80071	621	1	0	1	0	0	0	0	0	0	1	65	0	0	1	2	80056	0	7	7	17	25	560127	80100	240028	240000	80100	240000	240000	480497	3520229	5688608	0	1	80059	0	80075	80072	18	0	3	53	560100	200	240000	240000	200	320000	720000	80072	80074	1	1	80201	100	99	0	100	100	80000	80000	100	240016	15	43	0	240056	0	1	3	59	240041	5	1	54	43	15	0	0	5109	12	16	13	8	80068	80000	13	13	240000	240000	80100	80072	80072	80072	80072	80103
480204	80652	625	1	0	0	2	0	0	0	0	0	0	66	88	0	6	2	80056	3	9	7	20	25	560127	80100	240026	240000	80100	240000	240000	560464	3520229	5688626	0	0	80055	0	80075	80071	19	0	3	54	560100	200	240000	240000	200	320000	720000	80071	80073	1	1	80201	100	99	0	100	100	80000	80000	100	240016	15	43	0	240055	0	0	1	58	240171	6	1	56	43	15	0	0	5109	12	16	13	8	80068	80000	13	14	240000	240000	80100	80072	80076	80265	80071	80072

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	24	37	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	67	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480025	80077	620	0	0	0	0	0	0	58	0	0	0	1	80047	2	17	17	241	25	560051	80010	240040	240000	80010	240000	240000	480048	3501251	5688755	0	0	80043	80066	80067	13	0	3	45	560010	20	240000	240000	20	320000	720000	80067	80062	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	44	0	240040	0	0	0	40	240040	6	1	41	43	0	5019	3	16	2	3	80059	80000	10	10	240000	240000	80010	80063	80063	80063	80415	80067
480024	80062	621	0	0	0	0	0	0	45	0	0	5	1	80047	2	9	17	224	62	560049	80010	240042	240000	80010	240000	240000	480047	3511704	5709481	0	0	80213	80062	80066	13	0	3	49	560010	20	240000	240000	20	320000	720000	80260	80062	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	43	0	240039	0	2	0	40	240041	5	1	41	44	0	5019	3	17	4	3	80059	80000	10	10	240000	240000	80010	80067	80067	80067	80063	80071
480024	80067	621	0	0	0	0	0	0	45	0	0	0	1	80047	0	17	17	221	25	560050	80010	240039	240000	80010	240000	240000	480047	3528308	3878865	0	0	80051	80062	80066	16	0	3	49	560010	20	240000	240000	20	320000	720000	80062	80062	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	43	0	240040	0	0	0	40	240040	5	1	40	43	0	5019	4	17	3	3	80059	80000	10	10	240000	240000	80010	80068	80063	80063	80242	80066
480024	80066	620	0	0	0	0	0	0	46	0	0	0	2	80051	2	17	17	228	25	560050	80010	240040	240000	80010	240000	240000	480048	3533746	5751288	0	0	80043	80062	80062	9	0	3	27	560010	20	240000	240000	20	320000	720000	80062	80066	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	43	0	240040	0	2	0	42	240040	5	1	40	43	2	5019	3	16	3	2	80063	80000	10	10	240000	240000	80010	80051	80063	80067	80063	80063
480024	80062	620	0	0	0	0	0	0	45	0	0	3	1	80051	2	17	17	255	136	560049	80073	240042	240000	80010	240000	240000	480044	3505387	5746622	0	0	80043	80062	80066	13	0	3	49	560010	20	240000	240000	20	320000	720000	80255	80062	3	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	43	0	240040	0	1	0	40	240040	5	0	40	43	0	5019	3	16	2	3	80063	80000	14	14	240000	240000	80010	80066	80068	80063	80389	80063
480024	80068	621	0	0	0	0	0	0	58	0	0	0	1	80047	2	7	17	243	25	560058	80010	240039	240000	80010	240000	240000	480047	3533453	5746615	0	0	80047	80062	80062	9	0	3	45	560010	20	240000	240000	20	320000	720000	80062	80063	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	43	57	240040	0	0	0	40	240040	5	1	40	44	0	5019	4	17	3	3	80047	80000	10	10	240000	240000	80010	80065	80067	80063	80241	80063
480024	80062	621	0	0	0	0	0	0	177	0	0	2	2	80047	2	17	17	227	25	560051	80010	240040	240000	80010	240000	240000	480048	3533647	5745301	0	0	80047	80066	80070	13	0	3	49	560010	20	240000	240000	20	320000	720000	80062	80062	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	43	0	240040	0	0	0	40	240040	5	1	40	43	0	5019	3	17	3	3	80066	80000	14	10	240000	240000	80010	80063	80063	80063	80090	80063
480024	80066	620	0	0	0	0	0	0	46	0	0	2	1	80054	2	17	17	194	25	560376	80010	240039	240000	80010	240000	240000	480048	3501251	5716140	0	0	80047	80065	80062	9	0	3	43	560010	20	240000	240000	20	320000	720000	80062	80252	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	44	0	240040	0	0	0	41	240040	5	1	40	43	0	5019	3	16	3	4	80058	80000	10	10	240000	240000	80010	80063	80067	80067	80274	80065
480024	80070	621	0	0	0	0	4	0	46	0	0	2	1	80048	2	17	7	84	25	560049	80010	240039	240000	80010	240000	240000	480048	3533453	4142414	0	0	80043	80065	80062	9	45	3	45	560010	20	240000	240000	20	320000	720000	80062	80062	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	43	0	240040	0	0	0	40	240040	5	1	0	43	0	5019	3	17	2	3	80063	80062	10	13	240000	240000	80010	80068	80063	80063	80063	80063
480024	80062	620	0	0	0	0	0	1	45	0	0	0	1	80180	2	17	17	206	25	560053	80010	240305	240000	80010	240000	240000	480048	3533453	5746620	0	0	80055	80062	80062	9	0	3	178	560436	20	240000	240000	20	320000	720000	80066	80062	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	43	0	240040	0	0	0	0	240040	0	1	40	43	0	5019	2	17	3	2	80063	80000	10	10	240000	240000	80010	80066	80063	80076	80347	80066

LD3 (multiple, post-index, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations