Firestorm: LD3 (single, B) measurements

Code:

  ld3 { v0.b, v1.b, v2.b }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.009

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.009

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	1e	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
64005	28469	213	36	0	25	0	0	0	0	3	1	0	5087	28128	1	0	2	16117	4009	3009	1000	3000	1000	5000	35694	9	22784	0	28331	28330	3	10	4000	1000	3000	1000	6000	28202	28163	1	1	61001	1000	1000	1	1000	4	1001	0	2	1001	2	2	3	0	13959	10281	6871	3077	14	79	19732	3103	3810	15	55	60	27936	14407	12407	13255	1000	3000	28781	28306	28417	28264	28282
64004	28317	211	32	0	25	0	1	1	0	4	1	0	4868	28095	1	1	1	16548	4009	3009	1000	3000	1000	5001	35760	5	22909	0	28118	28569	3	10	4000	1000	3000	1000	6000	28135	28324	1	1	61001	1000	1000	0	1000	4	1002	0	1	1002	3	1	3	0	13798	10156	7206	3422	12	60	19486	3274	3801	12	54	61	27860	14705	13091	13171	1000	3000	28250	28295	28267	28346	28315
64004	28330	213	23	0	28	0	0	0	0	4	0	0	4805	28331	1	0	2	16530	4009	3009	1000	3000	1000	5000	35765	11	22878	0	28122	28646	3	10	4000	1000	3000	1000	6000	28130	28193	1	1	61001	1000	1000	0	1000	0	1002	0	2	1002	3	2	3	2	13733	10159	7194	3495	9	53	19240	3453	3804	10	56	53	27851	14054	12347	12724	1000	3000	28181	28209	28245	28220	28288
64004	28334	212	31	0	25	0	0	0	0	4	0	0	5003	28096	1	0	0	16453	4009	3009	1000	3000	1000	5001	35774	9	22888	0	28530	28373	3	10	4000	1000	3000	1000	6000	28172	28261	1	1	61001	1000	1000	0	1000	4	1002	0	1	1002	2	2	3	0	13625	10250	7089	3343	7	57	19116	3430	3803	10	55	56	27854	15455	12401	13221	1000	3000	28344	28383	28209	28183	28215
64004	28350	215	33	0	20	0	0	0	0	4	1	0	5055	28065	1	1	2	16134	4003	3003	1000	3000	1000	5001	35659	12	22827	0	28195	28691	3	10	4000	1000	3000	1000	6000	28211	28282	1	1	61001	1000	1000	0	1000	4	1002	0	1	1002	2	2	3	0	13361	9993	7161	3088	9	61	19289	3382	3804	10	53	58	27961	14878	12503	13446	1000	3000	28227	28188	28383	28123	28328
64004	28352	213	18	0	28	0	0	0	0	4	1	0	5038	28386	1	0	0	16167	4003	3009	1000	3000	1000	5000	35637	7	22836	0	28263	28255	3	10	4000	1000	3000	1000	6000	28095	28169	1	1	61001	1000	1000	0	1000	4	1002	0	1	1002	3	2	3	0	14125	10064	6927	3425	12	55	19199	3348	3796	11	58	57	27831	14520	12192	12983	1000	3000	28207	28144	28201	28609	28619
64004	28266	211	32	0	33	0	0	0	0	4	1	0	5006	28090	1	1	2	16101	4009	3009	1000	3000	1000	5001	35770	7	22906	3	28317	28354	3	10	4000	1000	3000	1000	6000	28157	28299	1	1	61001	1000	1000	0	1000	4	1002	0	2	1002	2	2	3	0	13722	9937	7096	3402	12	54	19280	3134	3805	18	62	57	27927	14690	12303	13256	1000	3000	28231	28227	28432	28361	28192
64004	28772	211	31	0	19	0	0	0	0	7	0	0	5233	27992	1	1	2	16177	4003	3009	1000	3000	1000	5001	35769	10	22870	0	28345	28316	3	10	4000	1000	3000	1000	6000	28228	28335	1	1	61001	1000	1000	0	1000	0	1001	0	2	1001	0	2	3	0	13686	10080	7139	3101	8	63	19331	3254	3800	9	56	63	28250	15410	13124	13015	1000	3000	28245	28327	28362	28265	28451
64004	28373	211	29	0	25	0	0	0	0	4	1	0	5111	28105	1	1	1	16045	4009	3003	1000	3000	1000	5000	35631	3	22874	0	28290	28318	3	10	4000	1000	3000	1000	6000	28213	28305	1	1	61001	1000	1000	0	1000	0	1002	1	2	1002	2	1	3	0	13766	9964	7207	3201	12	60	19664	3156	3803	12	57	66	27968	14459	12700	13292	1000	3000	28321	28314	28599	28709	28656
64004	28363	212	31	0	27	0	1	1	0	1	1	0	5157	28062	1	1	0	15995	4009	3009	1000	3000	1000	5000	35751	8	22849	0	28193	28330	3	10	4000	1000	3000	1000	6000	28172	28215	1	1	61001	1000	1000	0	1000	4	1002	2	2	1001	3	1	2	0	13924	10224	7109	3347	8	58	19221	3355	3806	6	56	61	27947	14717	12407	13159	1000	3000	28191	28339	28262	28280	28661

Count: 8

Code:

  ld3 { v0.b, v1.b, v2.b }[1], [x6]
  ld3 { v0.b, v1.b, v2.b }[1], [x6]
  ld3 { v0.b, v1.b, v2.b }[1], [x6]
  ld3 { v0.b, v1.b, v2.b }[1], [x6]
  ld3 { v0.b, v1.b, v2.b }[1], [x6]
  ld3 { v0.b, v1.b, v2.b }[1], [x6]
  ld3 { v0.b, v1.b, v2.b }[1], [x6]
  ld3 { v0.b, v1.b, v2.b }[1], [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320205	160065	1199	0	1	1	1	1	0	0	20	0	0	0	0	1	160050	0	0	0	159887	25	320106	100	240012	80000	100	240000	80000	500	400050	22794693	0	160046	0	160065	160065	79914	0	3	80038	320100	200	80000	240000	200	80000	480000	160059	160041	1	1	80201	100	99	100	100	80000	80000	1	100	80008	8	0	80032	0	2	30	80023	6	1	13	0	0	0	0	0	5110	1	17	1	1	160062	1	0	13	2	80000	240000	100	160047	160066	160066	160047	160047
320204	160046	1198	1	1	0	0	0	0	0	35	0	1	0	0	1	160050	1	6	6	159887	25	320112	100	240012	80000	100	240000	80000	500	400054	22790763	0	160046	0	160065	160065	79914	0	3	80028	320100	200	80000	240000	200	80000	480000	160046	160065	1	1	80201	100	99	100	100	80000	80000	1	100	80007	7	28	80060	0	2	30	80023	6	1	29	27	7	1	0	0	5110	1	17	1	1	160062	1	0	0	0	80000	240000	100	160047	160066	160066	160066	160066
320204	160065	1199	1	1	1	0	0	0	0	7	0	1	0	0	1	160050	0	6	6	159887	25	320112	100	240012	80000	100	240000	80000	500	400054	22790763	0	160046	0	160065	160065	79914	0	3	80047	320100	200	80000	240000	200	80000	480000	160046	160046	1	1	80201	100	99	100	100	80000	80000	0	100	80008	8	28	80007	1	2	30	80023	0	0	31	0	6	1	0	0	5110	1	17	1	1	160062	1	13	13	2	80000	240000	100	160066	160066	160047	160066	160066
320204	160065	1198	1	1	1	0	0	0	0	7	0	0	0	0	0	160050	1	6	0	159887	25	320112	100	240012	80000	100	240000	80000	500	400000	22794693	0	160046	0	160065	160046	79933	0	3	80047	320326	200	80000	240000	200	80000	480000	160065	160065	1	1	80201	100	99	100	100	80000	80000	0	100	80008	8	28	80030	0	1	31	80023	6	1	31	0	6	1	0	0	5110	1	17	1	1	160062	1	13	13	0	80000	240000	100	160066	160047	160066	160047	160047
320204	160065	1198	1	1	0	0	0	0	0	40	0	0	0	0	1	160031	1	6	6	159887	25	320112	100	240012	80000	100	240000	80000	500	400048	22790763	0	160027	0	160065	160046	79914	0	3	80047	320100	200	80000	240000	200	80000	480000	160065	160046	1	1	80201	100	99	100	100	80000	80000	0	100	80008	8	27	80030	0	1	30	80000	6	0	31	27	6	0	0	0	5110	1	17	1	1	160043	1	13	13	2	80000	240000	100	160066	160066	160047	160066	160066
320204	160065	1199	1	1	1	1	0	0	0	6	0	1	0	0	1	160050	1	0	6	159887	25	320112	100	240012	80000	100	240000	80000	500	400048	22790763	0	160046	0	160046	160065	79914	0	3	80028	320100	200	80000	240000	200	80000	480000	160065	160046	1	1	80201	100	99	100	100	80000	80000	0	100	80009	9	0	80031	0	0	223	80023	6	1	31	0	6	1	0	0	5110	1	17	1	1	160062	1	13	13	2	80000	240000	100	160066	160066	160047	160047	160047
320204	160065	1199	1	1	1	0	0	0	0	7	0	1	0	0	0	160101	0	6	6	159887	25	320112	100	240006	80000	100	240000	80000	500	400048	22790763	0	160046	0	160065	160065	79933	0	3	80028	320100	200	80000	240000	200	80000	480000	160065	160065	1	1	80201	100	99	100	100	80000	80000	0	100	80060	6	28	80007	0	1	33	80023	6	0	7	27	7	0	0	0	5110	1	17	1	1	160062	1	13	13	2	80000	240000	100	160066	160066	160047	160066	160066
320204	160046	1198	1	1	1	0	0	0	0	36	0	1	0	0	0	160050	1	6	6	159887	25	320112	100	240012	80000	100	240000	80000	500	400023	22794693	0	160046	0	160046	160065	79914	0	3	80047	320100	200	80000	240000	200	80000	480000	160065	160065	1	1	80201	100	99	100	100	80000	80000	0	100	80007	7	28	80006	0	2	30	80024	6	0	30	28	7	1	0	0	5110	1	17	1	1	160062	1	0	13	2	80000	240000	100	160047	160068	160158	160687	160066
320204	160065	1199	1	1	1	0	0	0	0	35	0	1	0	0	0	160031	1	6	6	159887	25	320106	100	240012	80000	100	240000	80000	500	400155	22790763	0	160046	0	160065	160046	79900	0	3	80047	320100	200	80000	240000	200	80000	480000	160065	160097	1	1	80201	100	99	100	100	80000	80000	0	100	80009	7	27	80009	0	1	971	80024	0	1	31	28	6	0	0	0	5110	1	17	1	1	160062	0	13	0	2	80000	240000	100	160066	160047	160047	160047	160047
320204	160065	1199	1	0	1	1	1	0	0	7	0	0	0	0	1	160050	1	6	0	159853	25	320106	100	240006	80000	100	240000	80000	500	400162	22794693	0	160027	0	160065	160065	79914	0	3	80047	320100	200	80000	240000	200	80000	480000	160065	160065	1	1	80201	100	99	100	100	80000	80000	0	100	80007	7	0	80031	0	0	6	80023	6	1	29	0	7	1	0	0	5110	1	17	1	1	160062	1	13	13	0	80000	240000	100	160047	160047	160066	160066	160047

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	160065	1199	1	4	2	0	1	0	0	0	0	0	48	0	1	0	0	2	162658	1	6	6	159838	164	324434	10	241734	81914	10	240000	80000	50	400009	22789342	0	1	160037	0	160056	160056	79924	0	3	80038	325886	20	80000	240000	20	80000	480000	160056	160056	6	1	80021	10	9	10	10	80000	80000	1	10	82064	6	28	80030	0	0	1	7	80000	6	0	30	0	6	3	0	0	0	5282	0	0	24	188	18	18	160053	0	0	13	2	80000	240000	10	160066	160565	161531	161645	161627
320024	161935	1213	1	1	0	0	3	0	0	0	6	3	6	0	1	0	0	0	160026	0	6	6	159838	72	320016	10	240006	80000	10	240000	80000	50	400048	22794693	0	1	160046	0	160066	160046	79914	0	3	80047	320010	20	80000	240000	20	80000	480000	160065	160046	1	1	80021	10	9	10	10	80000	80000	1	10	80008	7	27	80009	0	1	2	31	80023	0	1	29	0	7	1	0	0	0	5020	0	0	8	17	9	18	160062	0	13	0	0	80000	240000	10	160042	160060	160060	160057	160042
320024	160056	1199	0	0	0	0	0	0	0	0	0	0	7	0	0	0	0	0	160026	1	0	6	159873	25	320110	10	240000	80058	10	240000	80000	50	400012	22793568	0	1	160040	0	160113	160041	79924	0	3	80038	320010	20	80000	240000	20	80058	480000	160116	160056	1	1	80021	10	9	10	10	80000	80000	0	10	80061	0	18	82337	0	1	0	973	80000	0	0	0	0	0	2	0	0	0	5022	0	0	12	341	19	27	160038	0	10	46	0	80000	240000	10	162497	162248	162315	161409	160066
320024	160046	1199	1	0	0	0	2	1	0	0	0	1	20	0	1	0	0	0	162300	1	6	0	159887	823	323784	10	241524	81972	10	246216	82378	50	414042	22790763	0	1	160926	0	162157	162324	78646	0	3	80012	320010	20	82552	248004	20	82610	496008	162687	162658	2	1	80021	10	9	10	10	80000	80000	1	10	80000	0	18	80000	0	2	0	3786	82565	6	1	14	18	0	0	0	0	0	5062	0	63	16	17	18	7	160038	0	113	10	2	80000	240000	10	160060	160042	160060	160042	160042
320024	160057	1241	0	0	1	0	4	1	0	0	41	48	35	0	0	1	0	0	160041	1	6	6	159838	25	320010	10	240006	80000	10	240000	80000	50	400598	22792965	0	1	160091	0	160056	160056	79927	7	3	80022	320010	20	80000	240000	20	80000	480000	160059	160056	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80014	0	0	0	18	80000	0	1	14	22	0	0	0	0	0	5020	0	0	18	17	7	18	160056	1	71	0	2	80000	240000	10	160060	160060	160060	160042	160057
320024	160056	1198	0	0	0	0	0	0	0	0	0	0	20	0	0	1	0	0	160377	1	0	6	159838	25	320016	10	240006	80000	10	240000	80000	50	400022	22792965	0	1	160022	0	160056	160059	79927	0	3	80023	320010	20	80000	240000	20	80000	480000	160059	160056	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80018	0	0	0	17	80018	6	1	14	22	0	0	0	0	0	5020	0	0	7	17	9	18	160053	1	87	0	2	80000	240000	10	160060	160060	160042	160057	160042
320024	160041	1199	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	160044	1	6	6	159876	25	320016	10	240000	80000	10	240000	80000	50	400024	22791419	0	1	160027	0	160065	160065	79933	0	3	80047	320010	20	80000	240189	20	80000	480000	160054	160155	2	1	80021	10	9	10	10	80000	80000	0	10	80000	0	15	80000	0	0	0	0	80014	0	0	10	15	0	0	0	0	0	5020	0	0	18	17	18	7	160038	1	6	6	2	80000	240000	10	160042	160056	160055	160056	160056
320024	160041	1199	0	0	0	0	0	0	0	0	0	0	20	0	0	0	0	0	160039	1	6	6	159861	25	320016	10	240000	80000	10	240000	80000	50	400000	22792366	0	0	160036	0	160041	160055	79923	0	3	80037	320010	20	80000	240000	20	80000	480000	160055	160054	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80014	0	2	0	14	80014	6	0	13	0	0	0	0	0	0	5020	0	0	18	17	18	8	160051	1	0	6	2	80000	240000	10	160055	160042	160055	160042	160042
320024	160054	1199	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	160040	1	6	6	159872	25	320016	10	240006	80000	10	240000	80000	50	400008	22792366	0	1	160036	0	160055	160055	79923	0	3	80037	320010	20	80000	240000	20	80000	480000	160041	160054	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	15	80000	0	0	0	17	80000	6	1	14	15	0	0	0	0	0	5020	0	0	6	17	9	18	160038	0	6	0	2	80000	240000	10	160057	160056	160042	160105	160056
320024	160055	1400	0	0	0	0	0	0	1	1	0	0	17	0	0	0	0	0	160040	1	6	0	159872	25	320010	10	240006	80000	10	240000	80000	50	400007	22789342	0	0	160036	0	160054	160055	79909	0	3	80037	320010	20	80000	240000	20	80000	480000	160041	160041	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	15	80000	0	0	0	14	80000	0	1	6	23	7	1	0	0	0	5020	0	0	7	17	7	17	160059	1	9	9	2	80000	240000	10	160063	160063	160063	160063	160047

LD3 (single, B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations