Firestorm: LD3 (single, D) measurements

Code:

  ld3 { v0.d, v1.d, v2.d }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.008

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 3.008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
65005	29371	220	1	32	1	1	22	1	0	0	2	0	0	4680	28817	0	0	0	17012	5010	3008	2000	3000	2000	10000	35729	2	22885	29090	29287	3	10	5000	2000	3000	2000	9000	29286	29308	1	1	61001	1000	1000	0	2004	4	4	2006	0	0	2	2	2000	4	2	6	2	1	13206	9188	6915	3140	13	76	20289	3120	3815	10	57	56	28340	16119	13326	14954	2000	3000	29314	29425	29293	29310	29361
65004	29369	219	1	18	1	1	18	1	0	0	2	0	0	4526	28931	0	0	0	17091	5010	3010	2000	3000	2000	10000	35635	3	22862	29113	29319	3	10	5000	2000	3000	2000	9000	29219	29150	1	1	61001	1000	1000	0	2004	4	6	2003	0	0	1	7	2002	4	2	4	2	2	12972	9067	6863	3124	12	52	20333	3103	3811	19	49	58	28391	16177	13206	14911	2000	3000	29284	29360	29192	29279	29390
65004	29219	219	1	25	1	1	20	0	0	0	12	0	0	4662	28769	0	0	0	16986	5003	3008	2000	3000	2000	10000	35796	1	22988	29153	29220	3	10	5000	2000	3000	2000	9000	29177	29120	1	1	61001	1000	1000	0	2004	3	4	2003	0	0	1	4	2002	4	4	4	2	0	13042	9458	6895	3082	11	59	20223	3067	3817	12	56	54	28557	16292	13186	14931	2000	3000	29420	29323	29362	29406	29286
65004	29364	220	1	17	1	1	24	1	0	0	5	0	0	4655	28860	0	0	0	16979	5003	3010	2000	3000	2000	10000	35778	8	22872	29124	29234	3	10	5000	2000	3000	2000	9000	29165	29256	1	1	61001	1000	1000	0	2003	2	4	2003	0	0	0	4	2002	6	2	4	2	1	12943	9371	6797	3036	16	60	20330	3095	3810	15	51	64	28436	16273	13214	14953	2000	3000	29312	29295	29366	29247	29349
65004	29329	220	1	20	1	1	24	2	0	0	2	0	0	4634	28789	0	0	0	16988	5008	3003	2000	3000	2000	10000	35790	6	22909	29167	29261	3	10	5000	2000	3000	2000	9000	29189	29206	1	1	61001	1000	1000	0	2003	3	4	2002	0	0	1	4	2002	6	2	0	2	2	13036	9201	6882	3063	10	53	20197	3132	3821	11	64	60	28386	16219	13147	14856	2000	3000	29295	29221	29340	29328	29245
65004	29311	221	1	21	1	1	20	1	0	0	8	1	0	4582	28746	0	0	0	17056	5008	3003	2000	3000	2000	10000	35781	8	22927	29208	29318	3	10	5000	2000	3000	2000	9000	29190	29209	1	1	61001	1000	1000	1	2003	2	6	2003	0	0	0	4	2000	4	2	4	2	2	13202	9343	6868	3066	9	57	20302	3029	3818	15	54	56	28388	16169	13332	14786	2000	3000	29323	29317	29363	29324	29281
65004	29222	219	1	27	1	1	21	1	0	0	2	0	0	4607	28874	0	0	0	16963	5008	3003	2000	3000	2000	10000	35769	4	22954	29144	29279	3	10	5000	2000	3000	2000	9000	29144	29135	1	1	61001	1000	1000	0	2004	2	4	2006	0	0	0	4	2000	4	4	4	2	1	13217	9240	6949	3083	10	52	20283	3134	3814	14	63	55	28398	16307	13232	14837	2000	3000	29257	29371	29246	29297	29215
65004	29329	220	1	19	1	1	21	0	0	0	17	0	0	4637	28929	0	0	0	17077	5008	3008	2000	3000	2000	10000	35731	8	22928	29091	29269	3	10	5000	2000	3000	2000	9000	29104	29166	1	1	61001	1000	1000	0	2004	4	6	2004	0	0	1	2	2002	4	4	6	2	2	13296	9376	6871	3085	12	58	20280	3047	3818	19	64	64	28368	16065	13296	15098	2000	3000	29331	29321	29288	29318	29263
65004	29337	220	0	24	0	0	23	0	0	0	5	0	0	4646	28813	0	0	0	17050	5000	3003	2000	3000	2000	10000	35745	5	22920	29068	29307	3	10	5000	2000	3000	2000	9000	29179	29140	1	1	61001	1000	1000	0	2000	0	4	2000	0	0	0	0	2002	4	2	0	0	0	12922	9257	6841	3140	11	68	20265	3074	3813	19	60	67	28517	16604	13178	14875	2000	3000	29312	29264	29289	29293	29348
65004	29223	220	0	21	0	0	28	0	0	0	6	0	0	4634	28770	0	0	0	17032	5003	3003	2000	3000	2000	10000	35726	4	22893	29155	29318	3	10	5000	2000	3000	2000	9000	29162	29258	1	1	61001	1000	1000	1	2000	0	4	2002	0	1	0	5	2000	4	1	6	0	0	12939	9484	6832	3107	15	65	20180	3093	3815	13	61	64	28476	16073	13181	14655	2000	3000	29307	29320	29308	29281	29285

Count: 8

Code:

  ld3 { v0.d, v1.d, v2.d }[1], [x6]
  ld3 { v0.d, v1.d, v2.d }[1], [x6]
  ld3 { v0.d, v1.d, v2.d }[1], [x6]
  ld3 { v0.d, v1.d, v2.d }[1], [x6]
  ld3 { v0.d, v1.d, v2.d }[1], [x6]
  ld3 { v0.d, v1.d, v2.d }[1], [x6]
  ld3 { v0.d, v1.d, v2.d }[1], [x6]
  ld3 { v0.d, v1.d, v2.d }[1], [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	23	24	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	160065	1199	1	1	0	1	0	0	57	0	1	0	0	2	160050	2	5	5	159887	3	25	400106	100	240012	160000	100	240000	160000	500	801284	22790763	1	160046	0	160046	160046	79933	3	80047	400100	200	160000	240000	200	160000	720000	160065	160065	1	1	80201	100	99	100	100	80000	80000	1	100	160013	13	0	160159	0	1	54	160000	6	1	52	43	12	1	0	5110	1	17	1	1	160038	0	14	10	2	160000	240000	100	160061	160061	160042	160293	160042
400204	160041	1199	0	0	0	0	1	0	42	0	1	0	0	0	160045	0	12	12	159838	0	25	400106	100	240006	160000	100	240000	160000	500	800853	22789342	0	160041	0	160060	160041	79909	3	80038	400100	200	160000	240000	200	160000	720000	160041	160041	1	1	80201	100	99	100	100	80000	80000	1	100	160000	0	35	160036	3	0	32	160036	0	1	32	40	0	0	0	5110	1	17	1	2	160057	0	10	0	2	160000	240000	100	160061	160042	160061	160057	160042
400204	160056	1199	0	0	0	0	0	4	42	0	1	0	0	0	160045	0	12	12	159838	0	25	400106	100	240006	160000	100	240000	160000	500	800005	22792974	0	160201	0	160041	160041	79909	3	80023	400100	200	160000	240000	200	160000	720000	160060	160058	1	1	80201	100	99	100	100	80000	80000	1	100	160456	0	35	160036	0	0	36	160000	0	1	0	40	0	0	0	5110	1	17	1	1	160038	0	0	14	2	160000	240000	100	160057	160057	160057	160057	160061
400204	160058	1199	0	0	1	0	0	0	42	0	1	0	0	0	160045	2	12	0	159877	0	25	400106	100	240006	160000	100	240000	160000	500	800000	22793772	0	160041	0	160041	160060	79909	3	80042	400100	200	160000	240000	200	160000	720000	160060	160056	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	35	160494	0	0	36	160036	0	1	0	0	0	0	0	5110	1	17	1	1	160057	0	14	0	2	160000	240000	100	160042	160057	160061	160042	160061
400204	160060	1199	0	0	0	0	0	0	42	0	0	0	0	2	160050	2	5	5	159887	12	25	400106	100	240012	160000	100	240000	160000	500	801294	22790763	0	160027	0	160046	160065	79933	3	80028	400100	200	160000	240000	200	160000	720000	160065	160065	1	1	80201	100	99	100	100	80000	80000	0	100	160013	14	0	160051	0	0	12	160000	6	0	52	43	13	1	0	5110	1	17	1	1	160043	0	0	0	0	160000	240000	100	160068	160047	160066	160066	160066
400204	160065	1201	1	0	0	0	0	0	60	0	0	0	0	0	160045	2	0	12	159877	0	130	400106	100	240006	160000	100	240000	160000	500	800862	22789342	1	160037	0	160060	160063	79796	3	80042	400100	200	160000	240000	200	160000	720000	160060	160041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	35	160036	1	0	32	160036	6	1	32	40	0	0	0	5110	1	17	1	1	160038	0	14	10	2	160000	240000	100	160299	160042	160063	160061	160042
400204	160060	1199	0	0	0	0	1	0	55	0	0	0	0	2	160026	2	12	12	159877	0	25	400556	100	240006	160000	100	240000	160000	500	800000	22794184	1	160201	0	160041	160060	79928	3	80042	400100	200	160000	240699	200	160000	720000	160060	160056	1	1	80201	100	99	100	100	80000	80000	0	100	160013	13	43	160012	0	1	52	160495	6	1	12	0	12	0	0	5110	1	17	1	1	160062	0	14	14	2	160000	240000	100	160042	160042	160063	160061	160061
400204	160060	1199	0	0	0	0	0	0	42	0	0	0	0	2	160026	2	0	12	159877	0	25	400106	100	240000	160000	100	240000	160000	500	800853	22789342	0	160041	0	160060	160060	79928	3	80042	400100	200	160000	240000	200	160000	720000	160041	160056	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	35	160036	0	0	36	160000	6	1	32	40	0	0	0	5110	1	17	1	1	160057	0	0	14	2	160000	240000	100	160042	160061	160057	160061	160061
400204	160056	1198	0	0	0	0	0	0	42	0	0	0	0	2	160050	0	0	0	159853	0	25	400112	100	240012	160000	100	240000	160000	500	800039	22794702	1	160027	0	160299	160065	79933	3	80047	400100	200	160000	240000	200	160000	720000	160046	160065	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	35	160000	0	0	36	160036	6	1	0	0	0	0	0	5110	1	17	1	1	160053	0	10	14	0	160000	240000	100	160061	160061	160042	160057	160061
400204	160060	1199	0	0	0	1	0	0	0	0	1	0	0	2	160045	2	12	12	159869	0	25	400106	100	240006	160000	100	240000	160000	500	800853	22789342	0	160022	0	160060	160060	79928	3	80023	400100	200	160464	240000	200	160000	720000	160041	160056	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	0	160036	4	2	36	160036	6	0	32	40	0	0	0	5110	1	17	1	1	160057	0	0	0	2	160000	240000	100	160057	160042	160042	160042	160042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	19	1e	22	23	24	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	160054	1199	0	0	1	0	38	1	0	0	0	160041	2	12	12	159838	0	25	400010	10	240006	160000	10	240000	160000	50	800374	22792375	0	1	160022	160054	160056	79922	3	80023	400010	20	160000	240000	20	160000	720000	160054	160054	1	1	80021	10	9	10	10	80000	80000	1	10	160000	27	160024	0	0	24	160032	6	1	24	35	0	0	0	0	5020	2	13	17	10	10	160053	0	0	6	0	160000	240000	10	160107	160057	160059	160055	160105
400024	160054	1199	0	0	0	0	167	1	0	0	1	160041	2	12	0	159869	0	25	400016	10	240000	160000	10	240000	160000	50	800377	22788078	1	1	160039	160041	160056	79924	3	80038	400010	20	160000	240000	20	160000	720000	160054	160054	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	160024	0	0	0	160032	6	0	24	35	0	0	0	0	5020	1	11	17	10	9	160038	1	10	6	0	160000	240000	10	160042	160042	160057	160042	160042
400024	160056	1199	0	0	1	0	38	0	0	0	1	160041	2	12	0	159869	0	25	400010	10	240000	160000	10	240000	160000	50	800000	22789342	0	1	160022	160056	160054	79909	3	80038	400010	20	160000	240000	20	160000	720000	160056	160054	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	160032	0	0	32	160032	6	1	32	35	0	0	0	0	5020	0	9	17	10	9	160053	1	10	0	2	160000	240000	10	160057	160057	160057	160057	160042
400024	160041	1198	0	1	0	0	38	1	0	0	1	160039	2	12	0	159861	0	25	400016	10	240006	160000	10	240000	160000	50	800219	22792375	0	1	160037	160056	160056	79909	3	80038	400010	20	160000	240000	20	160464	720000	160054	160041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	27	160032	1	0	32	160032	6	1	24	35	0	0	0	0	5020	0	9	17	11	11	160051	0	10	6	2	160000	240000	10	160057	160057	160042	160055	160042
400024	160056	1199	0	0	0	0	0	0	0	0	1	160026	0	12	0	159861	0	25	400016	10	240006	160000	10	240000	160000	50	801011	22789342	0	1	160037	160056	160054	79924	3	80038	400010	20	160000	240000	20	160000	720000	160054	160054	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	160000	0	0	32	160032	6	0	24	0	0	0	0	0	5020	0	9	17	9	10	160053	1	6	6	2	160000	240000	10	160055	160055	160055	160057	160105
400024	160041	1198	1	0	0	0	38	0	0	0	0	160026	2	0	12	159869	0	25	400016	10	240000	160000	10	240000	160000	50	800000	22789342	0	1	160022	160054	160041	79922	3	80038	400010	20	160000	240000	20	160000	720000	160056	160054	1	1	80021	10	9	10	10	80000	80000	0	10	160000	27	160024	0	0	0	160032	0	0	24	35	0	0	0	0	5020	0	9	17	9	10	160053	1	10	6	2	160000	240000	10	160057	160057	160042	160057	160042
400024	160106	1199	0	0	0	0	30	1	0	0	1	160041	0	0	0	159869	0	25	400010	10	240000	160116	10	240504	160000	50	800377	22789342	0	1	160037	160041	160056	79922	3	80038	400010	20	160000	240000	20	160000	720000	160054	160041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	27	160000	0	0	35	160000	6	1	0	35	0	0	0	0	5020	1	10	17	9	8	160038	1	6	6	0	160000	240000	10	160057	160042	160057	160055	160057
400024	160056	1199	0	0	0	0	37	0	0	0	0	160026	2	12	12	159869	0	25	400016	10	240000	160000	10	240000	160122	50	800222	22789342	0	1	160037	160041	160041	79909	3	80038	400010	20	160000	240000	20	160000	720000	160056	160054	1	1	80021	10	9	10	10	80000	80000	0	10	160000	27	160032	1	0	35	160032	6	1	32	0	0	0	0	0	5020	1	9	17	9	9	160038	0	10	10	0	160000	240000	10	160042	160057	160057	160042	160042
400024	160056	1198	0	0	0	0	38	1	0	0	0	160026	0	12	12	159838	0	25	400016	10	240006	160000	10	240000	160000	50	800377	22792375	0	1	160035	160041	160041	79909	3	80038	400010	20	160000	240000	20	160464	720000	160056	160054	1	1	80021	10	9	10	10	80000	80000	1	10	160000	27	160000	0	0	0	160000	6	0	0	35	0	0	0	0	5020	1	9	17	10	10	160053	1	10	0	2	160000	240000	10	160042	160057	160055	160042	160042
400024	160041	1198	0	0	0	0	38	0	0	0	1	160041	2	12	0	159869	0	25	400016	10	240006	160000	10	240000	160000	50	800374	22792974	0	1	160037	160055	160054	79909	3	80038	400010	20	160000	240000	20	160000	720000	160054	160041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	160000	0	0	0	160024	0	1	0	0	0	0	0	0	5020	0	10	17	9	9	160038	1	10	6	2	160000	240000	10	160042	160042	160057	160057	160103

LD3 (single, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations