Firestorm: LD3 (single, H) measurements

Code:

  ld3 { v0.h, v1.h, v2.h }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.003

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.003

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	0e	0f	18	1e	22	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
64005	28791	213	8	1	1	2	0	0	0	2	1	5035	28348	1	1	0	16205	4006	3006	1000	3000	1000	5000	35712	7	22899	28401	28333	3	10	4000	1000	3000	1000	6000	28309	28219	1	1	61001	1000	1000	0	1000	0	0	1002	0	1	1000	1	2	2	13039	10240	7170	3378	0	74	19723	3190	3812	10	48	50	28118	14436	12477	13469	1000	3000	28732	28760	28370	28310	28314
64004	28493	212	9	0	0	0	0	0	0	0	1	5188	28425	1	1	1	16526	4000	3006	1000	3000	1000	5000	35711	2	22911	28212	28434	3	10	4000	1000	3000	1000	6000	28330	28188	1	1	61001	1000	1000	1	1000	0	2	1002	0	2	1000	1	0	2	13098	9322	7218	3213	1	52	19253	3171	3815	17	53	54	28073	15566	12563	13034	1000	3000	28427	28782	28315	28760	28361
64004	28791	216	9	0	0	0	0	0	0	0	1	5001	28159	1	1	0	16124	4003	3006	1000	3000	1000	5000	35599	3	22904	28233	28805	3	10	4000	1000	3000	1000	6000	28718	28379	1	1	61001	1000	1000	0	1000	0	2	1002	0	2	1001	0	2	2	13093	10012	6881	3383	2	50	19315	3132	3819	16	55	53	27967	15741	12501	13493	1000	3000	28409	28395	28798	28742	28158
64004	28418	213	4	0	0	0	0	0	0	3	1	5123	28088	1	1	0	16612	4006	3003	1000	3000	1000	5000	35704	12	22921	28358	28737	3	10	4000	1000	3000	1000	6000	28249	28660	1	1	61001	1000	1000	0	1000	0	2	1001	0	1	1001	1	1	2	13629	10084	7013	3221	4	50	19417	3094	3821	15	58	54	27913	15463	12637	13454	1000	3000	28390	28339	28289	28243	28423
64004	28480	215	6	0	0	0	0	0	0	2	1	4789	28096	1	1	0	16582	4003	3003	1000	3000	1000	5000	35625	3	22905	28638	28475	3	10	4000	1000	3000	1000	6000	28219	28350	1	1	61001	1000	1000	0	1000	0	2	1002	0	5	1002	1	2	0	13843	9467	7217	3420	1	55	19338	3127	3816	8	49	50	27896	14736	12373	13423	1000	3000	28365	28325	28372	28747	28365
64004	28298	215	3	0	1	0	0	0	0	3	1	5030	28097	1	1	1	16153	4006	3003	1000	3003	1000	5000	35709	5	22891	28633	28440	3	10	4000	1000	3000	1000	6000	28355	28251	1	1	61001	1000	1000	1	1000	0	2	1001	0	4	1000	0	2	2	13807	10099	7073	3333	1	58	19843	3164	3805	13	60	59	27936	15786	12820	13590	1000	3000	28437	28341	28398	28367	28292
64004	28383	213	3	0	0	0	0	0	0	2	0	5106	28034	0	0	0	16532	4006	3006	1000	3000	1000	5000	35608	2	22874	28607	28800	3	10	4000	1000	3000	1000	6000	28343	28220	1	1	61001	1000	1000	0	1000	0	0	1001	0	1	1002	1	0	0	13862	9851	7109	3360	2	60	19862	3193	3818	20	54	57	28079	15540	13291	13580	1000	3000	28336	28324	28820	28802	28472
64004	28417	213	6	0	0	0	0	0	0	0	1	4689	28539	0	0	0	16251	4006	3006	1000	3000	1000	5000	35716	3	22833	28550	28456	3	63	4000	1000	3000	1000	6000	28336	28281	1	1	61001	1000	1000	0	1000	0	2	1002	0	2	1000	1	0	0	13114	10157	6940	3399	1	50	19803	3284	3814	15	62	52	28059	14578	12643	14026	1000	3000	28793	28424	28418	28544	28700
64004	28706	215	6	0	0	0	0	0	0	2	1	5051	28047	0	1	1	16348	4003	3006	1000	3000	1000	5000	35743	0	22862	28626	28367	3	10	4000	1000	3000	1000	6000	28267	28639	1	1	61001	1000	1000	0	1000	0	2	1000	0	2	1001	1	2	0	13075	9423	6884	3175	1	51	19313	3392	3817	18	53	52	27904	15615	13340	13539	1000	3000	28772	28355	28803	28337	28376
64004	28842	213	4	0	1	0	0	0	0	7	1	4773	28172	0	1	1	16202	4003	3003	1000	3000	1000	5000	35698	3	22864	28291	28259	3	10	4000	1000	3000	1000	6000	28567	28688	1	1	61001	1000	1000	0	1000	0	2	1001	0	2	1000	1	2	2	13804	9366	7143	3386	2	59	19720	3403	3819	9	57	55	27977	15731	13235	13334	1000	3000	28422	28302	28469	28375	28581

Count: 8

Code:

  ld3 { v0.h, v1.h, v2.h }[1], [x6]
  ld3 { v0.h, v1.h, v2.h }[1], [x6]
  ld3 { v0.h, v1.h, v2.h }[1], [x6]
  ld3 { v0.h, v1.h, v2.h }[1], [x6]
  ld3 { v0.h, v1.h, v2.h }[1], [x6]
  ld3 { v0.h, v1.h, v2.h }[1], [x6]
  ld3 { v0.h, v1.h, v2.h }[1], [x6]
  ld3 { v0.h, v1.h, v2.h }[1], [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320205	160062	1198	0	0	0	0	0	0	0	0	0	17	0	1	0	0	160039	0	6	6	159861	25	320106	100	240000	80000	100	240000	80000	500	400020	22792366	0	160035	0	160054	160105	79922	3	80036	320100	200	80000	240000	200	80000	480000	160054	160062	1	1	80201	100	99	100	100	80000	80000	0	100	80006	9	23	80026	0	1	2	29	80020	6	1	7	0	7	0	0	0	5110	0	2	17	2	2	160059	1	9	9	2	80000	240000	100	160063	160063	160047	160063	160063
320204	160062	1198	1	0	1	1	1	1	1	0	0	608	0	1	0	1	160047	1	6	6	159881	71	320300	100	240048	80174	102	240504	80174	500	400033	22794001	1	160043	0	160062	160062	79930	3	80044	320100	200	80000	240000	200	80000	480000	160062	160062	1	1	80201	100	99	100	100	80000	80000	0	100	80064	7	23	81228	0	0	2	29	80020	6	1	25	23	6	0	0	0	5110	0	2	17	2	2	160059	0	9	9	2	80000	240000	100	160063	160063	160063	160063	160047
320204	160159	1199	1	0	2	2	0	0	0	6	5	32	0	1	0	1	160047	1	6	6	159881	25	320112	100	240012	80000	100	240000	80000	500	400043	22790763	1	160043	0	160062	160046	79930	3	80044	320100	200	80000	240000	200	80000	480000	160062	160062	1	1	80201	100	99	100	100	80000	80000	1	100	80007	7	23	80027	0	1	2	26	80020	6	1	25	0	6	1	0	0	5110	0	2	17	4	2	160059	0	9	9	2	80000	240000	100	160063	160063	160063	160047	160063
320204	160062	1199	1	0	1	0	1	0	0	0	0	32	0	1	0	0	160031	0	6	6	159881	25	320112	100	240012	80000	100	240000	80000	500	400039	22792857	1	160027	0	160062	160062	79930	3	80028	320100	200	80000	240000	200	80000	480000	160062	160062	1	1	80201	100	99	100	100	80000	80000	0	100	80007	6	24	80027	0	0	1	26	80018	6	1	26	24	7	0	0	0	5110	0	2	17	2	2	160043	1	9	0	2	80000	240000	100	160047	160063	160063	160063	160063
320204	160062	1199	1	0	0	1	0	1	1	0	0	32	0	1	0	1	160047	1	6	6	159881	25	320206	100	240012	80058	100	240000	80000	500	400033	22794001	0	160043	0	160062	160062	79930	3	80044	320100	200	80000	240000	200	80000	480000	160046	160062	1	1	80201	100	99	100	100	80000	80000	1	100	80008	8	24	80026	0	0	0	26	80018	6	1	7	23	7	2	0	0	5110	0	2	17	2	2	160059	0	9	9	2	80000	240000	100	160063	160063	160063	160063	160047
320204	160062	1199	1	0	0	1	1	0	0	0	0	6	0	1	0	1	160047	1	6	6	159881	25	320112	100	240012	80000	100	240000	80000	500	400033	22794001	0	160043	0	160062	160062	79930	3	80028	323720	200	80000	240000	200	80000	480000	160046	160062	1	1	80201	100	99	100	100	80000	80000	0	100	80007	8	24	80026	0	5	1	7	80020	6	1	25	0	6	0	0	0	5130	1	2	17	2	2	160059	0	0	9	0	80000	240000	100	160047	160063	160047	160047	160047
320204	160046	1199	1	0	1	1	1	0	0	0	0	7	0	1	0	1	160047	1	0	6	159881	25	320106	100	240012	80000	100	240000	80061	500	400003	22794001	0	160027	0	160062	160062	79914	3	80044	320100	200	80000	240000	200	80000	480000	160046	160062	1	1	80201	100	99	100	100	80000	80000	0	100	80008	8	24	80027	0	0	1	7	80019	6	1	26	0	7	0	0	0	5110	0	2	17	2	2	160059	1	0	9	2	80000	240000	100	160047	160063	160063	160063	160063
320204	160062	1199	1	0	0	0	1	0	0	0	0	32	0	0	0	1	160031	1	6	6	159881	25	320112	100	240012	80000	100	240000	80000	500	400033	22794001	0	160043	0	160062	160062	79914	3	80044	320100	200	80000	240000	200	80000	480000	160046	160062	1	1	80201	100	99	100	100	80000	80000	0	100	80007	7	24	80028	0	0	0	26	80020	6	1	7	23	6	1	0	0	5110	0	2	17	2	2	160043	1	9	9	2	80000	240000	100	160047	160063	160063	160063	160063
320204	160062	1199	1	0	1	1	0	0	0	0	0	52	0	0	1	1	160047	0	0	6	159853	25	320112	100	240012	80000	100	240000	80000	500	400033	22794001	0	160043	0	160062	160062	79930	3	80044	320100	200	80000	240000	200	80000	480000	160062	160046	1	1	80201	100	99	100	100	80000	80000	0	100	80007	9	23	80026	0	0	0	25	80019	6	0	26	24	7	1	0	0	5110	0	2	17	2	2	160059	0	0	9	2	80000	240000	100	160063	160063	160063	160063	160063
320204	160062	1199	1	0	1	1	1	1	0	0	0	7	0	0	0	1	160047	1	6	6	159853	25	320106	100	240012	80000	100	240000	80000	500	400000	22794004	0	160027	0	160062	160062	79930	3	80044	320100	200	80000	240000	200	80000	480000	160046	160062	1	1	80201	100	99	100	100	80000	80000	0	100	80009	7	23	80008	0	1	0	25	80020	6	1	7	23	6	2	0	0	5110	0	2	17	2	2	160059	0	9	9	0	80000	240000	100	160063	160063	160047	160063	160047

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d2	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	160062	1199	1	0	0	1	1	1	2141	1	0	0	160047	1	6	6	159869	25	320022	10	240012	80000	10	240000	80000	50	400034	22792597	1	1	160043	160062	160055	79930	3	80044	320010	20	80000	240000	20	80000	480000	160062	160066	1	1	80021	10	9	10	10	80000	80000	0	10	80007	8	24	80027	0	0	2	42	80018	6	1	27	23	7	0	0	5020	0	12	17	0	0	14	10	160052	0	0	9	0	80000	240000	10	160063	160056	160063	160056	160056
320024	160055	1199	1	0	0	0	0	0	1215	0	0	0	160040	10	0	16	159881	25	320028	10	240018	80000	10	240000	80000	50	400338	22791228	0	1	160043	160062	160062	79930	3	80044	320010	20	80000	240000	20	80000	480000	160062	160055	1	1	80021	10	9	10	10	80000	80000	0	10	80007	6	24	80027	0	0	1	26	80018	0	1	25	0	7	1	0	5020	0	17	17	0	0	14	14	160059	0	9	9	2	80000	240000	10	160056	160056	160063	160063	160063
320024	160062	1199	1	1	0	1	0	0	1367	0	0	0	160040	1	0	6	159890	25	320022	10	240012	80000	10	240000	80000	50	400013	22794001	0	1	162402	160062	160062	79923	3	80044	320010	20	80000	240000	20	80000	480000	160062	160113	1	1	80021	10	9	10	10	80000	80000	0	10	80007	8	24	80018	0	0	0	18	80018	6	0	17	24	6	0	0	5020	0	13	17	0	0	14	16	160052	0	0	9	0	80000	240000	10	160056	160067	160067	160067	160063
320024	160062	1199	1	0	1	1	0	0	142	0	0	0	160051	10	6	6	159881	25	320022	10	240012	80000	10	240000	80000	50	400038	22792597	0	1	160036	160055	160062	79930	3	80044	320010	20	80000	240000	20	80000	480000	160062	160062	1	1	80021	10	9	10	10	80000	80000	0	10	80008	9	23	80026	0	0	3	3780	80019	6	0	18	29	7	0	0	5020	0	13	17	0	0	13	13	160063	0	6	6	2	80000	240000	10	160063	160067	160063	160063	160063
320024	160066	1199	1	1	1	1	0	0	84	1	0	0	160047	1	6	17	159881	25	320022	10	240012	80000	10	240000	80000	50	400039	22794001	0	1	160043	160062	160055	79930	3	80044	320010	20	80000	240000	20	80000	480000	160066	160062	1	1	80021	10	9	10	10	80000	80000	0	10	80007	8	0	80018	0	0	1	26	80010	6	1	26	0	7	1	0	5020	0	14	17	0	0	11	11	160059	0	9	9	2	80000	240000	10	160063	160063	160056	160056	160067
320024	160106	1199	1	0	1	1	0	0	1135	0	0	0	160040	10	6	17	159881	25	320116	10	240012	80000	10	240000	80000	50	400033	22792597	0	1	160036	160062	160062	79930	3	80044	320010	20	80000	240000	20	80000	480000	160062	160055	1	1	80021	10	9	10	10	80000	80000	0	10	80008	8	24	80017	0	0	0	26	80018	0	1	18	24	6	1	1	5020	0	17	17	0	0	18	14	160059	1	0	0	2	80000	240000	10	160067	160056	160063	160056	160063
320024	160062	1199	1	1	1	1	0	1	1376	0	0	0	160051	11	0	6	159869	25	320022	10	240018	80000	10	240000	80000	50	400038	22792597	0	1	160043	160055	160062	79930	3	80044	320010	20	80000	240000	20	80000	480000	160066	160062	1	1	80021	10	9	10	10	80000	80000	0	10	80007	8	24	80027	0	0	1	20	80019	6	1	26	29	7	2	0	5020	0	13	17	0	0	13	11	160052	0	9	9	0	80000	240000	10	160063	160063	160063	160063	160063
320024	160055	1199	1	1	1	1	0	0	713	1	0	0	160051	1	0	6	159881	25	320022	10	240012	80000	10	240000	80000	50	400004	22794001	0	1	160036	160055	160062	79923	3	80048	320010	20	80000	240000	20	80063	480000	160062	160062	1	1	80021	10	9	10	10	80000	80000	0	10	80007	8	23	80027	0	0	0	39	80011	6	1	26	23	7	1	0	5020	0	12	17	0	0	16	16	160059	1	9	0	2	80000	240000	10	160063	160063	160063	160067	160063
320024	160055	1199	1	1	1	1	0	0	1103	0	0	0	160047	1	11	6	159881	25	320022	10	240012	80000	10	240000	80000	50	400013	22823280	0	1	160047	160399	160055	79934	22	80034	320010	20	80000	240000	20	80000	480000	160066	160062	1	1	80021	10	9	10	10	80000	80000	0	10	80007	9	0	80025	0	0	0	26	80010	6	0	26	24	0	0	0	5020	0	14	17	0	0	12	12	160059	0	9	9	2	80000	240000	10	160056	160063	160056	160056	160063
320024	160062	1199	1	1	1	1	1	1	1245	1	0	0	160051	11	0	14	159890	25	320022	10	240012	80000	10	240000	80000	50	400062	22794870	0	1	160043	160055	160062	79930	3	80044	320010	20	80000	240000	20	80000	480000	160062	160055	2	1	80021	10	9	10	10	80000	80000	0	10	80008	8	23	80018	0	0	1	27	80020	6	1	17	23	6	1	0	5020	0	13	17	0	0	11	12	160059	1	0	9	2	80000	240000	10	160063	160063	160063	160063	160067

LD3 (single, H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations