Firestorm: LD3 (single, S) measurements

Code:

  ld3 { v0.s, v1.s, v2.s }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.009

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.009

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0f	18	1e	22	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
64005	29315	220	0	19	0	18	0	1	0	49	1	4643	28709	1	1	1	17124	4009	3009	1000	3000	1000	5001	35775	0	0	0	22843	29215	29390	3	10	4000	1000	3000	1000	6000	29108	29077	1	1	61001	1000	1000	0	1000	0	4	1001	0	0	1	1001	3	1	3	0	0	0	12927	9181	6844	3058	6	58	20291	3119	3818	17	56	51	28284	16191	13834	15074	1000	3000	29368	29367	29304	29310	29368
64004	29352	219	0	16	0	20	0	0	0	8	0	4628	28793	1	0	1	17097	4009	3009	1000	3000	1000	5001	35735	2	0	0	22779	29153	29424	3	10	4000	1000	3000	1000	6000	29203	29141	1	1	61001	1000	1000	0	1000	0	4	1001	0	0	1	1001	3	1	3	0	0	0	12979	9352	6884	3107	7	57	20301	3132	3814	20	53	53	28378	16111	13801	14915	1000	3000	29238	29264	29257	29351	29317
64004	29431	219	0	17	0	24	0	0	0	7	0	4575	28745	1	0	1	17153	4009	3009	1000	3000	1000	5000	35792	4	0	0	22812	29046	29382	3	10	4000	1000	3000	1000	6000	29187	29208	1	1	61001	1000	1000	0	1000	0	3	1001	0	0	1	1001	3	1	3	0	0	0	12942	9175	6854	3094	6	55	20368	3077	3816	13	50	55	28342	16346	13971	14975	1000	3000	29382	29326	29260	29350	29268
64004	29291	221	0	20	0	16	0	0	0	24	0	4646	28760	1	0	1	17119	4009	3009	1000	3000	1000	5000	35783	2	0	0	22837	29077	29457	3	10	4000	1000	3000	1000	6000	29114	29154	1	1	61001	1000	1000	0	1000	0	3	1001	0	0	1	1001	3	1	2	0	0	0	12950	9275	6924	3075	9	54	20294	3038	3817	9	52	55	28335	16289	13898	15069	1000	3000	29319	29259	29341	29374	29277
64004	29240	219	0	25	0	21	0	0	0	67	1	4601	28719	1	0	1	17107	4009	3009	1000	3000	1000	5000	35783	7	0	0	22832	29152	29334	3	10	4000	1000	3000	1000	6000	29173	29169	1	1	61001	1000	1000	0	1001	3	4	1005	0	1	3	1003	2	4	2	1	2	0	12775	9075	6864	3066	8	55	20318	3091	3817	16	55	50	28380	16385	13908	15029	1000	3000	29271	29360	29314	29402	29350
64004	29426	219	0	19	0	17	0	0	0	12	1	4653	28796	2	1	2	17068	4015	3015	1000	3000	1000	5001	35828	2	0	0	22794	29119	29336	3	10	4000	1000	3000	1000	6000	29188	29171	1	1	61001	1000	1000	0	1000	0	3	1001	0	0	1	1001	3	1	3	0	0	0	12991	9178	6860	3067	9	50	20344	3117	3815	16	54	52	28328	16166	14017	15179	1000	3000	29267	29294	29246	29377	29284
64004	29314	220	0	20	0	22	0	0	0	11	1	4622	28756	1	0	2	17070	4009	3011	1000	3000	1000	5000	35738	1	0	0	22833	29099	29218	3	10	4000	1000	3000	1000	6000	29111	29142	1	1	61001	1000	1000	0	1000	0	3	1001	0	0	1	1001	3	1	3	0	0	0	12962	9217	6830	3039	9	56	20245	3078	3819	19	51	52	28335	16310	13824	14835	1000	3000	29205	29234	29406	29331	29300
64004	29250	220	0	24	0	17	0	0	0	10	1	4651	28812	1	0	1	17103	4009	3009	1000	3000	1000	5001	35790	7	0	0	22760	29106	29367	3	10	4000	1000	3000	1000	6000	29125	29097	1	1	61001	1000	1000	0	1000	0	3	1001	0	0	2	1001	2	1	3	0	0	0	12903	9287	6869	3101	8	53	20297	3126	3818	18	56	55	28432	16291	13940	15127	1000	3000	29341	29349	29362	29351	29226
64004	29383	220	0	21	0	14	0	0	0	282	0	4614	28859	1	0	1	17069	4009	3009	1000	3000	1000	5000	35802	4	0	0	22858	29144	29313	3	10	4000	1000	3000	1000	6000	29173	29119	1	1	61001	1000	1000	0	1000	0	4	1001	0	0	1	1003	3	1	3	0	0	0	13019	9196	6917	3080	14	55	20325	3080	3817	19	55	54	28398	16284	13752	15053	1000	3000	29278	29290	29267	29274	29275
64004	29357	220	0	20	0	24	0	0	0	52	0	4576	28858	1	0	1	17052	4009	3009	1000	3000	1000	5000	35800	5	0	0	22791	29124	29346	3	10	4000	1000	3000	1000	6000	29147	29128	1	1	61001	1000	1000	0	1000	0	4	1001	0	0	1	1001	2	1	3	0	0	0	13038	9241	6899	3088	11	58	20298	3072	3818	9	54	48	28375	16219	13858	15193	1000	3000	29282	29352	29397	29351	29282

Count: 8

Code:

  ld3 { v0.s, v1.s, v2.s }[1], [x6]
  ld3 { v0.s, v1.s, v2.s }[1], [x6]
  ld3 { v0.s, v1.s, v2.s }[1], [x6]
  ld3 { v0.s, v1.s, v2.s }[1], [x6]
  ld3 { v0.s, v1.s, v2.s }[1], [x6]
  ld3 { v0.s, v1.s, v2.s }[1], [x6]
  ld3 { v0.s, v1.s, v2.s }[1], [x6]
  ld3 { v0.s, v1.s, v2.s }[1], [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320205	160065	1199	0	0	0	0	0	0	0	1	1	0	0	20	0	0	0	0	160026	1	6	6	159873	25	320106	100	240000	80000	100	240000	80000	500	400300	22792965	0	160040	0	160056	160056	79909	0	3	80038	320100	200	80000	240000	200	80000	480000	160041	160056	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80013	0	0	17	80018	6	1	0	27	0	0	0	0	0	5110	0	1	17	1	1	160056	1	0	13	10	2	80000	240000	100	160057	160060	160060	160060	160060
320204	160059	1198	0	0	0	0	0	0	0	0	0	0	0	19	0	1	0	0	160026	1	6	6	159838	25	320106	100	240006	80000	100	240000	80000	500	400029	22789342	0	160040	0	160059	160041	79924	0	3	80014	320100	200	80000	240000	200	80000	480000	160059	160056	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80018	0	0	17	80024	6	1	0	27	0	0	0	0	0	5110	0	1	17	1	1	160053	1	0	10	0	0	80000	240000	100	160042	160042	160060	160060	160042
320204	160059	1199	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	160026	1	6	6	159873	25	320106	100	240006	80000	100	240000	80000	500	400011	22792965	0	160037	0	160056	160059	79909	0	3	80041	320100	200	80000	240000	200	80000	480000	160059	160056	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	0	80014	0	0	24	80018	0	1	0	28	0	0	0	0	0	5110	0	1	17	1	1	160056	1	0	13	0	2	80000	240000	100	160094	160060	160042	160060	160060
320204	160041	1199	0	0	0	0	0	0	0	0	0	0	0	24	0	0	0	0	160026	0	0	0	159876	25	320106	100	240006	80000	100	240000	80000	500	400022	22789342	1	160040	0	160056	160056	79927	0	3	80041	320100	200	80000	240000	200	80000	480000	160059	160056	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80018	0	0	18	80014	6	0	13	28	0	0	0	0	0	5130	1	1	17	1	1	160038	0	0	13	10	0	80000	240000	100	160057	160057	160057	160042	160060
320204	160041	1199	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	160044	0	0	6	159876	25	320106	100	240006	80000	100	240000	80000	500	400015	22792965	0	160027	0	160059	160059	79927	0	3	80023	320100	200	80000	240000	200	80000	480000	160041	160056	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80014	0	0	17	80018	6	1	18	28	0	0	0	0	0	5110	0	1	17	1	1	160038	0	0	13	10	0	80000	240000	100	160042	160060	160057	160060	160042
320204	160059	1199	0	0	0	0	0	0	0	0	0	0	0	20	0	0	0	0	160044	1	0	6	159876	25	320106	100	240000	80000	100	240000	80000	500	400019	22792965	1	160046	3	160059	160059	79927	0	3	80041	320100	200	80000	240000	200	80000	480000	160059	160056	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80014	1	0	21	80000	6	1	18	28	0	0	0	0	0	5110	0	1	17	1	1	160038	1	0	10	0	2	80000	240000	100	160060	160060	160060	160060	160042
320204	160059	1199	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	160026	1	0	0	159838	25	320100	100	240006	80000	100	240000	80000	500	400000	22792965	1	160046	0	160056	160041	79927	0	3	80041	320100	200	80000	240000	200	80000	480000	160041	160056	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80000	1	0	17	80018	0	1	14	0	0	0	0	0	0	5110	0	1	17	1	1	160038	1	0	0	0	2	80000	240000	100	160042	160057	160060	160063	160060
320204	160059	1199	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	160041	0	6	6	159838	25	320106	100	240006	80000	100	240000	80000	500	400029	22792965	0	160046	0	160056	160059	79909	7	3	80041	320100	200	80000	240000	200	80000	480000	160041	160041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80018	0	0	18	80018	6	0	13	0	0	0	0	0	0	5110	0	1	17	1	1	160038	1	0	0	13	0	80000	240000	100	160042	160060	160060	160060	160042
320204	160059	1199	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	160026	0	6	0	159838	25	320106	100	240000	80000	100	240000	80000	500	400015	22789342	1	160046	0	160041	160059	79909	0	3	80023	320100	200	80000	240000	200	80000	480000	160056	160056	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80000	0	0	14	80018	6	0	0	0	0	0	0	0	0	5110	0	1	17	1	1	160056	0	0	13	10	2	80000	240000	100	160057	160060	160042	160060	160060
320204	160041	1199	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	160044	0	6	6	159838	25	320106	100	240006	80000	100	240000	80000	500	400018	22792965	0	160046	0	160059	160041	79924	0	3	80023	320100	200	80000	240000	200	80000	480378	160056	160041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80017	0	0	18	80017	6	1	17	28	0	0	0	0	0	5110	0	1	26	1	1	160038	1	0	10	10	0	80000	240000	100	160060	160060	160060	160060	160060

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4e	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	160062	1199	1	0	1	1	0	0	0	0	31	0	1	0	1	160047	1	6	6	159881	0	25	320022	10	240006	80000	10	240000	80000	50	400038	22794001	0	1	160043	0	160046	160046	79930	0	3	80044	320010	20	80000	240000	20	80063	480000	160062	160062	1	1	80021	10	9	10	10	80000	80000	0	10	80008	8	23	80026	0	2	26	80020	6	1	27	24	6	0	0	0	0	5020	0	0	0	5	17	0	5	6	160059	1	9	9	2	80000	240000	10	160063	160063	160063	160063	160063
320024	160062	1199	1	0	1	0	0	0	0	0	32	0	1	0	1	160098	1	6	6	159881	0	25	320022	10	240006	80000	10	240000	80061	50	400045	22790763	0	1	160043	0	160062	160046	79930	0	3	80044	320010	20	80000	240000	20	80000	480000	160046	160062	1	1	80021	10	9	10	10	80000	80000	0	10	80008	7	24	80028	0	1	26	80018	6	1	7	24	7	1	0	0	0	5020	0	0	0	4	17	0	6	4	160059	0	9	9	0	80000	240000	10	160063	160063	160063	160063	160063
320024	160062	1199	1	0	1	1	0	0	0	0	32	0	0	0	1	160047	1	6	6	159881	0	25	320016	10	240012	80000	10	240000	80000	50	400003	22794001	1	1	160027	0	160046	160062	79914	7	3	80044	320010	20	80000	240000	20	80000	480000	160062	160062	1	1	80021	10	9	10	10	80000	80000	0	10	80007	8	24	80025	0	0	26	80018	6	1	26	24	6	0	0	0	0	5020	0	0	0	5	17	0	4	6	160059	0	9	9	2	80000	240000	10	160063	160063	160063	160063	160063
320024	160062	1199	1	0	0	1	0	0	0	0	31	0	0	0	1	160047	1	6	6	159881	0	25	320016	10	240012	80000	10	240000	80000	50	400038	22794001	0	1	160043	0	160062	160062	79930	0	3	80044	320010	20	80063	240000	20	80000	480000	160062	160046	1	1	80021	10	9	10	10	80000	80000	0	10	80007	7	24	80025	0	0	26	80000	6	1	26	23	7	0	0	0	0	5033	0	0	0	6	17	0	7	4	160059	0	9	0	2	80000	240000	10	160063	160063	160063	160063	160063
320024	160062	1199	1	0	1	0	0	0	0	0	6	0	1	0	1	160047	1	6	0	159881	0	25	320022	10	240012	80000	10	240000	80000	50	400033	22794001	0	0	160043	0	160062	160062	79930	0	3	80044	320010	20	80000	240000	20	80000	480000	160062	160062	1	1	80021	10	9	10	10	80000	80000	0	10	80007	8	0	80008	0	0	28	80019	6	1	26	0	7	1	0	0	0	5020	0	0	0	7	17	1	6	4	160059	1	9	9	2	80000	240000	10	160063	160063	160047	160063	160063
320024	160062	1198	1	0	0	1	0	0	0	0	7	0	1	0	1	160047	1	6	6	159881	0	25	320016	10	240012	80000	10	240000	80000	50	400029	22790763	0	1	160027	0	160062	160062	79914	0	3	80044	320010	20	80000	240000	20	80000	480000	160062	160062	1	1	80021	10	9	10	10	80000	80000	1	10	80008	8	23	80026	0	0	25	80019	0	1	26	24	6	1	0	0	0	5020	0	0	0	6	17	0	6	4	160059	0	9	9	0	80000	240000	10	160063	160063	160063	160063	160047
320024	160062	1199	1	0	0	0	1	1	0	0	31	0	1	0	1	160047	1	6	6	159881	0	25	320016	10	240012	80000	10	240000	80000	50	400047	22794001	0	1	160043	0	160046	160062	79930	0	3	80044	320010	20	80000	240000	20	80000	480000	160062	160062	1	1	80021	10	9	10	10	80000	80000	0	10	80009	7	24	80027	0	2	26	80000	6	1	26	24	7	2	0	0	0	5020	14	0	0	5	17	0	6	6	160059	1	9	9	2	80000	240000	10	160047	160063	160063	160047	160063
320024	160062	1199	1	0	0	1	0	0	0	0	7	0	1	0	1	160047	1	6	0	159881	0	25	320022	10	240006	80000	10	240000	80000	50	400038	22794001	0	1	160043	0	160062	160097	79930	0	3	80044	320010	20	80000	240000	20	80000	480000	160046	160046	1	1	80021	10	9	10	10	80000	80000	0	10	80007	8	23	80028	0	2	26	80020	6	1	25	23	6	2	0	0	0	5020	0	0	0	6	17	0	4	6	160059	1	9	9	0	80000	240000	10	160047	160063	160063	160063	160063
320024	160062	1199	1	0	1	1	0	0	0	0	31	0	0	0	1	160031	1	6	0	159881	0	25	320022	10	240012	80000	10	240000	80000	50	400000	22794001	0	1	160043	0	160062	160046	79930	0	3	80044	320010	20	80000	240000	20	80000	480000	160062	160062	1	1	80021	10	9	10	10	80000	80000	0	10	80007	8	24	80025	0	0	29	80018	6	0	26	0	7	1	0	0	1	5020	0	0	0	6	17	0	4	6	160059	1	9	9	2	80000	240000	10	160063	160063	160063	160063	160063
320024	160062	1199	1	0	0	0	0	0	0	0	32	0	1	0	1	160047	1	6	0	159881	8	25	320022	10	240012	80000	10	240000	80000	50	400033	22794001	0	1	160043	0	160046	160062	79914	0	3	80028	320236	20	80000	240000	20	80000	480000	160062	160062	1	1	80021	10	9	10	10	80000	80000	0	10	80009	9	23	80009	0	1	25	80000	6	0	26	23	7	1	0	0	0	5020	0	0	0	6	17	0	4	6	160059	0	9	9	2	80000	240000	10	160047	160063	160063	160063	160047

LD3 (single, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations