Firestorm: LD3 (single, post-index, B) measurements

Code:

  ld3 { v0.b, v1.b, v2.b }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.003

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.003

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5e	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
64005	29552	228	4	4	0	0	3	0	0	1	0	0	3	0	0	0	4537	28840	0	0	17163	5003	1000	3003	1000	1000	3000	1000	5000	5000	35637	0	3	22836	29136	29293	3	10	5000	1000	3000	2000	6000	29235	29259	1	1	61001	1000	1000	0	1000	0	3	1000	0	0	0	0	1000	0	0	2	0	0	13098	9407	6905	3192	0	53	20355	3193	3826	11	49	53	28555	1000	16282	13346	14509	1000	3000	1000	29312	29327	29260	29391	29409
64004	29475	227	0	3	0	0	1	0	0	1	0	0	6	0	0	0	4726	28913	0	0	17143	5003	1000	3000	1000	1000	3000	1000	5000	5000	35691	0	6	22784	29195	29230	3	10	5000	1000	3000	2000	6000	29219	29107	1	1	61001	1000	1000	0	1000	0	3	1000	0	0	0	0	1000	0	0	0	0	0	13121	9282	6931	3160	2	56	20281	3153	3823	17	52	55	28599	1000	16234	13335	14452	1000	3000	1000	29295	29363	29505	29299	29231
64004	29285	227	0	2	0	0	0	0	0	1	0	0	2	0	0	0	4612	28860	0	0	17045	5003	1000	3003	1000	1000	3000	1000	5000	5000	35709	0	2	22867	29094	29246	3	10	5000	1000	3000	2000	6000	29229	29218	1	1	61001	1000	1000	0	1000	0	3	1000	0	0	4	7	1003	0	0	3	0	0	13045	9104	6873	3101	1	55	20339	3227	3818	11	50	55	28494	1000	15910	13258	14209	1000	3000	1000	29315	29487	29274	29365	29344
64004	29177	227	0	3	0	0	2	0	0	1	0	0	0	0	0	0	4740	29164	0	1	17737	5000	1000	3003	1000	1000	3000	1000	5000	5000	35689	0	8	22818	29204	29591	3	10	5000	1000	3000	2000	6000	29525	29462	1	1	61001	1000	1000	0	1000	0	3	1000	0	0	0	3	1000	2	0	3	0	0	13074	9273	6945	3136	0	46	20430	3097	3824	14	50	57	28423	1000	16311	13444	14393	1000	3000	1000	29394	29300	29448	29338	29282
64004	29370	227	0	2	0	0	3	0	0	1	0	0	14	0	0	0	4617	28881	0	0	17541	5003	1000	3003	1000	1000	3000	1000	5000	5000	35631	0	7	22816	29118	29439	3	10	5000	1000	3000	2000	6000	29326	29239	1	1	61001	1000	1000	0	1000	0	0	1001	0	0	0	1	1001	2	0	0	0	147	13183	9321	6938	3199	0	50	20505	3340	3822	15	59	49	28671	1000	16203	13322	14538	1000	3000	1000	29409	29464	29335	29352	29308
64004	29303	228	0	3	0	0	0	0	0	1	0	0	2	0	0	0	4595	28876	0	0	17157	5000	1000	3003	1000	1000	3000	1000	5000	5000	35703	0	7	22844	29140	29311	3	10	5000	1000	3000	2000	6000	29148	29119	1	1	61001	1000	1000	0	1000	0	2	1000	0	0	0	0	1000	2	1	3	0	0	13136	9452	6913	3175	0	59	20380	3093	3824	20	51	49	28434	1000	16122	13416	14344	1000	3000	1000	29368	29448	29230	29355	29314
64004	29432	227	0	2	0	0	3	0	0	1	0	0	2	0	0	0	4723	28942	0	0	17143	5003	1000	3003	1000	1000	3000	1000	5000	5000	35621	0	5	22823	29137	29395	3	10	5000	1000	3000	2000	6000	29192	29242	1	1	61001	1000	1000	0	1000	0	0	1000	0	0	0	0	1000	3	0	0	0	0	13145	9374	6907	3074	1	48	20318	3185	3825	15	51	54	28508	1000	16242	13473	14412	1000	3000	1000	29460	29287	29266	29391	29469
64004	29426	229	0	4	0	0	4	0	0	0	0	0	0	0	0	0	4634	28904	0	0	16977	5003	1000	3003	1000	1000	3000	1000	5000	5000	35806	0	4	22838	29192	29286	3	10	5000	1000	3000	2000	6000	29152	29255	1	1	61001	1000	1000	0	1000	0	0	1000	0	0	0	2	1000	2	1	2	0	0	13178	9292	6885	3144	0	53	20395	3206	3828	17	50	49	28577	1000	16335	13376	14252	1000	3000	1000	29415	29360	29342	29383	29329
64004	29243	228	0	2	0	0	2	0	0	1	0	0	2	0	0	0	4654	28802	0	0	17091	5003	1000	3003	1000	1000	3000	1000	5000	5000	35634	0	0	22801	29230	29267	3	10	5000	1000	3000	2000	6000	29135	29193	1	1	61001	1000	1000	0	1000	0	3	1000	0	0	0	1	1000	3	0	3	0	98	13290	9347	6973	3181	1	47	20577	3242	3823	11	59	52	28747	1000	16068	13330	14646	1000	3000	1000	29404	29506	29497	29542	29412
64004	29516	237	0	2	0	0	2	0	0	0	0	0	2	0	0	1	4715	28711	1	1	17152	5000	1000	3000	1000	1000	3000	1000	5000	5000	35727	0	17	22832	29123	29138	3	10	5000	1000	3000	2000	6000	29145	29087	1	1	61001	1000	1000	0	1000	0	3	1001	0	0	0	4	1001	2	1	2	0	0	13040	9213	6906	3156	1	57	20324	3210	3821	17	53	55	28330	1000	16315	13347	14298	1000	3000	1000	29172	29220	29268	29284	29294

Count: 8

Code:

  ld3 { v0.b, v1.b, v2.b }[1], [x6], x8
  ld3 { v0.b, v1.b, v2.b }[1], [x6], x8
  ld3 { v0.b, v1.b, v2.b }[1], [x6], x8
  ld3 { v0.b, v1.b, v2.b }[1], [x6], x8
  ld3 { v0.b, v1.b, v2.b }[1], [x6], x8
  ld3 { v0.b, v1.b, v2.b }[1], [x6], x8
  ld3 { v0.b, v1.b, v2.b }[1], [x6], x8
  ld3 { v0.b, v1.b, v2.b }[1], [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320206	160056	1199	0	0	0	0	0	0	0	0	34	0	1	0	0	160050	1	6	6	159887	25	400112	80100	240012	80000	80100	240000	80000	400634	400095	22792965	160040	160041	160059	79927	3	80047	400100	200	80000	240000	200	160000	481044	160059	160534	4	1	80201	100	99	100	100	80000	80000	1	100	80006	6	0	80029	0	0	1	28	80022	6	1	14	18	0	0	5110	0	1	17	1	1	160062	0	80000	0	13	80000	240000	80100	160066	160066	160067	160066	160066
320204	160065	1240	1	0	0	0	0	1	0	0	6	0	0	0	0	160044	1	0	6	159838	25	400100	80100	240000	80000	80100	240000	80000	480499	400096	22792965	160037	160059	160059	79924	3	80047	400100	200	80000	240000	200	160000	480000	160065	160065	1	1	80201	100	99	100	100	80000	80000	1	100	80063	6	27	80029	0	3	1	34	80025	6	1	28	27	6	1	5110	0	1	17	1	1	160056	0	80000	13	10	80000	240000	80100	160042	160060	160042	160060	160042
320204	160059	1240	0	0	0	0	1	1	0	0	21	0	0	0	0	160050	1	6	6	159887	25	400112	80100	240012	80000	80100	240000	80000	480499	400084	22794693	160046	160065	160065	79914	3	80023	400100	200	80000	240000	200	160000	480000	160059	160056	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80000	0	0	0	31	80014	6	1	14	18	0	0	5110	0	1	35	2	1	160062	0	80000	13	13	80000	240000	80100	160066	160066	160047	160066	160047
320204	160065	1241	1	1	0	1	0	0	0	0	65	0	0	0	0	160044	1	6	6	159876	25	400106	80100	240000	80000	80100	240000	80000	400634	400099	22792965	160037	160059	160059	79924	3	80048	400100	200	80000	240000	200	160000	480000	160046	160046	1	1	80201	100	99	100	100	80000	80000	0	100	80063	6	0	80028	0	0	0	28	80023	6	1	29	26	5	0	5110	0	1	17	2	1	160056	0	80058	10	10	80000	240000	80100	160060	160117	160060	160057	160060
320204	160472	1312	0	0	0	0	0	0	6	6	193	0	0	1	0	160031	1	6	6	159853	25	400112	80100	240006	80058	80100	240000	80000	480499	400112	22794693	160046	160065	160065	79933	3	80041	400100	200	80000	240000	200	160000	480000	160059	160056	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80015	0	1	0	973	80016	6	1	14	20	0	0	5110	0	1	17	2	1	160062	1	80058	16	13	80000	240000	80100	160047	160066	160066	160066	160047
320204	160067	1241	1	1	1	0	0	0	0	0	289	0	0	0	0	160026	1	6	0	159824	25	400106	80100	240006	80000	80100	240000	80000	480499	400088	22792965	160040	160059	160041	79909	3	80047	400100	200	80000	240000	200	160116	480000	160065	160065	1	1	80201	100	99	100	100	80000	80000	0	100	80006	6	27	80028	0	1	0	30	80023	6	1	29	27	5	0	5110	0	1	17	1	1	160056	1	80000	10	10	80000	240000	80100	160057	160060	160061	160057	160060
320204	160059	1241	0	0	1	0	0	0	0	0	22	0	0	1	1	160050	1	6	0	159853	25	400264	80100	240012	80000	80100	240000	80000	480499	400117	22794693	160047	160065	160065	79933	3	80015	400100	200	80000	240000	200	160000	480000	160057	160056	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80016	0	1	2	0	80016	6	1	13	20	0	2	5110	0	1	17	1	1	160062	1	80000	13	0	80000	240000	80100	160066	160066	160066	160066	160066
320204	160046	1241	1	0	0	0	0	0	0	1	33	0	0	1	0	160044	0	6	6	159873	25	400106	80100	240000	80000	80100	240168	80000	400634	400094	22789345	160040	160059	160041	79909	3	80047	400100	200	80000	240000	200	160000	480000	160065	160065	1	1	80201	100	99	100	100	80000	80000	0	100	80069	7	27	80028	0	1	1	991	80022	6	1	28	27	6	0	5110	0	1	17	1	1	160056	1	80058	13	0	80000	240000	80100	160118	160060	160060	160042	160060
320204	160059	1241	0	0	0	0	0	1	3	3	152	176	0	0	0	160228	1	6	6	159749	130	400568	80274	240156	80174	80274	240504	80174	426585	403034	22792163	160166	160297	160659	78858	35	80008	400952	200	80174	240522	200	160348	481044	160294	160237	3	1	80201	100	99	100	100	80000	80000	1	100	80116	0	18	80228	0	0	0	2910	80000	6	1	14	20	0	0	5110	0	1	17	1	1	160062	0	80000	13	13	80000	240000	80100	160066	160066	160066	160066	160066
320204	160065	1240	1	0	0	1	1	0	0	0	34	0	0	1	0	160026	1	6	6	159873	25	400106	80100	240006	80000	80100	240000	80000	480499	400093	22792965	160038	160059	160059	79924	3	80047	400100	200	80000	240000	200	160000	480000	160065	160066	1	1	80201	100	99	100	100	80000	80000	0	100	80005	6	27	80028	0	1	0	29	80000	6	1	28	27	6	0	5110	0	1	17	1	1	160056	1	80000	13	13	80000	240000	80100	160060	160057	160057	160060	160060

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	24	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	160301	1242	0	0	0	0	0	0	4	2	283	352	0	0	160040	1	6	6	159872	0	25	400016	80010	240006	80000	80010	240000	80000	480049	400090	22792716	0	1	160036	160055	160055	79909	3	80044	400010	20	80000	240000	20	160000	480000	160041	160041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	13	80013	0	0	3	80000	6	1	10	17	0	0	0	5020	5	17	4	6	160038	0	80000	0	6	80000	240000	80010	160056	160056	160056	160056	160056
320024	160055	1241	0	0	0	0	1	0	0	0	40	0	0	0	160040	1	0	6	159863	0	25	400016	80010	240000	80000	80010	240000	80000	480049	400090	22792716	0	1	160036	160041	160041	79923	3	80037	400010	20	80000	240000	20	160000	480000	160055	160055	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	13	80013	0	0	15	80010	0	1	14	0	0	0	0	5020	6	17	6	5	160052	1	80000	10	6	80000	240000	80010	160056	160056	160056	160056	160057
320024	160055	1242	0	0	0	0	0	0	0	0	19	0	0	0	160040	1	0	0	159873	0	25	400016	80010	240006	80000	80010	240000	80000	480049	400088	22792716	0	1	160036	160055	160055	79923	3	80023	400010	20	80000	240000	20	160000	480000	160055	160055	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80000	1	0	19	80013	6	1	13	0	0	0	0	5020	5	17	3	4	160038	1	80000	9	6	80000	240000	80010	160056	160057	160056	160056	160042
320024	160041	1240	0	0	0	0	0	0	0	0	18	0	0	0	160040	0	0	6	159872	0	25	400016	80010	240006	80000	80010	240000	80000	480049	400087	22792716	0	1	160022	160041	160055	79923	31	80037	400010	20	80000	240000	20	160000	480000	160055	160041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80000	0	0	13	80015	6	1	12	17	0	0	0	5020	8	17	9	6	160052	1	80000	9	9	80000	240000	80010	160042	160056	160056	160056	160042
320024	160055	1241	0	0	0	0	1	0	0	0	19	0	0	0	160026	1	0	6	159872	0	25	400016	80010	240006	80000	80010	240000	80000	480049	400082	22792716	0	1	160022	160055	160041	79909	3	80023	400010	20	80000	240000	20	160000	480000	160041	160055	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80000	0	0	0	80013	5	0	12	17	0	0	0	5020	6	17	4	5	160052	0	80000	0	0	80000	240000	80010	160056	160056	160056	160056	160056
320024	160055	1240	0	0	0	0	0	0	0	0	19	0	0	0	160040	1	6	0	159872	0	25	400016	80010	240006	80000	80010	240000	80000	480049	400092	22792716	1	1	160036	160055	160055	79923	3	80037	400010	20	80000	240000	20	160000	480000	160041	160055	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	17	80013	1	0	16	80013	6	1	0	17	0	0	0	5020	5	17	6	7	160052	0	80000	9	10	80000	240000	80010	160056	160056	160042	160056	160056
320024	160055	1240	0	0	0	0	0	0	0	0	31	0	0	0	160041	1	6	6	159872	0	25	400016	80010	240006	80000	80010	240000	80000	480049	400084	22790859	0	1	160022	160055	160055	79923	3	80037	400010	20	80000	240000	20	160000	480000	160055	160055	1	1	80021	10	9	10	10	80000	80000	0	10	80228	2	0	80128	0	2	2880	80184	0	0	12	17	0	2	0	5171	8	260	5	6	160301	0	80116	9	6	80000	240000	80010	160177	160296	160234	160294	160232
320024	160172	1243	0	1	0	0	1	1	2	4	619	176	0	0	160026	1	6	6	159872	0	25	400010	80010	240006	80000	80010	240000	80000	480049	400090	22792716	0	1	160036	160055	160055	79923	3	80037	400010	20	80000	240000	20	160000	480000	160055	160055	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	13	80012	0	0	1938	80073	6	0	0	17	0	0	1	5020	6	17	4	6	160052	1	80000	9	6	80000	240000	80010	160042	160056	160042	160056	160056
320024	160055	1241	0	0	0	0	1	0	0	0	34	0	0	0	160040	1	6	6	159872	0	25	400016	80010	240006	80000	80010	240000	80000	480049	400088	22789345	0	1	160036	160055	160055	79923	3	80037	400010	20	80000	240000	20	160000	480000	160057	160055	1	1	80021	10	9	10	10	80000	80000	0	10	80116	0	13	80067	0	0	9	80012	6	0	0	17	0	0	0	5020	5	17	7	8	160052	1	80000	0	6	80000	240000	80010	160056	160056	160113	160056	160056
320024	160055	1240	0	0	0	0	0	0	0	0	21	0	0	0	160040	1	6	0	159872	0	25	400010	80010	240006	80000	80010	240000	80000	480049	400082	22792716	0	1	160043	160062	160065	79930	3	80044	400010	20	80000	240000	20	160000	480000	160062	160062	1	1	80021	10	9	10	10	80000	80000	0	10	80008	7	22	80024	0	0	23	80018	6	1	25	24	6	0	0	5020	6	17	6	5	160059	1	80000	10	10	80000	240000	80010	160063	160118	160063	160063	160063

LD3 (single, post-index, B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations