Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD3 (single, post-index, H)

Test 1: uops

Code:

  ld3 { v0.h, v1.h, v2.h }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.003

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.003

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)09l2 tlb miss instruction (0a)0f1e223a3f43464951schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f6061696b6d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd load (98)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
6400528491213131126131506728328000161335003100030031000100030001000500050003563720002282432816328282310500010003000200060002807028175116100110001000010000210000001001200139861004470793364166819295339138071665702785210001524111971127491000300010002838628239282712852928235
640042837121302502103050822804610016102500310003000100010003000100050005000356681500228680282072843731050001000300020006000281552825711610011000100001000021001024100021313893105207094342595719194342838081667702792610001514512114126331000300010002831528389284782827928408
640042832821102302700052232801600016104500310003003100010003000100050005000356961000228540279972822431050001000300020006000282172827211610011000100011000001000000100121214006105497190341486819203335438091867692788510001526611759125771000300010002817028319281582836028327
640042820621202502302052252803601016041500310003003100010003000100050005001356335002283402823728260310500010003000200060002804028027116100110001000110000210010001001103137131010172673421107219130340838081656632798010001442412345128461000300010002845428338283462834228256
6400428449212026019015050772805201015873500310003003100010003000100050005000357032410229020281802811731050001000300020006000281712833811610011000100001000001001000100100213938100587069355297019271337238021663722786210001504212398127531000300010002853828059285082856528492
6400428437212020023030521728036010160175003100030001000100030001000500050003570112002286802807428317310500010003000200060002811028268116100110001000010000210010011000100139771017072103472116719439340238001572642792510001452612285131501000300010002822428095283282815328280
6400428339212022020030510028029010162345003100030031000100030001000500050013563218102279702819428087310500010003000200060002806728125116100110001000010000210001041000100138571027271683283116419275336538041868622788110001477812171128241000300010002822428182283552831328227
6400428329212022021000519828200000161785003100030031000100030001000500050003569221002280102807528457310500010003000200060002825228058116100110001000110000010010011003012138221046771713453106219290332337991667692787510001454012366127401000300010002820428356282112834228242
6400428290212017022031503927988011161605003100030061000100030001000500050013570823002278902800428197310500010003000200060002820128360116100110001000010000210010001000002138741026171853445126619246345838131567682794810001459712164128391000300010002809428272282452822528324
6400428334213024020030521828196010159815003100030001000100030001000500050003574822002280802825628205310500010003000200060002831928279116100110001000010000210012011001012138541034172423410116619367329838032167652796210001459312445128831000300010002813128287283602841128117

Test 2: throughput

Count: 8

Code:

  ld3 { v0.h, v1.h, v2.h }[1], [x6], x8
  ld3 { v0.h, v1.h, v2.h }[1], [x6], x8
  ld3 { v0.h, v1.h, v2.h }[1], [x6], x8
  ld3 { v0.h, v1.h, v2.h }[1], [x6], x8
  ld3 { v0.h, v1.h, v2.h }[1], [x6], x8
  ld3 { v0.h, v1.h, v2.h }[1], [x6], x8
  ld3 { v0.h, v1.h, v2.h }[1], [x6], x8
  ld3 { v0.h, v1.h, v2.h }[1], [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0008

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2223243a3e3f404346494e5051schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)daddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
320205160065128611101100463521000016005001661598870254001128015824001280000801002400008000048049940010522794693016004601601231600657993303800474001002008000024000020016000048000016006516004611802011009910010080000800000100801177278003000029800236129266151101170111600621800001308000024000080100160066160066160066160066160066
320204160068128510210000350100001600500106159887625400112801592400128000080158240000800004804994001072279076601600460160046160046799330380047400100200800002400002001600004800001600651600651180201100991001008000080000010080005608002901128800236152761511011701116006218000013168000024000080100160066160066160066160047160047
3202041600651286100000005001000160050016615988702540011280100240012800008010024000080000480499400116227946930160046016006516006679933038004740010020080000240000200160000480000160046160046118020110099100100800008000001008000752680031000318002301280515110117014160062180000008000024000080100160066160066160066160066160066
32020416006512861110000064001000160050016615988702540011280100240012800008010024000080000480499400109227946930160046016006516006579933038004740010020080000240000200160000480000160065160046118020110099100100800008000001008000762780028001288002361292750511011701116006208000014138000024000080100160066160069160066160066160066
320204160065128611010000440010001600500166159887052340011280100240012800008010024000080000480499400105227946930160046016006516004679933038004740010020080000240000200160000480000160065160123118020110099100100800008000001008000552780030010288000061292760512311701116006218005813148000024000080100160125160067160066160066160066
32020416006512861000010034001000160050016615983702540011280100240012800008010024000080000480499401058227946930160046016006516006679933038004740010020080000240000200160000480000160065160046118020110099100100800008000011008000653080086000288002261312751511011701116006218000013138000024000080100160066160047160047160047160126
3202041600651286100111004900100016005000061598870254001128010024001280000801582400008000048049940011522794693016004601600651600657993303800474001002008000024000020016000048000016004616006511802011009910010080000800000100800055278002900028800226152751511011701116008408000013138000024000080100160066160047160068160066160047
3202041600651286101000003400000016005001661598530784004168021624007880174802162405048017440969740300722787422016008601600651601047990001580033400670200813932403482001603484806961601841601864180201100991001008000080000010080180527801411001953802516129060514914401116018518023213138000024000080100160066160066160066160066160066
320204160065128611110000127000000160051016615988704940011280100240012800008010024000080000480499400105227952150160046016006516006579933038004740010020080000240000200160000480000160065160065118020110099100100800008000001008000653280028001288002361282750511011701116004318000013168000024000080100160066160066160066160047160066
320204160065128611001000673001000160053010615988702540011280100240012800008010024000080000480499400112227946930160047016006616006579933038004740010020080000240000200160000480000160065160065118020110099100100800008000001008000762680028010298002161292760511011701116006218000013138000024000080100160047160066160066160066160047

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f22233a3f4346494e4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)c2branch cond mispred nonspec (c5)c9branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
320025160055124101000000881001600261661598380254000108006824000680000800712400008000040018440008222792716016003616005516005579909038003740001020800002400002016000048000016005516005511800211091010800008000001080000013800121013800125111170000502041744160052080000968000024000080010160042160056160042160042160056
3200241600551240000110015000016004017015987202540001680010240006800008001024016880000480049400087227927160160036160055160041799230380023400010208000024017420160000480000160055160041118002110910108000080000010800000080010001380010511000000502051754160052080000968000024000080010160056160056160055160042160056
32002416005512400001110360000160099166159872025400016800102400068000080010240000800004246084000882279271601600371600551600557990903800374000102080000240000201600004800001600981600551180021109101080000800000108000001380012101680010600130000502051746160038080000068000024000080010160056160056160056160042160056
32002416004112400000000310000160040166159872025400016800102400068000080010240000800584800494000822279275801600361600551600567992303800374000102080058240000201600004800001600551600551180021109101080000800000108000001380010001080013011000000502062635160052080000668000024000080010160099160042160042160056160065
32002416004112410000000190100160040166159872025400016800102400068005880010240000800004800494000812279259701600351600541600997992303800374000102080000240000201600004800001600551600541180021109101080000800000108000001380014101382808519130000502041734160052180000068000024000080010160056160056160056160056160056
3200241600551241010000000000160040166159838025400016800102400068005880010240000800004800494000902279271601600931600411601147992303800374000102080000240000201600004800001600551600551180021109101080000800000108000001380010001380000510170000502051776160052080000068000024000080010160042160056160056160056160056
3200241600551241000000015000001600401601598380254000168001024000680000800102400008000048004940008422792716016007616005516005579923016800374000102080000240000201600004800001601131600551180021109101080000800000108000001380009103800105113139000502051736160052180000968000024000080010160042160056160056160042160056
3200241601141241000000016000016002610615982502540001680010240006800008001024000080000480049401029227927160160036160055160055799230380037400010208000024000020160000480000160055160055118002110910108000080000110800000178000000973800096110132000507345395160161180174098000024000080010160235160234160220160235160176
32002416021812430100034355462640001602181601597720127400624801842401508005880010240000800004001844000892279271601600361600411600417992303800374000102080000240000201600004800001600541600551180021109101080000800000108000001780013103800135110170000502061744160052180000968000024000080010160056160042160042160056160056
320024160041124100010001500001600401001598660254000168001024000680000800102400008000048004940008322792716016003616005516005579923038003740001020800002400002016000048000016005516004111800211091010800008000001080000017800130013800130010170000502031754160052180000668000024000080010160056160056160056160056160042